METHOD OF DISTRIBUTING METAL LAYERS IN A POWER DEVICE

Abstract

A metal distributing method of a FET (Field Effect Transistor) device, having: depositing a first dielectric layer on a planar silicon surface; etching a first level metal layer pattern in the first dielectric layer; filling in a first level metal layer in openings determined by the first level metal layer pattern; depositing a second dielectric layer on the first dielectric layer and the first level metal layer; etching a second level metal layer pattern in the second dielectric layer; and filling in a second level metal layer in openings determined by the second level metal layer pattern; the first level metal layer and the second level metal layer are contacted directly, with no via layer in between.

Claims

1. A metal distributing method for a FET (Field Effect Transistor) device, comprising: depositing a first dielectric layer on a planar silicon surface; etching a first level metal layer pattern in the first dielectric layer; filling in a first level metal layer in openings determined by the first level metal layer pattern; depositing a second dielectric layer on the first dielectric layer and the first level metal layer; and etching a second level metal layer pattern in the second dielectric layer; filling in a second level metal layer in openings determined by the second level metal layer pattern; wherein the first level metal layer and the second level metal layer are contacted directly, with no via layer in between, and wherein a contact surface of the first level metal layer and the second level metal layer is a planar surface, and is coplanar with top surfaces of the first dielectric layer, and wherein for each contacted first level metal layer and second level metal layer, the first level metal layer is covered by the second level metal layer.

2. The metal distributing method of claim 1, wherein both depositing the first dielectric layer and depositing the second dielectric layer comprise: depositing an etch-stop layer; depositing a silicon dioxide layer on the etch-stop layer; and depositing a silicon oxynitride layer on the silicon dioxide layer.

3. The metal distributing method of claim 2, wherein both etching the first level metal layer pattern in the first dielectric layer and etching the second level metal layer pattern in the second dielectric layer comprise: forming a photoresist layer to a targeted dielectric layer; patterning the photoresist layer to expose the targeted dielectric layer; etching away the targeted dielectric layer through openings of the photoresist layer; and removing the photoresist layer.

4. The metal distributing method of claim 2, wherein the etch-stop layer comprises silicon nitride.

5. A FET (Field Effect Transistor) device, comprising: a first dielectric layer on a planar silicon surface; a first level metal layer damascened in the first dielectric layer; a second dielectric layer on the first dielectric layer and the first level metal layer; and a second level metal layer damascened in the second dielectric layer; wherein the first level metal layer and the second level metal layer are contacted directly, with no via layer in between, and wherein a contact surface of the first level metal layer and the second level metal layer is a planar surface, and is coplanar with top surfaces of the first dielectric layer, and wherein for each contacted first level metal layer and second level metal layer, the first level metal layer is covered by the second level metal layer.

6. The FET device of claim 5, wherein the first dielectric layer and the second dielectric layer comprises: an etch-stop layer; a silicon dioxide layer on the etch-stop layer; and a silicon oxynitride layer on the silicon dioxide layer.

7. The FET device of claim 6, wherein the etch-stop layer comprises silicon nitride.

8. The FET device of claim 6, wherein a thickness of the etch-stop layer is less than 150 nm.

9. The FET device of claim 6, wherein a thickness of the silicon oxynitride layer is less than 150 nm.

10. The FET device of claim 5, wherein a thickness of the first level metal layer is in a range of 0.12 μm-0.38 μm.

11. The FET device of claim 5, wherein a minimum width of lines of the first level metal layer is 0.12 μm.

12. The FET device of claim 5, wherein a minimum space between lines of the first level metal layer is 0.12 μm.

13. The FET device of claim 5, wherein a thickness of the second level metal layer is 0.9 μm˜1.5 μm.

14. The FET device of claim 5, wherein a minimum width of lines of the second level metal layer is 0.9 μm.

15. The FET device of claim 5, wherein a minimum space between lines of the second level metal layer is 0.5 μm.

16. A FET (Field Effect Transistor) device, comprising: a first level metal layer, patterned to be connected to a source contact and a drain contact, wherein areas of the first level metal layer connected to the source contact are separated from areas of the first level metal layer connected to the drain contact; and a second level metal layer, patterned to be directly contacted to the first level metal layer, with no via layer in between, wherein areas of the second level metal layer electrically connected to the source contact via the first level metal layer are separated from areas of the second level metal layer electrically connected to the drain contact via the first level metal layer, and wherein a contact surface of the first level metal layer and the second level metal layer is a planar surface, and is coplanar with top surfaces of the first dielectric layer, and wherein for each contacted first level metal layer and second level metal layer, the first level metal layer is covered by the second level metal layer.

17. The FET device of claim 16, wherein a thickness of the first level metal layer is in a range of 0.12 μm˜0.38 μm.

18. The FET device of claim 16, wherein a minimum width of lines of the first level metal layer is 0.12 μm.

19. The FET device of claim 16, wherein a thickness of the second level metal layer is in a range of 0.9 μm˜1.5 μm.

20. The FET device of claim 16, wherein a minimum width of lines of the second level metal layer is 0.9 μm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The present invention can be further understood with reference to the following detailed description and the appended drawings, wherein like elements are provided with like reference numerals. The drawings are only for illustration purpose. They may only show part of the devices and are not necessarily drawn to scale.

[0012] FIG. 1 schematically shows a top view of a prior art power FET 10 with first level metal layer.

[0013] FIG. 2 schematically shows a cross section view of a prior art power FET 20 with two level metal layers.

[0014] FIG. 3 shows a cross section view of a FET device 30 in accordance with an embodiment of the present invention.

[0015] FIG. 4 shows a top view of the FET device 30 in FIG. 3 in accordance with an embodiment of the present invention.

[0016] FIG. 5A˜H shows a metal distributing process of the FET device 30 in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION

[0017] Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention.

[0018] The terms “left,” right,” “in,” “out,” “front,” “back,” “up,” “down, “top,” “atop”, “bottom,” “over,” “under,” “beneath,” “above,” “below” and the like in the description and the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that embodiments of the technology described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

[0019] FIG. 3 shows a cross section view of a FET device 30 in accordance with an embodiment of the present invention. As shown in FIG. 3, the FET device comprises: a first dielectric layer 301 on an underlying planar silicon surface 303; a first level metal layer M1 damascened in the first dielectric layer 301; a second dielectric layer 302 on the first dielectric layer 301 and the first level metal layer M1; and a second level metal layer M2 damascened in the second dielectric layer 302.

[0020] The cross section view in FIG. 3 shows part of the power FET 30 for illustration, not the whole device. The power FET 30 may have a large extension with drain and source alternating distributed.

[0021] In FIG. 3, the first dielectric layer 301 is patterned by a masking step to define the location of the first level metal layer M1. And in the same way, the second dielectric layer 302 is patterned by a masking step to define the location of the second level metal layer M2. As shown in FIG. 3, the first level metal layer M1 comprises stripes (lines) M12 and M11 respectively connected to the source contact SC and the drain contact DC, wherein the stripe M12 and the stripe M11 are spaced away. Similarly, the second level metal layer M2 comprises stripes M22 and M21 respectively connected to the stripes M12 and M11, wherein the stripe M22 and the stripe M21 are spaced away.

[0022] In the prior art power FET 20 shown in FIG. 2, a via layer V1 is deposited on the first dielectric layer. However, in the present invention, as shown in FIG. 3, a main, thick, copper interconnect layer, i.e., the second level metal layer M2 instead of the via layer V1, is distributed on the first dielectric layer 301, and has direct contact to the first level metal layer M1, which means the first level metal layer M1 and the second level metal layer M2 are contacted directly, with no via layer in between. The thickness of the second dielectric layer 302 may be the maximum compatible with the metal pitch, which is set by the underlying power FET pitch.

[0023] FIG. 4 shows a top view of the FET device 30 in FIG. 3 in accordance with an embodiment of the present invention. As shown in FIG. 4, the stripe M12 of the first level metal layer M1 covers the source contact SC and has an extension at stripe ends to overlap an end of the field plate contact FPC, connecting the field plate contact FPC to a source potential (not shown in FIG. 4). Except the stripe end, there is no first level metal layer over the field plate contact FPC, and the field plate contact FPC is isolated from the overlying second level metal stripe M21 connecting to the drain contact DC. In FIG. 4, area of the second level metal layer M2, i.e., M22, electrically connected to the source contact SC via the first level metal layer M1, i.e., M12, is separated from area of the second level metal layer M2, i.e., M21, electrically connected to the drain contact DC via the first level metal layer M1, i.e., M11, to avoid short of the source and drain of the FET device 30.

[0024] In one embodiment, a thickness of the first level metal layer M1 could be in a range of 0.12 μm ˜0.38 μm, and has both a minimum line width and a minimum space between lines of 0.12 μm, making its minimum pitch 0.24 μm.

[0025] In one embodiment, a thickness of the second level metal layer M2 could be in a range of 0.9 μm-1.5 μm, having a minimum line width of 0.9 μm and a minimum space between lines of 0.5 μm, making its minimum pitch 1.4 μm.

[0026] In one embodiment, the thick second level metal layer M2 may be covered by passivation and then connected to overlying thick copper RDL (“ReDistribution Layer”) using holes etched in the passivation. The thick copper RDL may be covered by passivation and then contacted using wire bonding to bond pad openings outside the FET device. In one embodiment, the thick second level metal layer M2 may be followed by further via layers and interconnect. In all cases, one masking step is saved by the elimination of the via layer V1 between the first level metal layer M1 and the second level metal layer M2.

[0027] FIG. 5A˜H shows a metal distributing process of a FET device in accordance with an embodiment of the present invention.

[0028] As shown in FIG. 5A, an etch-stop layer 501 is deposited on the underlying silicon surface 303. In one embodiment, the etch-stop layer 501 comprises silicon nitride. In one embodiment, the thickness of the etch-stop layer 501 is in a range of 50 nm˜150 nm.

[0029] In FIG. 5B, a silicon dioxide layer 502 is deposited on the etch-stop layer 501. The silicon dioxide layer 502 is much thicker than the etch-stop layer 501, and a thickness of the silicon dioxide layer 502 is decided by the thickness requirement of the first level metal layer M1.

[0030] In FIG. 5C, a silicon oxynitride layer 503 is deposited on the silicon dioxide layer 502. In one embodiment, the thickness of the silicon oxynitride layer 503 is in a range of 50 nm˜150 nm. The etch-stop layer 501, the silicon dioxide layer 502 and the silicon oxynitride layer 503 constitute the first dielectric layer 301.

[0031] In FIG. 5D, a photoresist layer 510 is deposited on the silicon oxynitride layer 503, and is patterned to define the location of the first level metal layer M1.

[0032] In FIG. 5E, the first dielectric layer 301 is etched through the openings of the photoresist layer 510. In one embodiment, the silicon dioxide layer 502 and the silicon oxynitride layer 503 are etched through openings of the photoresist layer 510 first, and then the photoresist layer 510 is removed. After that, the etch-stop layer 501 is etched through the openings of the silicon dioxide layer 502 and the silicon oxynitride layer 503.

[0033] In FIG. 5F, the first level metal layer M1 is filled in the openings left after etching the first dielectric layer. In one embodiment, the first level metal layer M1 comprises copper. In other embodiments, the first level metal layer M1 may comprise conductive materials like Tin, Nickle, Lead or Aluminum. In one embodiment, filling copper into the openings of the first dielectric layer comprises successively depositing metal barrier layer and copper seed layer, and then plate copper to the whole underlying surface.

[0034] In FIG. 5G, a chemical mechanical polishing is performed to the surface to remove the unnecessary metal to obtain a planar surface at a level of the first dielectric layer.

[0035] In FIG. 5H, the second dielectric layer 302 is deposited on the underlying surface in a same way that the first dielectric layer 301 is deposited, which comprises depositing an etch-stop layer 504, a silicon dioxide layer 505 and a silicon oxynitride layer 506 successively. The thickness of the silicon dioxide layer 505 is decided by the thickness requirement of the second level metal layer M2. Persons of ordinary skill in the art could decide the thickness of the second level metal layer according to the application requirement. Also, in FIG. 5H, the second dielectric layer 302 is patterned and etched to be filled in with the second level metal layer M2 in the same way that the first level metal layer M1 is formed, and is not illustrated step by step for brevity.

[0036] The values of the aforementioned thickness of the metal layers, the line widths of metal lines, the spaces between metal lines, the pitches of the metal stripes are ideal. In real device, the process design rule allows a ±50% deviation from the target spec.

[0037] In some embodiments, the dielectric layer may comprise other suitable materials known to persons of ordinary skill in the art.

[0038] Obviously many modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described. It should be understood, of course, the foregoing disclosure relates only to a preferred embodiment (or embodiments) of the invention and that numerous modifications may be made therein without departing from the spirit and the scope of the invention as set forth in the appended claims. Various modifications are contemplated and they obviously will be resorted to by those skilled in the art without departing from the spirit and the scope of the invention as hereinafter defined by the appended claims as only a preferred embodiment(s) thereof has been disclosed.