Stack-like III-V semiconductor product and production method

Abstract

A stack-like III-V semiconductor product comprising a substrate and a sacrificial layer region arranged on an upper side of the substrate and a semiconductor layer arranged on an upper side of the sacrificial layer region. The substrate, the sacrificial layer region and the semiconductor layer region each comprise at least one chemical element from the main groups III and a chemical element from the main group V. The sacrificial layer region differs from the substrate and from the semiconductor layer in at least one element. An etching rate of the sacrificial layer region differs from an etching rate of the substrate and from an etching rate of the semiconductor layer region at least by a factor of ten. The sacrificial layer region is adapted in respect of its lattice to the substrate and to the semiconductor layer region.

Claims

1. A stack-like III-V semiconductor product comprising: a substrate; a sacrificial layer region arranged on the substrate; and a semiconductor layer region arranged on a surface of the sacrificial layer region, wherein the substrate, the sacrificial layer region and the semiconductor layer region each comprise at least one chemical element from the main group Ill and one chemical element from the main group V, wherein at least a portion of the sacrificial layer region differs in at least one element from the substrate and from a portion of the semiconductor layer region arranged directly on the surface of the sacrificial layer region, wherein an etching rate for a predetermined etching process at least for a portion of the sacrificial layer region differs by at least a factor of 10 from the etching rate for the substrate as well as from the etching rate for the portion of the semiconductor layer region arranged directly on the surface of the sacrificial layer region, and wherein the sacrificial layer region comprises an at least partially amorphized layer produced by implantation, wherein the at least partially amorphized layer is arranged adjacent a center or in the center of the sacrificial layer region, and wherein the sacrificial layer region comprises three sacrificial layers and two outer layers of the three sacrificial layers include InGaAs or AlAs or GaInP or AlGaAs or consist of InGaAs or AlAs or GaInP or AlGaAs and a center sacrificial layer comprises or consists of GaAs.

2. The stack-like III-V semiconductor product according to claim 1, wherein the etching rates differ by at least a factor of 100 or at least a factor of 1000.

3. The stack-like III-V semiconductor product according to claim 1, wherein the sacrificial layers of the sacrificial layer region are arranged on top of one another in stacks.

4. The stack-like III-V semiconductor product according to claim 1, wherein at least a portion or the entire sacrificial layer region has a lattice constant adapted to the substrate and to at least a portion of the semiconductor layer region.

5. The stack-like III-V semiconductor product according to claim 1, wherein the amorphized layer is arranged in the center of the sacrifice layer region.

6. The stack-like III-V semiconductor product according to claim 1, wherein the sacrificial layer region includes a first sacrificial layer and a second sacrificial layer and a third sacrificial layer.

7. The stack-like III-V semiconductor product according to claim 1, wherein the sacrificial layer region comprises exactly three sacrificial layers.

8. The stack-like III-V semiconductor product according to claim 1, wherein the sacrificial layer region has a layer thickness of 0.1 μm-10 μm or 1 μm-3 μm.

9. The stack-like III-V semiconductor product according to claim 1, wherein the substrate is formed of GaN or of GaAs or of InP.

10. The stack-like III-V semiconductor product according to claim 1, wherein the semiconductor layer region has a layer thickness of 0.3 μm-30 μm or 1 μm to 5 μm.

11. A III-V semiconductor product production method, the method comprising: providing a substrate; producing a sacrificial layer region on the substrate, the sacrificial layer region being lattice adapted to the substrate; producing an at least partially amorphized layer within the sacrificial layer region by implantation; producing a semiconductor layer region, wherein the substrate, the sacrificial layer region and the semiconductor layer region comprise at least one chemical element selected from the main group Ill and one chemical element from the main group V; stripping the substrate from the semiconductor layer region along the sacrificial layer region; stripping a portion of the sacrificial layer region remaining on the substrate and on the semiconductor layer region via an etching process, wherein an etching rate at least for a portion of the sacrificial layer region differs by at least a factor of 10 from the etching rate for the substrate as well as from the etching rate for the portion of the semiconductor layer region arranged directly on the surface of the sacrificial layer region, wherein the at least partially amorphized layer is arranged adjacent a center or in the center of the sacrificial layer region, and wherein the sacrificial layer region comprises three sacrificial layers and two outer layers of the three sacrificial layers include InGaAs or AlAs or GaInP or AlGaAs or consist of InGaAs or AlAs or GaInP or AlGaAs and a center sacrificial layer comprises or consists of GaAs.

12. The III-V semiconductor product production method according to claim 11, wherein at least a portion of or the entire sacrificial layer region is lattice adapted to at least a portion of the semiconductor layer region.

13. The III-V semiconductor product production method according to claim 11, wherein the amorphized layer is formed in the center of the sacrificial layer region.

14. The III-V semiconductor product production method according to claim 11, wherein the amorphized layer is produced using a proton beam.

15. The III-V semiconductor product production method according to claim 11, wherein implantation is carried out with an energy in a range between 20 keV and 500 keV and a dosage is between 1e14 N/cm.sup.2 and 1e16 N/cm.sup.2.

16. The III-V semiconductor product production method according to claim 11, wherein the stripping is mechanically initiated and is performed in the portion of the sacrificial layer region.

17. The III-V semiconductor product production method according to claim 11, wherein, prior to stripping, a carrier layer is arranged on an upper side of the semiconductor layer region.

18. The III-V semiconductor product production method according to claim 11, wherein, after stripping, the semiconductor layer region and the surface freed from sacrificial layer region residues are arranged on a carrier.

19. The III-V semiconductor product production method according to claim 11, wherein, after stripping, portions of the sacrificial layer region remaining on the substrate are stripped and the substrate is made available for reuse.

20. The III-V semiconductor product production method according to claim 11, wherein the semiconductor layer region is cohesively arranged on a carrier substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitive of the present invention, and wherein:

(2) FIG. 1 is a view of an embodiment of a III-V semiconductor according to the invention,

(3) FIG. 2 is a view of an embodiment of a production method according to the invention,

(4) FIG. 3 is a view of an embodiment of an IR-LED structure in each case prior to stripping,

(5) FIG. 4 is a view of an embodiment of an ILM lattice-matched double solar cell structure, and

(6) FIG. 5 is a view of an embodiment of an IMM four-junction solar cell prior to stripping.

DETAILED DESCRIPTION

(7) The illustration in FIG. 1 shows an embodiment of a III-V semiconductor product 10, comprising a GaAs wafer as a substrate 12, a sacrificial layer region 14 comprising an AlGaAs layer, and a semiconductor layer region 16 comprising a GaAs layer. The sacrificial layer region 14 comprises an at least partially or completely amorphized layer 18 produced by implantation. In an embodiment, the sacrificial layer region 14 comprises exactly two semiconductor layers or exactly three semiconductor layers. The amorphized layer 18 allows for simple separation of the semiconductor layer region 16 from the substrate 12.

(8) It should be noted that instead of a GaAs semiconductor wafer, a GaN semiconductor wafer or an InP semiconductor wafer or another III-V semiconductor wafer can also be used as a substrate 12. Instead of a wafer made of InP, in an embodiment, the substrate 12 comprises a layer of InP only on the surface of a GaAs wafer. Such a structure is also referred to as a virtual substrate. An advantage is that this way mechanical stability can be increased and considerable costs saved.

(9) The chemical composition and the stoichiometry of the sacrificial layer region is preferably chosen in accordance with the substrate 12, so that the sacrificial layer region can preferably be formed adapted in respect of its lattice to the respective substrate 12, and, with regard to a subsequent etching process, can preferably be stripped particularly selectively with respect to the sacrificial layer region 14 and the substrate 12.

(10) The illustration in FIG. 2 shows an embodiment of a III-V semiconductor product production method according to the invention. A sacrificial layer region 14 with a first sacrificial layer 14.2 and a second sacrificial layer 14.4 and a third sacrificial layer 14.6 is produced on the carrier 12 by epitaxy.

(11) Within the second sacrificial layer 14.4, the at least partially or completely amorphized layer 18 is produced by implantation. Here, the implantation step can be carried out both immediately after production of the second sacrificial layer 14.4 and after production of the third sacrificial layer.

(12) The semiconductor layer region 16 is then grown, preferably epitaxially, on the sacrificial layer region 14.

(13) In an embodiment, the semiconductor layer region 16 comprises several or a plurality of semiconductor layers according to an intended application. The semiconductor layers are preferably arranged on top of one another in the form of an epitaxial stack.

(14) In particular, the semiconductor layers can be readily used for, for example, a GaN-HEMT or GaN-LED or for the formation of a multi-junction solar cell, in particular an inverted metamorphic multi-junction solar cell.

(15) To form an IMM solar cell, as compared to conventional solar cells, the semiconductor layers are grown inverted with respect to the order of the band gaps.

(16) Subsequently, the upper side of the semiconductor layer region 16 is cohesively connected to a carrier layer 20.

(17) Provided that the semiconductor layer region 16 is thin, i.e. mechanically unstable, or also for other reasons, the application of the carrier layer 20 is preferably advantageous.

(18) Subsequently, the sacrificial layer region 14 is mechanically notched laterally by means of a tool 22, preferably at the level of the amorphized layer 18, and the semiconductor layer region 16 is separated by the carrier layer 20 from the substrate 12 along the sacrificial layer region 14.

(19) In an embodiment, a circumferential edge region of the sacrificial layer portion 14 is stripped again after the formation of the amorphized layer 18 and/or after the formation of further semiconductor layers, but prior to stripping by an etching process, so that the layer stack has a recessed step 18 in the sacrificial layer region 14.

(20) After stripping, portions of the sacrificial layer region 14 remain on both the substrate 12 and the semiconductor layer region 16.

(21) The remaining portions of the sacrificial layer region 14 are stripped by etching the support layer 12 and the semiconductor layer region 16 (shown as a dashed line only for the portion of sacrificial layer region 14 remaining on the semiconductor layer region 16).

(22) In a further development, after complete stripping of the sacrificial layer region 14 from the underside of the semiconductor layer region 16, the underside of the semiconductor layer region 16 is at least force-fittingly arranged on a carrier 24 and the carrier layer 20 is stripped.

(23) Preferably, in arranging the semiconductor layer region 16 on a carrier 24, for example by wafer bonding or by metal bonding, the semiconductor layer region 16 is cohesively connected to a carrier 24.

(24) After stripping the sacrificial layer region 14 residue from the substrate 12, the substrate 12 is available for re-epitaxy.

(25) The illustration in FIG. 3 shows an embodiment of an IR-LED structure prior to being stripped. In the embodiment, on the substrate 12 formed as GaAs, a sacrificial layer 14 is made from AlGaAs and then an amorphized layer is produced in the center of the sacrificial layer 14 by implantation. A semiconductor region 16 comprising an IR-LED layer structure IRL is then epitaxially produced.

(26) Hereafter, a full-surface metallic layer M1 is deposited on the upper side of the stack.

(27) The illustration in FIG. 4 shows an embodiment of an ILM lattice-matched double solar cell structure prior to stripping. The semiconductor region 16 comprises a first subcell GAlP with GaInP and a second subcell GA2 with GaAs formed on a sacrificial layer GA made of GaAs.

(28) In an embodiment, between the first subcell GAlP and the GaAs sacrificial layer, a further sacrificial layer is formed of AlInGaP. It is advantageous that the further sacrificial layer made of AlInGaP has a wet chemical selectivity to the GaAs sacrificial layer.

(29) Both solar subcells and the sacrificial layer are adapted in respect of their lattice to the substrate and are monolithically stacked. It is understood that a tunnel diode is formed between the two solar subcells and the GaInP subcell has a larger band gap than the GaAs subcell. The metallic layer M1 or a semiconductor mirror is formed on the upper side.

(30) In the embodiment shown in FIG. 5, an IMM four-junction solar cell structure is shown prior to stripping. Only the differences from the embodiment shown in FIG. 4 are explained below. The semiconductor region 16 comprises four solar subcells S1 to S4. It is understood that in each case a tunnel diode is formed between the individual solar subcells and the S1 subcell has a larger band gap than the S2 subcell and the S2 subcell has a larger band gap than the S3 subcell and the S3 subcell has a larger band gap than the S4 subcell. The solar subcells S1 to S4 are preferably monolithic.

(31) The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are to be included within the scope of the following claims.