Three level PWM class D amplifier

Abstract

A Class D amplifier comprising a control circuit configured to receive an audio input signal and derive first, second and third PWM switching control signals therefrom, being supplied to respectively first, second and third switches of a driver, the first and second switches being serially arranged between first and second supply voltages, and having a common node coupled to an output terminal. The driver comprises a DC level shifter being configured to provide a reference voltage to a reference terminal in at least first and second states of operation, said reference voltage including a DC component at least substantially equidistant between the first and second supply voltages. Said third switch being included in a shunt path between the output and the reference terminal.

Claims

1. A three level Class D amplifier comprising a control circuit configured to receive an analog input signal and derive therefrom first, second and third PWM switching control signals being supplied to respectively first, second and third switches of a driver to obtain a three level PWM single ended output signal between an output terminal and a reference terminal, the first and second switches being serially arranged between first and second supply voltages, one of which providing a common ground coupled to the reference terminal, a common node of the first and second switches being coupled to the output terminal through a reference capacitor, said third switch being included in a shunt path between the output terminal and the reference terminal, a first level of said three level PWM output signal being obtained in said first state of operation in which the first switch is closed and the second and third switches are open, a second level thereof being obtained in said second state of operation in which said second switch is closed and said first and third switches are open, and an intermediate level thereof at least substantially equal to the reference voltage is being obtained in a third state of operation in which said third switch is closed and said first and second switches are open, said reference capacitor being configured to integrate signal voltage variations received from said common node in the first and second states of operation into a DC reference voltage including a DC component at least substantially equidistant between the first and second supply voltages.

2. A three level Class D amplifier comprising a control circuit configured to receive an analog input signal and derive therefrom first, second and third PWM switching control signals being supplied to respectively first, second and third switches of a driver to obtain a three level PWM single ended output signal between an output terminal and a reference terminal, the first and second switches being serially arranged between first and second supply voltages, one of which providing a common ground coupled to the reference terminal through a reference capacitor, a common node of the first and second switches being coupled to the output terminal, said third switch being included in a shunt path between the output terminal and the reference terminal, a first level of said three level PWM output signal being obtained in said first state of operation in which the first switch is closed and the second and third switches are open, a second level thereof being obtained in said second state of operation in which said second switch is closed and said first and third switches are open, and an intermediate level thereof at least substantially equal to the reference voltage is being obtained in a third state of operation in which said third switch is closed and said first and second switches are open, said reference capacitor being configured to integrate signal voltage variations received from said common node in the first and second states of operation into a DC reference voltage including a DC component at least substantially equidistant between the first and second supply voltages.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention is explained in further detail, and by way of example, with reference to the accompanying drawings wherein:

(2) FIG. 1 is a schematic diagram of the prior art three level SE Class-D amplifier of U.S. Pat. No. 9,515,617.

(3) FIG. 2 is a schematic diagram of a first embodiment of a three level SE Class-D amplifier according to the invention.

(4) FIG. 3 is a schematic diagram of a second embodiment of a three level SE Class-D amplifier according to the invention allowing to couple a load to the driver using common ground with a single wire connection between the output O of the driver and the load.

(5) FIG. 4 is a schematic diagram of a third embodiment of a three level SE Class-D amplifier according to the invention using a differential supply voltage, providing a first supply voltage at +0.5Vs and a second supply voltage at −0.5Vs around a zero level common ground GND, allowing to couple a load to the driver using said common ground with a single wire connection between the output O of the driver and the load.

(6) FIGS. 5A, 5B and 5C are schematic diagrams showing the state of the first to third switches S1, S2 and S3 and the various currents in the respective first, second and third states of operation of the first SE embodiment of the Class-D amplifier of FIG. 2.

(7) FIGS. 6A, 6B and 6C are schematic diagrams showing the state of the first to third switches S1, S2 and S3 and the various currents in the respective first, second and third states of operation of the second embodiment of the SE Class-D amplifier of FIG. 3.

(8) FIGS. 7A, 7B and 7C are schematic diagrams showing the state of the first to third switches S1, S2 and S3 and the various currents in the respective first, second and third states of operation of the third embodiment of the SE Class-D amplifier of FIG. 4.

(9) FIG. 8A is a plot illustrating the PWM output signal waveform pwmm of the cited prior art amplifier as well as the first to third embodiments of a SE Class-D amplifier according to the invention.

(10) FIG. 8B is a plot illustrating the PWM output signal of FIG. 8A after being filtered into an analog output signal fos.

(11) FIG. 9 is a schematic diagram of a control circuit generating control signals for the switches of the driver D of the three level PWM SE amplifier of the first to third embodiments of SE Class-D amplifiers according to the invention.

(12) FIG. 10 is a schematic diagram of a load of the first to third embodiments of SE Class-D amplifiers according to the invention functioning as audio amplifier.

(13) FIG. 11 is a schematic diagram of a load of the first to third embodiments of SE Class-D audio amplifiers according to the invention functioning as RF antenna amplifier.

(14) Throughout the drawings, the same reference numerals indicate similar or corresponding features or functions. The drawings are included for illustrative purposes and are not intended to limit the scope of the invention.

DETAILED DESCRIPTION

(15) In the following description, for purposes of explanation rather than limitation, specific details are set forth such as the particular architecture, interfaces, techniques, etc., in order to provide a thorough understanding of the concepts of the invention. However, it will be apparent to those skilled in the art that the present invention may be practiced in other embodiments, which depart from these specific details. In like manner, the text of this description is directed to the example embodiments as illustrated in the Figures, and is not intended to limit the claimed invention beyond the limits expressly included in the claims. For purposes of simplicity and clarity, detailed descriptions of well-known devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

(16) FIG. 1 illustrates the prior art SE three level half bridge Class-D amplifier of U.S. Pat. No. 9,515,617 providing a three level PWM output signal OS, which on itself is similar to the one shown in FIG. 8A. As already described in more detail in the above introductory of the description, inherent to this prior art SE amplifier are the multiple sources of power loss, due to the use of a PCB external floating capacitor Cfly and the need for extra switches to operate it.

(17) FIG. 2 shows a first embodiment of a three level PWM SE Class D amplifier according to the invention comprising a control circuit CC receiving an analog input signal AIS and deriving therefrom respective first, second and third two level PWM switching control signals, cs1, cs2 and cs3. The control circuit CC will be described in more detail with reference to FIG. 9.

(18) These first, second and third PWM switching control signals, cs1, cs2 and cs3, are coupled to control inputs of first, second and third switches, S1, S2 and S3, respectively, of a driver D.

(19) The driver D comprises a type half H bridge circuit having a serial arrangement of said first and second switches S1 and S2, respectively, coupled between a positive first supply voltage +Vs and a second supply voltage functioning as common ground, zero voltage level GND. The common node between the first and second switches S1 and S2, is coupled to an output terminal O. A DC level shifter including a ground connected reference capacitor Cref, hereafter also being referred to as DC level shifter Cref, provides a DC reference voltage Vref to the reference terminal REF. According to the invention, said third switch S3 is included in a shunt path SP between the output terminal O and the reference terminal REF.

(20) In operation, an amplifier external load L is coupled to the driver D between the output terminal O and the reference terminal REF.

(21) The first, second and third switches, S1, S2 and S3 are being controlled by said first, second and third PWM switching control signals, cs1, cs2 and cs3 to provide a modulation scheme generating a three level SE PWM output signal between the output terminal O and the reference terminal REF. According to the invention, a first level of said three level PWM output signal is being obtained in the first state of operation in which the first switch S1 is closed and the second and third switches S2 and S3 are open, a second level thereof is being obtained in the second state of operation, in which said second switch S2 is closed and said first and third switches S1 and S3, are open, and an intermediate level thereof at least substantially equidistant between the first and second level is being obtained in a third state of operation in which said third switch S3 is closed, whereas said first and second switches S1 and S2, respectively are open. These first to third states of operation will be explained in greater detail with reference to FIGS. 5A to 5C.

(22) The DC level shifter Cref is dimensioned such that within the timing of the modulation scheme, the voltage variations arriving across DC level shifter Cref from the output terminal O are being averaged into said DC reference voltage Vref, at least substantially equidistant between the first and second supply voltages, V1 and V2., i.e. at 0.5Vs. In generating said DC reference voltage Vref, the DC level shifter Cref of FIG. 2 corresponds to the DC level shifter constituted by reference capacitor Cref of the prior art three level PMW SE audio amplifier of FIG. 1 and no further amplification is needed for a proper understanding of the invention.

(23) The switches S1, S2 and S3 may be implemented in CMOS or any other semiconductor technology and are being controlled by respective switching control signals cs1, cs2 and cs3 to switch on, close or bring it into a conductive state, e.g. at a binary value cs=1 and switch off, open or bring it into a non-conductive state at a binary value cs=0. Dependent on the switching speed of the switches S1 to S3, the amplifier may be dimensioned to function as an audio amplifier, such as referred to in the above cited U.S. Pat. No. 9,515,617, in which case the analog input signal is an audio signal and the load L includes an audio filter AF followed by a loudspeaker LS as shown in FIG. 10, or by a single audio loudspeaker LS (not shown) such as referred to in the above cited U.S. Pat. No. 6,211,728. At a sufficiently high switching speed the amplifier may be dimensioned to function as an RF transmitter amplifier, in which case the analog input signal is an RF transmitting signal and the load L includes an RF filter RF followed by an RF antenna ANT as shown in FIG. 11.

(24) A functional block diagram of the control circuit CC is shown in FIG. 9 and includes a three level PWM modulator M followed by a gate driver circuit GDC. An analog input signal AIS is being provided to the modulator M and modulated therein into a three level PWM modulated signal PWMM. FIG. 8A illustrates by way of example said analog input signal AIS and the three level PWM modulated signal generated therefrom by the modulator M with curves ais and pwmm, respectively, both in a unitary scaling. First, second and third signal levels at respective amplitudes +1, −1 and 0 of this three level PWM modulated signal pwmm are being obtained in respective first, second and third states of operation of the modulator M.

(25) Such modulator M is itself known, e.g. from https://www.mathworks.com/help/physmod/sps/powersys/ref/pwmgenerator3level.html.

(26) At the reception of these first, second and third levels, the gate driver circuit GDC generates the respective appropriate sets of binary values of the first to third switching control signals cs1, cs2 and cs3, necessary for the driver D to correspond to the modulator M in state of operation. In the above example of binary values for the switching control signals cs1, cs2 and cs3, this will be obtained with gate driver circuit GDC generating binary values (1,0,0), (0,1,0) and (0,0,1) for the first to third switching control signals (cs1,cs2,cs3) when receiving the respective first, second and third level of the three level PWM modulated signal from the modulator M.

(27) This results in an amplification of the three level PWM signal of the modulator M pwmm in the driver D into the above three level differential PWM output signal between the output terminal O and the reference terminal REF as illustrated in FIG. 8B with curve pwmo. First, second and third signal levels at respective amplitudes 0.5Vs, −0.5Vs and 0 of this three level PWM modulated signal pwmo are being obtained in respective first, second and third states of operation of the driver D.

(28) In the audiofilter AF of FIG. 10, or as the case may be in the RF filter RF of FIG. 11 of the load L, the three level differential PWM output signal pwmo is being filtered to obtain a filtered output signal fos, which includes a signal component aos, representing an amplified version of the analog input signal ais.

(29) Given the above functionalities of the various switches of the driver D in the first, second and third states of operation necessary to obtain the above amplification according to the invention, the translating thereof to an actual realization of the control circuit CC is straightforward to a person skilled in the art and is not limited to the example described with reference to FIG. 9.

(30) FIG. 5A is a functional diagram illustrating the driver D of the above first embodiment of a three level PWM SE Class D amplifier according to the invention being connected to an external load L, which does not form part of the amplifier, in its first state of operation, in which the first switch S1 is closed and the second and third switches, S2 and S3, respectively, are open. This means that the voltage level at the output terminal O is equal to the supply voltage Vs.

(31) The flow of the supply current in this first state of operation is indicated with solid arrows.

(32) Starting from the supply voltage Vs the current subsequently passes the closed first switch S1, and the output terminal O, after which the supply current is split into on the one hand a wanted load current and on the other hand an unwanted leakage current LleakT1 charging the parasitic capacitance CparT1 occurring at the output terminal O. The leakage current LleakT1 will be discussed in greater detail with reference to FIG. 8A.

(33) The wanted load current is being supplied through the output terminal O to the load L and subsequently integrated in the DC level shifter Cref, into a reference voltage Vref defined by the voltage across the DC level shifter Cref of 0.5Vs, appearing at the reference terminal REF. The so obtained first level of the three level PWM SE output signal between the output terminal O and the reference terminal REF in this first state of operation therewith corresponds to 0.5Vs.

(34) FIG. 5B is a functional diagram illustrating the driver D of the first embodiment of a three level PWM SE Class D amplifier according to the invention in its second state of operation, in which the second switch S2 is closed and said first and third switches S1 and S3, respectively, are open, resulting at the output terminal O in a second level of said three level PWM signal corresponding to zero voltage level GND.

(35) The flow of the load current in this second state of operation is indicated with dotted arrows.

(36) Unlike the load current in the first state of operation, the load current in the second state of operation is being supplied from the DC level shifter Cref. Starting from the DC level shifter Cref the load current passes the load L, the output terminal O and the second switch S2, whereupon it sinks to the common zero voltage level GND. Due to the voltage across the DC level shifter Cref, the second level of the three level PWM SE output signal between the output terminal O and the reference terminal REF therewith corresponds to −0.5Vs.

(37) In this second state of operation the load current does not charge the power supply provided by the first supply voltages, Vs and GND, respectively.

(38) FIG. 5C is a functional diagram illustrating the driver D of the first embodiment of a three level PWM SE Class D amplifier according to the invention in its third state of operation, in which the first and second switches, S1 and S2 are open and the third switch S3 is closed. The output terminal O is on the one hand disconnected from both first and second supply voltages Vs and GND, respectively, and on the other hand via the third switch S3 connected to the reference terminal REF. This results into a third level of the three level PWM SE output signal between the output terminal O and the reference terminal REF in this third state of operation corresponding to 0, i.e. corresponding to an intermediate DC level substantially equidistant between the first and second level of said three level PWM output signal.

(39) Also in this third state of operation no current is being supplied to the load L from the power supply, provided by the first and second supply voltages, Vs and GND, respectively.

(40) As can be derived from FIG. 8A, during positive halves of the audio input signal AIS the driver D toggles between the first and third state of operation and vice versa in order for the three level pulse width modulation signal between the output terminal O and the reference terminal REF to switch between the first level and the intermediate level and vice versa.

(41) This first state of operation occurs once per clock period only during the positive halves of the three level pulse width modulated output signal. Compared to the prior art amplifier of FIG. 1, this reduces the average occurrence of leakage current IleakO charging the parasitic capacitances at the output terminal O, to fclock/2. The leakage current IleakO depends on the parasitic capacitance CparO and the voltage level difference between the high and intermediate level, i.e. 0.5Vs, resulting in
IleakO=CparO*0.5fclock*0.5Vs.

(42) During negative halves of the audio input signal AIS the driver D toggles between the second and third state of operation and vice versa in order for the three level PWM signal between the output terminal O and the reference terminal REF to switch between the second level and the intermediate level and vice versa. As both second and third states of operation require no power from the supply voltages, said three level PWM output signal is being generated during the negative halves of the audio input signal without any power being supplied to the driver D from the voltage supply.

(43) This means that compared to the total leakage current Ileak=CparO*fclock*0.5Vs*3 of the cited single-ended output driver of U.S. Pat. No. 9,515,617, the invention increases power efficiency with approximately a factor 5.

(44) Furthermore, in removing the use of a flying capacitor, the invention limits the sources of EMI noise to merely the inevitable one occurring at the output terminal O, therewith providing an increase in EMI reduction with approximately a factor 3.

(45) Unlike the three level PWM SE Class D amplifiers of cited U.S. Pat. No. 9,515,617 the intermediate level of the three level PWM output signal between the output terminal O and the reference terminal REF is obtained by disconnecting the output terminal O from both first and second supply voltages and simultaneously interconnecting both output and reference terminals by closing the third switch S3. As a consequence, the voltage difference between these terminals reduce to zero.

(46) FIG. 3 illustrates a second embodiment of a three level PWM SE Class-D switching amplifier according to the invention which differs from the first embodiment of FIG. 2 mainly in that the DC level shifter Cref is coupled between the common node of the first and second switches S1 and S2 and the output terminal O. The DC level shifter Cref integrates supply currents received from said common node in said first and second states of operation into a DC reference voltage similar to the DC reference voltage Vref of the first embodiment. However here, the DC reference voltage Vref is being supplied to the output terminal O, whereas the reference terminal REF is coupled to ground GND. This allows coupling of the external load L through the reference terminal REF to the same ground GND as the amplifier, requiring only a single wire to connect the output terminal O to a signal input of said external load L.

(47) FIG. 6A is a functional diagram illustrating the driver D of the second embodiment of a three level PWM SE Class D amplifier according to the invention in its first state of operation, in which the first switch S1 is closed and the second and third switches, S2 and S3, respectively, are open.

(48) The flow of the supply current in this first state of operation is indicated with solid arrows.

(49) Starting from the supply voltage Vs, the supply current subsequently passes the closed first switch S1, after which at the common node of the first and second switches S1 and S2, the supply current is split into on the one hand an unwanted leakage current LleakT1 charging the parasitic capacitance CparT1 occurring at said common node. On the other hand the supply current provides a wanted load current, charging DC level shifter Cref to a DC voltage of 0.5Vs, resulting in a DC voltage defining the first level of the three level PWM SE output signal between the output terminal O and the reference terminal REF of Vs −0.5Vs=0.5Vs. The leakage current LleakT1 will be discussed in greater detail with reference to FIG. 8A.

(50) FIG. 6B is a functional diagram illustrating the driver D of the second embodiment of a three level PWM SE Class D amplifier according to the invention in its second state of operation, in which the second switch S2 is closed and said first and third switches S1 and S3, respectively, are open.

(51) The flow of the load current in this second state of operation is indicated with dotted arrows.

(52) Unlike the load current in the first state of operation, the load current in the second state of operation is being supplied from the DC level shifter Cref. Starting from the reference capacitor Cref the load current passes the load L, the output terminal O and the second switch S2, whereupon it sinks to the common zero voltage level GND. This results in a DC voltage defining the second level of the three level PWM SE output signal between the output terminal O and the reference terminal REF of −0.5Vs.

(53) In this second state of operation the load current does not charge the power supply provided by the first supply voltages, Vs and GND, respectively.

(54) FIG. 6C is a functional diagram illustrating the driver D of the second embodiment of a three level PWM SE Class D amplifier according to the invention in its third state of operation, in which the first and second switches, 51 and S2 are open and the third switch S3 is closed. The output terminal O is on the one hand disconnected from both first and second supply voltages Vs and GND, respectively, and on the other hand via the third switch S3 connected to the reference terminal REF. This results in a DC voltage defining the third level of the three level PWM SE output signal between the output terminal O and the reference terminal REF of 0, i.e. equidistant between said first and second levels and corresponding to the intermediate level of said three level PWM output signal.

(55) Also in this third state of operation no current is being supplied to the load L from the power supply, provided by the first and second supply voltages, Vs and GND, respectively.

(56) As can be derived from FIG. 8B, during positive halves of the audio input signal AIS the driver D toggles between the first and third state of operation and vice versa in order for the three level pulse width modulation signal between the output terminal O and the reference terminal REF to switch between the first level and the intermediate level and vice versa.

(57) The first state of operation occurs once per clock period only during the positive halves of the three level pulse width modulated output signal. Compared to the prior art amplifier of FIG. 1, this reduces the average occurrence of leakage current IleakO charging the parasitic capacitances at the output terminal O, to fclock/2. The leakage current IleakO depends on the parasitic capacitance CparO and the voltage level difference between the high and intermediate level, i.e. 0.5Vs, resulting in
IleakO=CparO*0.5fclock*0.5Vs.

(58) During negative halves of the audio input signal AS the driver D toggles between the second and third state of operation and vice versa in order for the three level PWM signal at the output terminal O to switch between the second level and the intermediate level and vice versa. As both second and third states of operation require no power from the supply voltages, said three level PWM output signal at the output terminal O is being generated during the negative halves of the audio input signal without any power being supplied to the driver D from the voltage supply.

(59) FIG. 4 illustrates a third embodiment of a three level PWM SE Class-D switching amplifier according to the invention using of a differential pair of first and second supply voltages at first and second voltage levels of e.g. +0.5Vs and −0.5Vs, respectively, providing the function of the DC level shifter Cref as used in the above first and second preferred embodiments of the invention of FIGS. 2 and 3, by taking the supply voltage at common node between said first and second supply voltages as common ground GND. For that purpose, said common node is connected to the reference terminal REF, providing a DC reference voltage Vref=0, which is equidistant between the first and second voltage levels +0.5Vs and 0.5Vs. As a result thereof both the driver D and the load L share ground GND in common removing the necessity for the use of a reference capacitor Cref as DC level shifter and requiring only a single wire between the output terminal O and the external load L to operatively connect the load L to the driver D.

(60) The third switch S3 is included in a shunt path SP between the output terminal O and ground GND, which in operation constitutes a controllable shunt path SP across to the external load L.

(61) The modulation scheme used in this third embodiment of the SE Class-D switching amplifier according to the invention of FIG. 4 is similar to the one of the first embodiment of FIG. 2A and is also based on first to third states of operation of the driver D, in which the states of switches S1, S2 and S3 are the same as those in the corresponding first to third states of operation of the first embodiment of FIG. 2A.

(62) FIG. 7A illustrates the first state of operation of the driver D of the amplifier of FIG. 4, in which the first switch S1 is closed and the second and third switches, S2 and S3, respectively, are open, resulting in the three level PWM output signal between the output terminal O and the reference terminal REF obtaining a first level.

(63) The flow of the load current in this first state of operation is indicated with solid arrows.

(64) The parasitic capacitances CparT1 occurring at the output terminal O—shown in dotted lines—are charged by leakage current LleakT1 at each positive edge of the three level PWM output signal. By the same reasoning as above with reference to FIG. 5A also here,
IleakT1=CparT1*0.5fclock*0.5Vs.

(65) FIG. 7B illustrates the second state of operation of the driver D, in which the second switch S2 is closed and said first and third switches S1 and S3, respectively, are open.

(66) The flow of the load current in this second state of operation is opposite to that in the first state of operation, and indicated with dotted arrows.

(67) Unlike the load current in the first state of operation, the load current in the second state of operation is being supplied from the zero voltage level GND to the load L after which it passes the third switch S3 on its way to the second supply voltage −0.5Vs, resulting in a second level of the three level PWM output signal between the output terminal O and the reference terminal REF at −0.5Vs.

(68) FIG. 7C illustrates the third state of operation of the driver D, in which the first and second switches, S1 and S2 are open and the third switch S3 is closed. The output terminal O is on the one hand disconnected from both first and second supply voltages 0.5Vs and −0.5Vs, respectively, and on the other hand via the closed third shunting switch S3 connected to the common ground voltage GND, defining the third level of said three level PWM output signal between the output terminal O and the reference terminal REF at an intermediate level corresponding to the ground voltage GND, i.e. substantially equidistant between said first and second levels.

(69) Also for this third embodiment of a SE Class-D switching amplifier according to the invention, FIG. 8A illustrates that during positive halves of the audio input signal ais the driver D toggles between the first and third state of operation and vice versa in order for the three level PWM output signal between the output terminal O and the reference terminal REF to switch between the first level and the intermediate level and vice versa.

(70) Similar to the first embodiment of a SE Class-D switching amplifier of FIG. 3, the first state of operation occurs once per clock period only during the positive halves of the three level PWM output signal, reducing the average occurrence of leakage current IleakT1 charging the parasitic capacitances CparT1 at the output terminal O to fclock/2. As the leakage current IleakT1 depends on the parasitic capacitance CparT1 and the voltage level difference between the first and intermediate level of 0.5Vs:
IleakT1=CparT1*0.5fclock*0.5Vs.

(71) During negative halves of the audio input signal AIS the driver D toggles between the second and third state of operation and vice versa in order for the three level PWM output signal at the output terminal O to switch between the second and the intermediate level and vice versa. As both second and third states of operation require no power from the voltage supply, the driver D doesn't charge the power supply provided by the first and second supply voltages 0.5Vs and −0.5Vs when generating said three level PWM output signal, during the negative halves of the audio input signal AIS.

(72) The reasoning given above with respect to the power efficiency and EMI reduction of the first embodiment of the invention of FIG. 2A, applies to this third embodiment of the invention of FIG. 4 as well, in the sense that compared to the prior art amplifier of U.S. Pat. No. 9,515,617, also here an increase in power efficiency with approximately a factor 5 is being obtained, and an increase in EMI reduction with approximately a factor 3.

(73) The invention is not limited to the embodiments explicitly disclosed. The person skilled in the art of Class D amplifier design will recognize further policies to be followed within the ambit of the present invention. For example, the invention may well be applied mutatis mutandis to pulse density modulation amplifiers. Furthermore it may well be possible in the third state of operation of the above first SE embodiment of a Class-D amplifier according to the invention to accept a certain common mode distortion and disconnect the reference capacitor Cref from the reference terminal REF.

(74) The invention is embodied in each new characteristic and each combination of characteristics. Any reference signs do not limit the scope of the claims. The word “comprising” does not exclude the presence of other elements than those listed in a claim. Use of the word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements.