Multi quantized digitally controlled power supply voltage for multi amplifier stages

Abstract

Methods and systems for power amplification with digital quantized power supply with multiple amplifiers are disclosed herein. In one embodiment, In one embodiment, a time-varying envelope signal is sampled, quantized and decomposed into several constituent signals that are individually amplified, and then combined to form a desired amplified version of the quantized time-varying envelope. Amplitude, phase and/or frequency characteristics of one or more of the signals and supply voltages V.sub.dd and source current of one or more amplifiers are digital controlled based on the information provided by quantization process and slow and fast power control information. Amplitude, phase and/or frequency characteristics of one or more of the constituent signals to be amplified are controlled to provide the desired amplitude, phase, frequency, and/or spectral characteristics of the desired quantized version of the time-varying envelope signal.

Claims

1. A method for power amplification with multi quantized digitally controlled power supply voltage on amplifier stages, comprising the following steps: receiving an input signal carrying the information to be transmitted; receiving a first clock signal with a value set according to a signal frequency of the input signal; receiving a second clock signal with a value set according to a desired sampling rate of the input signal; receiving a third clock signal in accordance with a desired output signal frequency of a desired output signal; receiving a slow and fast power control information to control an output power of an amplification stage with N.sub.bq power amplifiers, where N.sub.bq denotes the number of power amplifiers, by selecting different sets of N.sub.bq supply voltage values V.sub.dd to be applied to the N.sub.bq power amplifiers over different information blocks or over each data block of the input signal carrying the information; sampling said input signal carrying the information in accordance with the desired sampling rate to generate samples of the input signal; processing the samples of the input signal to generate an in-phase and a quadrature component of each sample; processing in a quantizer with N.sub.bq quantization bits, where N.sub.bq denotes the number of quantization bits equal to the number of power amplifiers, the quantization of said in-phase and quadrature components of each sample to generate N.sub.bq quantization bits that correspond to a quantized value of said in-phase component and N.sub.bq quantization bits that correspond to a quantized value of the quadrature component, respectively; processing individually in a digital mapper the N.sub.bq quantization bits of the quantized value of the in-phase component to generate a corresponding amplitude and phase of a polar representation of each quantization bit and processing individually the N.sub.bq quantization bits of the quantized value of the quadrature component to generate an amplitude and a phase of a polar representation of each quantization bit, wherein the amplitude associated to each quantization bit is defined according to a decomposition of the quantized value into polar components with amplitudes given by the sets with N.sub.bq amplitudes |c.sub.I,i| and N.sub.bq amplitudes |c.sub.q,i| for the in-phase and quadrature component, respectively; processing said sets with N.sub.bq amplitudes |c.sub.I,i| and N.sub.bq amplitudes |c.sub.q,i| of polar components of the decomposition of the in-phase and quadrature component, to generate a control information that selects the set of N.sub.bq supply voltage values V.sub.dd to be applied to the N.sub.bq amplifiers; processing the polar components of in-phase component by multiplying by a pulse signal with a desired spectral shape and processing the polar components of quadrature component by multiplying by a pulse signal with a desired spectral shape; processing the in-phase signals and quadrature signals by summing pairs of signals with same amplitude to generate a set of N.sub.bq constituent signals with constant envelope and a sum equal to the quantized version of the input signal carrying the information; multiplying the resulting set of N.sub.bq constituent signals with constant envelope by a periodic signal with the frequency of a radio frequency (RF) signal; biasing the N.sub.bq power amplifiers of the amplification stage with a set of N.sub.bq supply voltage values V.sub.dd, and/or drive currents, according to the decomposition of the quantized values into polar components and the slow and fast power control information; amplifying each one of the N.sub.bq constituent signals in one of N.sub.bq power amplifiers of said amplification stage and summing in a combiner the amplified constituent signals to create the desired output signal.

2. The method according to claim 1, wherein said step of receiving said input signal carrying the information comprises: receiving one band limited information signal with time varying envelope or receiving the in-phase and quadrature phase components of one band limited information signal with time varying envelope or receiving the samples of in-phase and quadrature component of one information band limited signal with time varying envelope or comprises receiving samples of one information band limited signal with time varying envelope.

3. The method according to claim 1, wherein the quantizer and digital mapper can be implemented in a single block using a single quantizer followed by a mapper for both in-phase and quadrature component of each sample or two quantizers followed by two mappers, each one for each in-phase and quadrature component, and wherein the quantization and the mapping can be performed by a comparator and a Look up table (LUT) with the corresponding quantization bits of the quantized value.

4. The method according to claim 1, wherein said step of quantizing the in-phase and quadrature component of each sample of said input signal carrying information to generate the quantization bits, may use a number of quantization bits that can change between different samples of said input signal.

5. The method according to claim 1, wherein the quantization and generation of polar components of said in-phase and quadrature component of each sample can be performed by a comparator and a look up table (LUT) with the corresponding amplitudes and phases of polar components for the N.sub.bq quantization bits or can be done once by a block that quantizes and generates directly the N.sub.bq quantization bits and the amplitudes and phases of polar components for the N.sub.bq quantization bits of the in-phase and quadrature components.

6. The method according to claim 1, wherein the generation of control information that selects the set of N.sub.bq supply voltage values V.sub.dd to be applied to the N.sub.bq power amplifiers can be performed by a look up table (LUT) with the supply voltage value V.sub.dd to be applied to each power amplifier or can be done once by a block that quantizes and generates directly the N.sub.bq quantization bits, the amplitudes and phases of polar components for the in-phase and quadrature components, and the control information for selecting the set of N.sub.bq supply voltage values V.sub.dd.

7. The method according to claim 1, wherein: said step of sampling comprises sampling said input signal in accordance with said desired sampling rate to generate the samples of the in-phase and quadrature components of the input signal carrying the information; said step of quantization comprises two quantizers where one quantizer is employed in the quantization of in-phase component of each sample and generates N.sub.bq quantization bits that correspond to the quantized version of the sample and another quantizer employed to quantize the quadrature component of each sample and that generates N.sub.bq quantization bits that correspond to the quantized version of the sample of quadrature component; said step of processing the sets with N.sub.bq amplitudes |c.sub.I,i| and N.sub.bq amplitudes |c.sub.q,i| for the in-phase and quadrature component, to generate the control information that selects the set of N.sub.bq supply voltage values V.sub.dd to be applied to the N.sub.bq amplifiers may also generate a set of N.sub.bq values of biasing currents to be applied to the N.sub.bq amplifiers.

8. The method according to claim 1, wherein a feedback can be coupled to each power amplifier to give information needed for a digital pre-distortion to compensate impairments of the amplifiers.

9. An apparatus for power amplification with multi quantized digitally controlled power supply voltage on amplifier stages, comprising: an input circuitry that receives an input signal carrying the information to be transmitted; an input circuitry that receives a clock signal with a value set according to a signal frequency of the input signal; an input circuitry that receives a clock signal with a value set according to a desired sampling rate of the input signal; an input circuitry that receives a clock signal in accordance with a desired output signal frequency of a desired output signal; an input circuitry that receives a slow and fast power control information; a sampling circuitry that samples the input signal carrying the information in accordance with the desired sampling rate to generate samples of the input signal carrying the information; a digital mapper circuitry that processes the samples of said input signal to generate an in-phase and a quadrature component of each sample, wherein a quantizer circuitry with N.sub.bq quantization bits, where N.sub.bq denotes the number of quantization bits, performs the quantization of the in-phase and quadrature component to generate N.sub.bq quantization bits that correspond to a quantized value of the in-phase component and N.sub.bq quantization bits that correspond to a quantized value of the quadrature component, and processes in a mapper the N.sub.bq quantization bits of the quantized value of the in-phase component and quadrature component to generate an amplitude and phase of a polar representation of each quantization bit, wherein the amplitude associated to the polar representation of each quantization bit is defined according to a decomposition of the quantized value into polar components with amplitudes given by the sets with N.sub.bq amplitudes |c.sub.I,i| and N.sub.bq amplitudes |c.sub.q,i| for the in-phase and quadrature components, respectively; a V.sub.dd voltage mapper circuitry that uses the signals provided by the digital mapper circuitry to generate a set of N.sub.bq control signals used to select the N.sub.bq supply voltage values V.sub.dd to be applied to the amplifiers of an amplification stage circuitry with N.sub.bq power amplifiers, according to the slow and fast power control information; a circuitry with phase shifters and polar converters, that generates the phase rotations associated to the polar representation of each quantization bit and adjust delays between the polar signals associated to the quantization bits; a circuitry that adjusts the amplitude of each in-phase polar signal according to the in-phase amplitude coefficients |c.sub.I,i| to generate N.sub.bq in-phase constituent signals and a circuitry that adjusts the amplitude of each quadrature polar signal according with the quadrature amplitude coefficients |c.sub.q,i| to generate N.sub.bq quadrature constituent signals; a bank of filters with a same impulsive response, that receives the in-phase and quadrature constituent signals and filter them to assure a desired spectral shape; a circuitry that combines pairs of in-phase constituent and quadrature constituent signals to generate a set of N.sub.bq constituent signals with quasi or constant envelope; a circuitry that receives the N.sub.bq constituent signals with quasi or constant envelope and up-convert them by multiplying each one by a periodic signal, with the desired output signal frequency; an amplification stage circuitry with N.sub.bq power amplifiers in parallel, that receives said constituent signals with quasi or constant, comprising at least N.sub.bq active power amplification branches with different power outputs levels controlled by a set of supply voltage values V.sub.dd provided by the digital mapper circuitry, wherein each one of the said constituent signals with quasi or constant envelope-is amplified by the power amplifier of his branch; a combiner circuitry coupled to the N.sub.bq branches of said amplification stage circuitry that combines the outputs of the branches of said amplification stage circuitry according to the control signals of V.sub.dd voltage mapper circuitry.

10. The apparatus of claim 9, wherein said received input signal carrying the information by input circuitry comprises: one band limited information signal with time varying envelope or the in-phase and quadrature components of one band limited information signal with time varying envelope or the samples of in-phase and quadrature components of one information band limited signal with time varying envelope or comprises the samples of one information band limited signal with time varying envelope.

11. The apparatus of claim 9, wherein: said quantizer circuitry may comprise two quantizers in parallel where one quantizer is used to quantize the in-phase component of each sample and generates N.sub.bq quantization bits that correspond to the quantization of the in-phase component and another quantizer that quantizes the quadrature component of each sample to generate N.sub.bq quantization bits that correspond to the quantization of the quadrature component; said digital mapper circuitry may comprises two mappers in parallel, with each one coupled to one quantizer, where one generates N.sub.bq constituent signal components in which the quantized value of said in-phase component of each sample is decomposed and a second one that generates N.sub.bq constituent signals components in which the quantized value of said quadrature component of each sample is decomposed, where the constituent signals components may have only a discrete number of amplitudes and discrete number of phases belonging to two sets of phases and amplitudes values with a maximum size equal to the number of quantization bits; a circuitry that combines the in-phase's constituent signals components and quadrature's constituent signal components with same amplitude, that result from the said digital mapper circuitry, to generate a set of substantially constant envelope constituent signals whose sum is equal to the quantized sample of the signal.

12. The apparatus of claim 9, wherein: said input circuitry receives the input signal carrying the information to be transmitted, receives the clock signal with the value set according to the signal frequency of the input signal, receives the clock signal with the value set according to the desired sampling rate of the input signal and receives the clock signal in accordance with the desired output signal frequency of the desired output signal; a phase splitter circuitry is coupled to the sampling circuitry to receive the samples and generates the in-phase and quadrature components for each sample; a quantizer circuitry is coupled to the sampling circuitry to quantize the in-phase and quadrature component of each samples and generates the quantization bits that correspond to the quantized value of each component; said digital mapper circuitry receives the quantization bits from the quantizer and generates N.sub.bq constituent signal components in which the quantized value of each component is decomposed, wherein the constituent signal components are defined according to the decomposition of the quantized value as a sum of polar components with amplitudes given by the sets with N.sub.bq amplitudes |c.sub.I,i| and N.sub.bq amplitudes |c.sub.q,i| for the in-phase and quadrature component, and generates control signals, proportional to the amplitude coefficients |c.sub.I,i| and |c.sub.q,i| to be used by the V.sub.dd voltage mapper; said V.sub.dd voltage mapper generates a set of N.sub.bq control signals to control the supply voltage values V.sub.dd values and generates a digital control signal for a fast/slow power control block circuitry.

13. The apparatus of claim 9, wherein said input circuitry that receives the input signal carrying the information, said input circuitries that receive clock signals, said sampling circuitry, said digital mapper circuitry, said quantizer circuitry, said V.sub.dd voltage mapper circuitry, said circuitry with phase shifters and polar converters, said bank of filters may be implemented by discrete electronic components, digital signal processors or by software in field programmable gate arrays (FPGA).

14. The apparatus of claim 9, wherein each of the N.sub.bq power amplifiers of the amplification stage circuitry has a unique supply voltage value V.sub.dd from the set of supply voltage values V.sub.dd and a bias applied to the amplification stage circuitry, and where the supply voltage values V.sub.dd and the bias applied to the N.sub.bq amplifiers, are the output of a fast/slow power control block circuitry that sends the control signals to a direct current/direct current (DC/DC) converter circuitry that define the set of V.sub.dd values to be generated by the DC/DC converter.

15. The apparatus of claim 9, further comprising a low-dropout regulator (LDO) to generate the set of supply voltage values V.sub.dd and bias signals, used in the amplification stage.

16. The apparatus of claim 9, wherein the outputs of the N.sub.bq power amplifiers of amplification stage circuitry have different power levels according to the supply voltage value V.sub.dd applied to each power amplifier branch.

17. The apparatus of claim 9, wherein: each power amplification branch may include multiple power amplification stages represented by a limiter that provides a signal to power drivers in parallel, each one providing an input signal to the switches of each power amplifier; each power amplifier may include two complementary switches based on transistors, followed by a bandpass filter, composed by passive reactive elements like capacitors and inductors.

18. The apparatus of claim 9, wherein said digital mapper circuitry comprises one or more look up tables which are used to process quantization bits and said digital control signals.

19. The apparatus of claim 9, wherein said amplification stage circuitry with N.sub.bq power amplifiers in parallel comprises a plurality of power amplifiers that may be current source amplifiers or switched amplifiers.

20. The apparatus of claim 9, wherein said amplification stage circuitry with N.sub.bq power amplifiers in parallel: may comprise a plurality of bipolar junction transistors (BJTs) of type NPN or of type PNP or; may comprise a plurality of Field Effect Transistors (FETs) with N or P Channels or; may comprise a plurality of Field Effect Transistors (FETs) with N or P Channels, using silicon based on metal-oxide-semiconductor (MOS) technology or; may comprise a plurality of Field Effect Transistors (FETs) with N or P Channels, using Gallium arsenide (GaAs) technology, Gallium nitride (GaN) technology and/or silicon-germanium (SiGe) technology.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) The various aspects of embodiments of the present invention will be described with reference to the accompanying drawings, wherein generally similar reference numbers indicate identical or functionally similar elements. The various aspects of the embodiments disclosed here, including features and advantages of the present invention outlined above, are described more fully in the detailed description in conjunction with the drawings in which:

(2) FIG. 1 is a process flowchart embodiment for multi quantized digitally controlled power supply voltage for multi amplifier stages method with current source amplifiers.

(3) FIG. 2A is a block diagram that illustrates an exemplary embodiment of a multi quantized digitally controlled power supply voltage for multi amplifier stages apparatus for current source amplifiers without multiplying the polar quadrature components signals by a periodic signal in a intermediate frequency before being up-converted.

(4) FIG. 2B is a block diagram that illustrates an exemplary embodiment of a multi quantized digitally controlled power supply voltage for multi amplifier stages apparatus for current source amplifiers where the resulting polar quadrature components signals are multiplied by a periodic signal in a intermediate frequency before being up-converted.

(5) FIG. 3 is a process flowchart embodiment for multi quantized digitally controlled power supply voltage for multi amplifier stages method with switched amplifiers.

(6) FIG. 4A is a block diagram that illustrates an exemplary embodiment of a multi quantized digitally controlled power supply voltage for multi amplifier stages apparatus for switched amplifiers without multiplying the polar quadrature components signals by a periodic signal in a intermediate frequency before being up-converted.

(7) FIG. 4B is a block diagram that illustrates an exemplary embodiment of a multi quantized digitally controlled power supply voltage for multi amplifier stages apparatus for switched amplifiers and where the resulting the polar quadrature components signals are multiplied by a periodic signal in an intermediate frequency before being up-converted.

(8) FIG. 5 is a block diagram that illustrates an exemplary embodiment for implementing the digital mapper employed in a multi quantized digitally controlled power supply voltage for multi amplifier stages.

(9) FIG. 6 is a block diagram that illustrates an exemplary embodiment for implementing a class A amplification stage in a multi quantized digitally controlled power supply voltage for multi amplifier stages method.

(10) FIG. 7 is a block diagram that illustrates another exemplary embodiment for implementing a class D amplification stage in a multi quantized digitally controlled power supply voltage for multi amplifier stages.

DETAILED DESCRIPTION OF THE INVENTION

(11) Table of Contents 1. Introduction 1.1. Decomposition of time-varying envelope signals into constant envelope components 2. Multi Quantized Digitally Controlled Power Supply Voltage for Multi Amplifier Stages (MQDCPSVMAS) methods and systems 2.1. Multi Quantized Digitally Controlled Power Supply Voltage for Multi Amplifier Stages with current source amplifiers 2.2. Multi Quantized Digitally Controlled Power Supply Voltage for Multi Amplifier Stages with switched amplifiers 3. Multi amplifier amplification stage embodiments 4. Summary 5. Conclusions
1. Introduction

(12) Methods, apparatuses and systems for Multi Quantized Digitally Controlled Power Supply Voltage for Multi Amplifier Stages (MQDCPSVMAS) are disclosed herein. High-level description of MQDCPSVMAS methods and systems according to embodiments of the present invention will be provided in sections 2 and 3.

(13) Some definitions are provided in this section only for convenience purposes and are not limiting. The meaning of these terms will be apparent for a person skilled in the art based on the entirety of the teachings provided herein.

(14) Modulated signals can be described by s(t)=s.sub.l(t) cos(ω.sub.ct)+js.sub.Q(t)sin(ω.sub.ct), where ω.sub.c=2πf.sub.c denotes the angular frequency, f.sub.c denotes the carrier frequency, and s.sub.l(t) and s.sub.Q(t) denote the in-phase and the quadrature component, respectively. The signal can be also described by s(t)=Re{{tilde over (s)}(t)e.sup.jω.sup.c.sup.t}, where {tilde over (s)}(t)=s.sub.l(t)+js.sub.Q(t) denotes the complex envelope, s.sub.l(t) denotes the in phase component, s.sub.Q(t) denotes the quadrature component, with the signal envelope given by e(t)=√{square root over ((s.sub.l(t)).sup.2+(S.sub.Q(t)).sup.2)}. When e(t) is invariant along time the signal is said as constant envelope signal. Time varying envelope signal refers a signal where e(t) varies with time. Having both non-constant envelope and phase, s(t) is said to be a time-varying complex envelope signal. The dynamic range (DR) of the envelope represents the range of values between which the signal's envelope varies. The dynamic range of the in-phase component (DRi) represents the range of values between which the in-phase component varies. The dynamic range of the quadrature component (DRq) represents the range of values between which the quadrature component varies.

(15) For purposes of convenience, and not limitation, time varying complex envelope signals are sometimes referred to herein as time varying envelope signals.

(16) 1.1 Decomposition of Time-Varying Envelope Signals into Constant Components

(17) In a time varying envelope signal the envelope values may assume any value inside the dynamic range, being infinite the number of possible values. Through a quantization process the discretization of envelope could be done by restricting the possible values to a finite set of quantization values ={s.sub.0, s.sub.1, . . . , s.sub.N.sub.QL.sub.−1}, where N.sub.QL denotes the number of quantization levels, i.e. the size of the alphabet of quantization symbols. Let denote as s(nT.sub.s)=s.sub.n the time domain sample of the time-varying envelope signal at the sample instant nT.sub.s and s.sub.l(nT.sub.s)=s.sub.nI and s.sub.Q(nT.sub.s)=s.sub.nQ the corresponding in-phase and quadrature components. Dynamic ranges of (nT.sub.s)=s.sub.n, s.sub.l(nT.sub.s)=s.sub.nI and s.sub.Q(nT.sub.s)=s.sub.nQ are DR, DRi and DRq respectively. For purposes of convenience, and not limitation it is assumed that DRi=DRq.

(18) The quantizer transforms the time domain sample of the input signal s.sub.n into a quantized symbol s.sub.n,QT taken from a discrete alphabet of N.sub.QL=2.sup.N.sup.bq possible quantization symbols. The N.sub.bq quantization bits and N.sub.QL=2.sup.N.sup.bq quantization levels can be defined in terms of the maximum quantization error

(19) ${\mathrm{.Math.}}_Q=\frac{\mathrm{DR}}{2\times 2^{N_b}}=\Delta ,$
where 2Δ represents the quantization interval between two adjacent quantization symbols. The N.sub.bq quantization bits (β.sub.n.sup.(N.sup.b.sup.−1), β.sub.n.sup.(N.sup.b.sup.−2), . . . , β.sub.n.sup.(1), β.sub.n.sup.(0)) are employed in the definition of N.sub.m≤N.sub.bp polar components (i.e., N.sub.m phases and N.sub.m amplitudes) in which each quantization level can be decomposed. The bits (β.sub.n.sup.(N.sup.bq.sup.−1), β.sub.n.sup.(N.sup.bq.sup.−2), . . . , β.sub.n.sup.(1), β.sub.n.sup.(0)) are converted into polar form (β.sub.n.sup.(N.sup.bq.sup.−1), β.sub.n.sup.(N.sup.bq.sup.−2), . . . , b.sub.n.sup.(1), b.sub.n.sup.(0)) by b.sub.n.sup.(m)=(−1)β.sub.n.sup.(m). Each symbol from the finite set of quantizer values or symbols ={s.sub.0, s.sub.1, . . . , s.sub.N.sub.QL.sub.−1}, can be represented as a sum of N.sub.m≤N.sub.bq polar components, that are the result of the decomposition of quantization value s.sub.n,QT into polar components or complex components, which is given by:

(20) $\begin{array}{c}{s}_{n,\mathrm{QT}}=c_0+c_1{b}_n^{\left(0\right)}+c_2{b}_n^{\left(1\right)}+c_3{b}_n^{\left(0\right)}{b}_n^{\left(1\right)}+c_4{b}_n^{\left(2\right)}+\mathrm{.Math.}\\ =\underset{i=0}{\overset{N_m-1}{.Math.}}{c}_i\underset{m=0}{\overset{N_m-1}{.Math.}}{\left(b_n^{\left(m\right)}\right)}^{{\gamma }_{m,i}}\\ =\underset{i=0}{\overset{N_m-1}{.Math.}}{c}_i{b}_n^{\mathrm{eq}\left(i\right)},\end{array}\hspace{1em}$
with (γ.sub.N.sub.m.sub.−1,iγ.sub.N.sub.m.sub.−2,i . . . γ.sub.1,i, γ.sub.0,i) denoting the binary representation of i, b.sub.n.sup.(m)=(−1)β.sub.n.sup.(m) denoting the polar representation of the bit β.sub.n.sup.(m), b.sub.n.sup.eq(i)=Π.sub.m=0.sup.N.sup.m.sup.−1(b.sub.n.sup.(m)).sup.γ.sup.m,i denoting the i'th polar component of s.sub.n, and N.sub.m is the number of non-null complex coefficients c.sub.i of the referred decomposition equation above (the total number of coefficients is 2.sup.N.sup.bq). For example, for N.sub.b=6 and a symmetrical dynamic range DR (using as reference the zero value) the quantization levels are ±pΔ+jkΔ, with p=1, 3, 5, 7 and k=1, 2, 3 5, 7 which can be given by
s.sub.n,QT=c.sub.1b.sub.n.sup.(0)+c.sub.2b.sub.n.sup.(1)+c.sub.4b.sub.n.sup.(2)+c.sub.8b.sub.n.sup.(3)+c.sub.16b.sub.n.sup.(4)+c.sub.32b.sub.n.sup.(5),
with c.sub.1=Δ, c.sub.2=jΔ, c.sub.4=j2Δ, c.sub.8=j2Δ, c.sub.16=4Δ, c.sub.32=j4Δ and c.sub.i=0, for ∀i≠1, 2, 4, 8, 16, 32.

(21) Also, the quantization could be done by two quantizers, each one employed to quantize the in-phase and the quadrature component separately. Thus, the time domain sample of the complex envelope in-phase component s.sub.nI can be transformed into a quantized symbol S.sub.nI,QT taken from a finite alphabet of 2.sup.N.sup.bq possible quantization symbols. Also, the time domain sample of the quadrature component s.sub.nQ can be transformed into a quantized symbol S.sub.nQ,QT taken from a finite alphabet of 2.sup.N.sup.bq possible quantization symbols. The N.sub.bq quantization bits and N.sub.QL=2.sup.N.sup.bq quantization levels applied in each component can be defined in terms of the maximum quantization errors

(22) ${\mathrm{.Math.}}_{\mathrm{Qi}}=\frac{\mathrm{DRi}}{2x{2}^{N_{\mathrm{bq}}}}=\frac{2\Delta i}{2}\mathrm{and}{\mathrm{.Math.}}_{\mathrm{Qq}}=\frac{\mathrm{DRq}}{2\times 2^{N_{\mathrm{bq}}}}=\frac{2\Delta q}{2}$
where 2Δi and 2Δq represent the quantization interval for the in-phase component and quadrature component, respectively. For each component, N.sub.bq quantization bits (β.sub.nI.sup.(N.sup.bq.sup.−1), β.sub.nI.sup.(N.sup.bq.sup.−2), . . . , β.sub.nI.sup.(1), β.sub.nI.sup.(0)) and (β.sub.nq.sup.(N.sup.bq.sup.−1), β.sub.nq.sup.(N.sup.bq.sup.−2), . . . , β.sub.nq.sup.(1), β.sub.nq.sup.(0)) are employed in the definition of N.sub.m≤N.sub.bq polar components (i.e., N.sub.m phases and N.sub.m amplitudes) in which each quantization level can be decomposed. Both set of bits (β.sub.nI.sup.(N.sup.b.sup.−1), β.sub.nI.sup.(N.sup.b.sup.−2), . . . , β.sub.nI.sup.(1), β.sub.nI.sup.(0)) and (β.sub.nq.sup.(N.sup.bq.sup.−1), β.sub.nq.sup.(N.sup.bq.sup.−2), . . . , β.sub.nq.sup.(1), β.sub.nq.sup.(0)) are converted into polar forms (b.sub.nI.sup.(N.sup.bq.sup.−1), b.sub.nI.sup.(N.sup.bq.sup.−2), . . . , b.sub.nI.sup.(1), b.sub.nI.sup.(0)) by b.sub.nI.sup.(m)=(−1)β.sub.nI.sup.(m) and b.sub.nq.sup.(m)=(−1)β.sub.nq.sup.(m).

(23) Each in-phase symbol from the finite set of symbols I={s.sub.I,0, s.sub.I,1, . . . , s.sub.I,N.sub.QL.sub.−1} can be represented as a sum of N.sub.mI≤N.sub.bq polar components that are the result of the decomposition of quantization value s.sub.nI,QT into polar components given by

(24) $\begin{array}{c}{s}_{\mathrm{nI},\mathrm{QT}}=c_{I,0}+c_{I,1}{b}_{\mathrm{nI}}^{\left(0\right)}+c_{I,2}{b}_{\mathrm{nI}}^{\left(1\right)}+c_{I,3}{b}_{\mathrm{nI}}^{\left(0\right)}{b}_{\mathrm{nI}}^{\left(1\right)}+c_{I,4}{b}_{\mathrm{nI}}^{\left(2\right)}+\mathrm{.Math.}\\ =\underset{i=0}{\overset{N_{\mathrm{mI}}-1}{.Math.}}{c}_{I,i}\underset{m=0}{\overset{N_{\mathrm{mI}}-1}{.Math.}}{\left(b_{\mathrm{nI}}^{\left(m\right)}\right)}^{{\gamma }_{m,i}},\end{array}\hspace{1em}$
with (γ.sub.N.sub.mI.sub.−1,i γ.sub.N.sub.mI.sub.−2,i . . . γ.sub.1,i, γ.sub.0,i) denoting the binary representation of i, and N.sub.mI is the number of non-null c.sub.i real coefficients of the referred decomposition (the total number of coefficients is 2.sup.N.sup.bq−1). For example, for N.sub.bq=3 and a symmetrical dynamic range DRi (using as reference the zero value) the quantization levels are ±7Δ, ±5Δ, ±3Δ, +Δ, which can be given by
s.sub.nI,QT=c.sub.I,1b.sub.nI.sup.(0)+c.sub.I,2b.sub.nI.sup.(1)+c.sub.I,4b.sub.nI.sup.(2),
with c.sub.I,1=Δ, c.sub.I,2=2Δ, c.sub.I,4=4Δ and c.sub.I,0=c.sub.I,3=c.sub.I,5=c.sub.I,6=c.sub.I,7=0. For the quadrature component each symbol from the finite set of quantizer symbolsQ={s.sub.q,0, s.sub.q,1, . . . , s.sub.q,N.sub.QL.sub.−1}, can be represented as a sum of N.sub.mQ≤N.sub.bq polar components, that are the result of the decomposition of quantization value S.sub.nq,QT into polar components given by

(25) $\begin{array}{c}{s}_{\mathrm{nq},\mathrm{QT}}=c_{q,0}+c_{q,1}{b}_{\mathrm{nq}}^{\left(0\right)}+c_{q,2}{b}_{\mathrm{nq}}^{\left(1\right)}+c_{q,3}{b}_{\mathrm{nq}}^{\left(0\right)}{b}_{\mathrm{nq}}^{\left(1\right)}+c_{q,4}{b}_{\mathrm{nq}}^{\left(2\right)}+\mathrm{.Math.}\\ =\underset{i=0}{\overset{N_{\mathrm{mQ}}-1}{.Math.}}{c}_{q,i}\underset{m=0}{\overset{N_{\mathrm{mQ}}-1}{.Math.}}{\left(b_{\mathrm{nq}}^{\left(m\right)}\right)}^{{\gamma }_{m,i}},\end{array}\hspace{1em}$
with (γ.sub.N.sub.mQ.sub.−1,i γ.sub.N.sub.mQ.sub.−2,i . . . γ.sub.1,i, γ.sub.0,i) denoting the binary representation of i, and N.sub.mQ is the number of non-null g.sub.i real coefficients of the referred decomposition (the total number of coefficients is 2.sup.N.sup.b−1). For example, for N.sub.b=3 and a symmetrical dynamic range (using as reference the zero value) the quantization levels are ±j7Δ, ±j5Δ, ±j3Δ, ±jΔ, which can be given by
s.sub.nq,QT=c.sub.q,1b.sub.nq.sup.(0)+c.sub.q,2b.sub.nq.sup.(1)+c.sub.q,4b.sub.nq.sup.(2),
with c.sub.q,1=jΔ, c.sub.q,2=j2Δ, c.sub.q,4=j4Δ and c.sub.q,0=c.sub.q,3=c.sub.q,5=c.sub.q,6=c.sub.q,7=0.

(26) By a proper selection of the pulse shape to be applied to the polar components and time shifts between in-phase and quadrature it is possible to decompose the quantized envelope as a sum of constant envelope components. Since each component is amplified by an amplifier the signal resulting from the combination of all outputs could be given by s.sub.n,QT,out=Σ.sub.i=0.sup.N.sup.m.sup.−1p.sub.i, where p.sub.i denotes the output power at i'th branch. For class A, and AB amplifiers we have p.sub.i=f(V.sub.dd, V.sub.in, I.sub.in). For class D amplifiers p.sub.i=f(V.sub.dd). In such conditions, to obtain the amplified version of the quantized envelope in class A or AB, the quantizer needs to provide the set with N.sub.bq values of V.sub.dd to be employed in the amplifiers plus the mapping rule (amplitude and phase) for the components. In class D, all the components may have the same amplitude, being necessary the N.sub.bq phases and the set of N.sub.bq V.sub.dd values.

(27) The example above refers the case of quantized samples taken from time variant envelope signals. A person skilled in the art, however, will understand that by quantizing the envelope values of any time-variant envelope signal, and decomposing in a plurality of quasi or constant envelope signals, any amplified version of the time-variant quantized version of the envelope signal can be generated as a sum of the amplified constant envelope signals.

(28) 2. Multi Quantized Digitally Controlled Power Supply Voltage for Multi Amplifier Stages Methods and Systems

(29) MQDCPSVMAS methods and systems according to embodiments of the present invention rely on the ability to quantize and decompose any quantized time-varying envelope signal into several substantially constant envelope constituent signals or to generate such constituent signals, amplify the constituent signals, and then sum the amplified signals to generate an amplified version of the time-varying envelope signal.

(30) In sections 2.1-2.2, embodiments of the present invention are provided, including N.sub.bq amplification branch embodiments with all supply voltage values V.sub.dd of all branches fixed over each information block or varying over the information block duration according to the control information provided by the quantizer and fast and slow power control unit that defines the selection rule of the V.sub.dd sets between envelope samples and information blocks. In the following descriptions, each embodiment is first presented conceptually using a mathematical derivation of underlying concepts of the embodiment. Two embodiments of a method of operation of the MQDCPSVMAS are then presented, followed by various system level embodiments.

(31) In all embodiments for purposes of convenience, and not limitation it is assumed same quantization rule for both in-phase and quadrature components of the envelope samples.

(32) According to one embodiment of the invention, herein called MQDCPSVMAS with current source amplifiers (MQDCPSVMASCS) for ease of illustration and not limitation, a time varying envelope signal is decomposed into N.sub.bq pairs of in-phase and quadrature constituent components with different amplitudes and DRi=DRq. In each pair the in-phase and quadrature constituent components are combined to generate a constituent signal with constant envelope that is amplified individually by an amplifier configured with a V.sub.dd selected from a set of N.sub.bq values. These N.sub.bq outputs of the N.sub.bq amplifiers are then summed to construct an amplified version of the quantized time-varying envelope of the signal.

(33) According to another embodiment of the invention, herein called MQDCPSVMAS with switched amplifiers (MQDCPSVMASSA) for ease of illustration and not limitation, a time varying envelope signal is decomposed into N.sub.bq pairs of in-phase and quadrature constituent components with same amplitude and DRi=DRq. In each pair, the in-phase and quadrature constituent components are amplified individually by an amplifier configured with a V.sub.dd selected from a set of N.sub.bq values, with the V.sub.dd defined as a function of coefficients c.sub.I,i and c.sub.q,i to assure different voltage outputs. The N.sub.bq signals at amplifiers outputs are then summed to construct an amplified version of the quantized time-varying envelope of the signal.

(34) It is noted that one quantizer and N.sub.bq amplification branches are employed in these embodiments. It is also assumed DRi=DRq and the same number of quantization bits for in-phase and quadrature components for purposes of illustration, and not limitation. The scope of the invention covers the use of two quantizers, one quantizer for in-phase and another for quadrature component, as well as the use of other number of branches different than N.sub.bq, DRi≠DRq, and sets of V.sub.dd values with sizes different than the number of quantization bits, and the implementation of such variations will be apparent to persons skilled in the art based on the teachings contained herein.

(35) Accordingly, in the MQDCPSVMAS embodiments the time domain sample of the signal s.sub.n is transformed into a quantized symbol s.sub.n,QT taken from a finite alphabet of 2.sup.N.sup.bq complex quantization symbols. The N.sub.bq quantization bits and N.sub.QL=2.sup.N.sup.bq quantization levels can be defined in terms of the maximum quantization error

(36) ${\mathrm{.Math.}}_Q=\frac{\mathrm{DR}}{2\times 2^{N_b}}=\Delta ,$
where 2Δ represents the quantization interval. The N.sub.b quantization (β.sub.n.sup.(N.sup.bq.sup.−1), β.sub.n.sup.(N.sup.bq.sup.−2), . . . , β.sub.n.sup.(1), β.sub.n.sup.(0)) bits are employed in the definition of N.sub.m≤N.sub.bq complex components in which each quantization level can be decomposed. The bits (β.sub.n.sup.(N.sup.bq.sup.−1), β.sub.n.sup.(N.sup.bq.sup.−2), . . . , β.sub.n.sup.(1), β.sub.n.sup.(0)) are converted into polar form (b.sub.n.sup.(N.sup.bq.sup.−1), b.sub.n.sup.(N.sup.b.sup.−2), . . . , b.sub.n.sup.(1), b.sub.n.sup.(0)) b.sub.n.sup.(m)=(−1)β.sub.n.sup.(m). The finite set of quantizer symbols ={s.sub.0, s.sub.1, . . . , s.sub.N.sub.QL.sub.−1}, where N.sub.QL=2.sup.N.sup.b is the number of complex quantization levels. Each symbol from the finite set of quantizer complex alphabet ={s.sub.0, s.sub.1, . . . , s.sub.N.sub.QL.sub.−1}, can be represented as a sum of N.sub.m≤N.sub.bq components, that are the result of the decomposition of quantization value s.sub.n,QT given by

(37) $\begin{array}{c}{s}_{n,\mathrm{QT}}=c_0+c_1{b}_n^{\left(0\right)}+c_2{b}_n^{\left(1\right)}+c_3{b}_n^{\left(0\right)}{b}_n^{\left(1\right)}+c_4{b}_n^{\left(2\right)}+\mathrm{.Math.}\\ =\underset{i=0}{\overset{N_m-1}{.Math.}}{c}_i\underset{m=0}{\overset{N_m-1}{.Math.}}{\left(b_n^{\left(m\right)}\right)}^{{\gamma }_{m,i}}\\ =\underset{i=0}{\overset{N_m-1}{.Math.}}{c}_i{b}_n^{\mathrm{eq}\left(i\right)},\end{array}\hspace{1em}$

(38) Each one of the N.sub.m polar components with amplitude c.sub.i has the amplitude and phase information associated to the components in which the quantized envelope can be decomposed. Note that the polar complex components can be modulated by an offset modulation such as offset quadrature phase shift keying (OQPSK), minimum phase shift keying (MSK), Gaussian MSK (GMSK) or other offset signal with a pulse shape selected to achieve high spectral efficiency and constant envelope.

(39) As referred previously, the complex quantizer can be replaced by two quantizers, with one associated to the in-phase component and the other applied to the quadrature component. Under these conditions each in-phase symbol from the finite set of symbols I={s.sub.I,0, s.sub.I,1, . . . , S.sub.I,N.sub.QL.sub.−1}, can be represented as a sum of N.sub.mI≤N.sub.bq polar components that are the result of the decomposition of quantization value s.sub.nI,QT into polar components given by

(40) $s_{\mathrm{nI},\mathrm{QT}}=\underset{i=0}{\overset{N_{\mathrm{mI}}-1}{.Math.}}{c}_{I,i}\underset{m=0}{\overset{N_{\mathrm{mI}}-1}{.Math.}}{\left(b_{\mathrm{nI}}^{\left(m\right)}\right)}^{{\gamma }_{m,i}},$
with (γ.sub.N.sub.mI.sub.−1,iγ.sub.N.sub.mI.sub.−2,i . . . γ.sub.1,i, γ.sub.0,i) denoting the binary representation of i, and N.sub.mI is the number of non-null c.sub.I,i real coefficients of the referred decomposition (the total number of coefficients is 2.sup.N.sup.bq−1). For the quadrature component results the decomposition of quantization value S.sub.nq,QT into polar components given by

(41) 0$s_{\mathrm{nq},\mathrm{QT}}=\underset{i=0}{\overset{N_{\mathrm{mQ}}-1}{.Math.}}{c}_{q,i}\underset{m=0}{\overset{N_{\mathrm{mQ}}-1}{.Math.}}{\left(b_{\mathrm{nq}}^{\left(m\right)}\right)}^{{\gamma }_{m,i}},$
with N.sub.mQ the number of non null c.sub.q,i imaginary coefficients of the referred decomposition (the total number of coefficients is 2.sup.N.sup.b−1. Thus, it is possible to write
s.sub.n,QT=s.sub.nI,QT+s.sub.nq,QT.

(42) According to the MQDCPSVMASCS embodiment are employed current source amplifiers of class A in the N.sub.bq amplification branches, only for illustration purposes and not limitation. Let consider the input signal applied to the i'th amplifier given by
v.sub.in,i(t)=A.sub.i sin(2πf.sub.RFt+θ.sub.i)*r(t),
where A.sub.i=f(c.sub.I,i, c.sub.q,i), f.sub.RF denotes the RF frequency, θ.sub.i=g(c.sub.I,i, c.sub.q,i) represents the phase of input signal in the i'th amplification branch and r(t) denotes the impulsive response of a filter that performs the spectral shaping of the amplifier's input signal (operator*denotes the convolution). In a transconductance based linear amplifier, the output signal voltage, considering a load R.sub.L, is approximately given by
v.sub.RL,i(t)=g.sub.m,iv.sub.in,i(t)r.sub.0∥R.sub.L,
where g.sub.m denotes the transconductance, R.sub.L represents the load and r.sub.0 the output resistance of the active device. Through an optimization process it is possible to maximize the amplifier efficiency by setting the power supply voltage V.sub.dd
2V.sub.dd,i=g.sub.m,iA.sub.ir.sub.0∥R.sub.L=k.sub.iA.sub.i,
with k.sub.i denoting a constant factor.

(43) Under these conditions the efficiency is maximized, and the output power is P.sub.out,i ∝V.sub.dd,i.sup.2. It follows that an amplified version of the quantized envelope can be obtained by the combination of N.sub.bq output voltages v.sub.R.sub.L.sub.,i(t). From the quantization process it is possible to generate the set of quantization bits, the N.sub.bq amplitudes of the quantization components amplitudes A.sub.i and the set with N.sub.bq phases θ.sub.i-, related with the phase of the input signal applied to the N.sub.bq amplifiers and the V.sub.dd values that optimize the N.sub.bq amplifiers according the amplitude and phase of the input signal.

(44) According to one embodiment of MQDCPSVMASSA, only for illustration purposes and not limitation, are employed switched amplifiers of class D in the N.sub.bq amplification branches. For a switched mode amplifier, as for the case of class D operation, the output voltage at the load at the fundamental can be translated by

(45) $v_{\mathrm{out},i}\left(t\right)=\frac{V_{\mathrm{dd},i}}{R_L}\sin \left(2\pi f_{\mathrm{RF}}t+{\alpha }_i+f\left({\theta }_i\right)\right)*r\left(t\right),$
where V.sub.dd,i is the supply voltage applied to the i'th amplifier, α.sub.i is a phase shift due to delays in the amplifier circuit and f(θ.sub.i) is a phase shift function of the phase of the input signal. Since the output voltage is independent of the voltage's amplitude of the input signal, each V.sub.dd,i element should be proportional by a factor k.sub.i to the corresponding amplitude A.sub.i. Under these conditions the signal, that results from the combination of the N.sub.bq outputs voltages, is an amplified version by a factor K of the quantized value of the envelope of the input signal. Thus, the set of N.sub.bq values of V.sub.dd, the sets of N.sub.bq phases θ.sub.i and N.sub.bq V.sub.dd values proportional to the components amplitudes A.sub.i, are sufficient to obtain the amplified version of the envelope and assure at same time the optimal operational conditions for each amplifier in the set of N.sub.bq amplifiers employed in the amplification stage.
2.1 Multi Quantized Digitally Controlled Power Supply Voltage for Multi Amplifier Stages with Current Source Amplifiers

(46) In MQDCPSVMASCS embodiment the in-phase and quadrature components are used to generate constituent signals with constant envelope that are individually amplified. In one embodiment the in-phase and quadrature components have different amplitudes and phases, according to the set of coefficients c.sub.I,1 and c.sub.q,i. In another embodiment the in-phase and quadrature components have same amplitude and different phases, being the quantized components combined to generate constituent signals with constant envelope that are individually amplified.

(47) The operation of the MQDCPSVMASCS embodiment shall be described further with reference to the flowchart of FIG. 1. Optional components are illustrated with dashed lines. The process starts at step 101, which includes receiving the signal carrying the information, that will be amplified. In another embodiment this involves receiving the RF signal carrying the information. In another embodiment this involves receiving the signal carrying the information in the intermediate frequency (IF). In another embodiment this involves receiving the envelope samples of the signal carrying the information.

(48) Step 102 includes receiving a clock signal set according to the signal frequency of the input signal.

(49) Step 103 includes receiving a clock signal set according to a desired sample rate of the input signal. It is important to mention that, as understood by a person skilled in the art, the sampling rate may vary according to the bandwidth of the input signal and the desired time resolution of the sampling process.

(50) Step 104 includes receiving a clock signal in accordance with the frequency of the desired output RF signal.

(51) Step 105 includes receiving slow and fast power control information to control the power output level after the amplification stage, by selecting different sets of V.sub.dd values and amplifiers' source currents over different information blocks, or selecting different sets of V.sub.dd values and amplifiers' source currents for the different samples of the envelope of the input signal carrying the information to be sent.

(52) Step 106 includes sampling the input signal in accordance with the sampling rate, to generate the samples of the input signal. In the embodiment example of FIG. 1, step 106 is implemented by a sampling circuit or a sample and hold (S/FI) circuit. In embodiments with multicarrier signals, step 106 can be implemented by a fast Fourier transform (FFT) with a higher time resolution to fulfill the sampling rate requirement.

(53) Step 107 includes processing the signal samples to generate in-phase and quadrature components of the sample.

(54) Step 108 includes processing in a quantizer with N.sub.bq quantization bits the in-phase and quadrature components to generate the quantization bits that correspond to the quantized value of the in-phase and the quantization bits that correspond to the quantized value of the quadrature component, respectively. As understood by a person skilled in the art based on the teaching herein, step 108 can be performed by a block using a single quantizer for both component samples or two quantizers, each one for each component. Also, as understood by a person skilled in the art based on the teaching herein, step 108 can be performed by a comparator and a LUT with the corresponding quantization bits of the quantized values.

(55) Step 109 includes processing individually the quantization bits of the quantized in-phase component to generate the corresponding amplitude and phase of polar representation of each quantization bit and processing individually the quantization bits of the quantized quadrature component to generate the corresponding amplitude and phase of polar representation of each quantization bit. The amplitude associated to each quantization bit is defined according to the decomposition of the quantized value into polar components with amplitudes given by the sets with N.sub.bq amplitudes |c.sub.I,i| and N.sub.bq amplitudes |c.sub.q,i| for the in-phase and quadrature component, respectively. As understood by a person skilled in the art based on the teaching herein, step 108 can be performed by a comparator and a LUT with the corresponding amplitudes and phases of the quantization bits. It is important to note that in certain embodiments of the present invention steps 107 and 108 can be done once by a block that quantizes and generates directly the bits, the amplitudes of polar components and the phases for the in-phase and quadrature components.

(56) Step 110 includes processing the sets with N.sub.bq amplitudes |c.sub.I,i| and N.sub.bq amplitudes |c.sub.q,i| for the in-phase and quadrature component, to generate the control information that selects the corresponding set of N.sub.bq values of V.sub.dd to be applied to the N.sub.bq amplifiers. As understood by a person skilled in the art based on the teaching herein, step 110 can be performed by a LUT with the corresponding V.sub.dd to be applied to the amplifiers. It is important to note that in certain embodiments of the present invention steps 107, 108, 109 and 110 can be done once by a block that quantizes and generates directly the bits, the amplitudes of polar components, the phases for the in-phase and quadrature components and the control information for selecting the corresponding V.sub.dd set.

(57) Step 111A includes processing the polar in-phase components by multiplying by a pulse signal with the desired spectral shape.

(58) Step 111B includes processing the polar quadrature components by multiplying by a pulse signal with the desired spectral shape.

(59) Step 112 is optional and includes multiplying the resulting signals of steps 111A and 111B by a periodic signal with the frequency of the IF signal.

(60) Step 113 includes processing the in-phase signals and quadrature signals by summing pairs of signals with same amplitude to generate a set of N.sub.bq signals with constant envelope and a sum equal to the quantized version of the envelope.

(61) Step 114 includes multiplying the resulting signals of step 113 by a periodic signal with the frequency of the RF signal.

(62) Step 115 includes the biasing of the N.sub.bq amplifiers with the corresponding set of N.sub.bq values of V.sub.dd, defined in steps 105 and 109 according the mapping rule of the decomposition of the quantized values.

(63) Step 116 includes individually amplifying each one of the constituent signals and summing the amplified signals to generate the desired output signal.

(64) Block diagram 200A of FIG. 2A is an example that illustrates an exemplary embodiment of the MQDCPSVMASCS embodiment implementing the process flowchart 100 of FIG. 1, without the optional step 112. In the example of FIG. 2A, optional components are illustrated with dashed lines. In other embodiments, additional components may be optional. In this example, it is received a bandpass data signal with a time varying envelope 201, a clock reference signal 202 for the sampling process and a channel clock 204 with the desired frequency for the output signal, are received as inputs. In another embodiment the signal 201 can be the samples of a time-varying envelope signal and the S/H inside of the digital mapper 205 is not required. In other embodiments signal 201 can be a baseband signal, or IF signal. In FIG. 5 is illustrated an exemplary embodiment of the digital mapper 205.

(65) The clock reference signal 202 can be used by the digital mapper 205, by the delay phases shifters polar converters blocks 212 and 213, and by the amplitude adjustment blocks 216 and 217. The common clock signal 202 is used to ensure that the outputs of quantizer 206-{1, . . . , N.sub.bq} and 207-{1, . . . , N.sub.bq} are time aligned, to ensure that the outputs of blocks 212 and 213 are time synchronized and the outputs of blocks 216 and 217 are also synchronized. It can be understood by a person skilled in the art that the choice of the clock reference signal is made according to the bandwidth of the input signal and the desired output signal.

(66) In the digital mapper 205 the signal carrying the information is sampled according to a clock signal 202 and are generated the in-phase and quadrature components of each sample. Still referring to FIG. 2A, the in-phase and quadrature components of each sample are converted by the N.sub.bq bit quantizer of the digital mapper 205 into two sets of quantization bits signals 206-{1, . . . , N.sub.bq} and 207-{1, . . . , N.sub.bq}, respectively. The quantization bits 206-{1, . . . , N.sub.bq} and 207-{1, . . . , N.sub.bq} are used by an internal mapper in 205, that can be a lookup table, to generate the signals 208-{1, . . . , N.sub.bq} with the in-phase amplitude coefficients |c.sub.I,i| and the signals 209-{1, . . . , N.sub.bq} with the quadrature amplitude coefficients |c.sub.q,i|, that are used in amplitude adjustment blocks 216 and 217. In 205 a voltage mapper uses control information based on signals 208-{1, . . . , N.sub.bq} and 209-{1, . . . , N.sub.bq} to generate a set N.sub.bq control signals and 210-{1, . . . , N.sub.bq} to select the set of V.sub.dd values in the lookup table 238. The set of V.sub.dd values is selected in 238 according to the control signal 210-{1, . . . , N.sub.bq} and the control signal 237, provided by the fast/slow power control block 236. The digital mapper 205 also provides an optional control signal 211 to the fast/slow power control block 236, to be used in the selection of correct set of V.sub.dd values in 238. Fast/slow power control block 236 also receives a control signal 235 with information about the maximum output RF power required for transmission.

(67) The signals 206-{1, . . . , N.sub.bq} and 207-{1, . . . , N.sub.bq} are provided to the delay phase shifters and polar converter blocks 212 and 213, to generate the phase rotations associated to each quantization bit and the corresponding polar representation and adjust the delays between the signals associated to the quantization bits. For illustration purposes and not limitation, for the quantization bits of the in-phase component 206-{1, . . . , N.sub.bq}, the bit 0 corresponds a phase of it and for the bit 1 a phase of 0. For the quantization bits of quadrature component 207-{1, . . . , N.sub.bq}, the bit 0 corresponds a phase of −π/2 and for the bit 1 a phase of π/2. The blocks 212 and 213 adjust the delays of the outputs signals 214-{1, . . . , N.sub.bq} and 215-{1, . . . , N.sub.bq} according the desired offset to be applied between the in-phase and quadrature signals 214-{1, . . . , N.sub.bq} and 215-{1, . . . , N.sub.bq} and the feedback information provided by the control signal 246-{1, . . . , N.sub.bq} from the multi amplifier amplification stage 231.

(68) In phase component signals 214-{1, . . . , N.sub.bq} are provided to the block 216 that adjusts the amplitude of each signal according the signals 208-{1, . . . , N.sub.bq} with the in-phase amplitude coefficients |c.sub.I,i| to generate the in-phase constituent signals 218-{1, . . . , N.sub.bq}. Also, the quadrature component signals 215-{1, . . . , N.sub.bq} are provided to the block 217 that adjusts the amplitude of each signal according the signals 209-{1, . . . , N.sub.bq} with the quadrature amplitude coefficients |c.sub.q,i| to generate the quadrature constituent signals 219-{1, . . . , N.sub.bq}. Both set of signals 218-{1, . . . , N.sub.bq} and 219-{1, . . . , N.sub.bq} could be submitted to a set of filters 220-{1, . . . , N.sub.bq} and 221-{1, . . . , N.sub.bq}, with the same impulsive response, to assure the desired spectral shape.

(69) The in-phase signals 222-{1, . . . , N.sub.bq} are combined in 224-{1, . . . , N.sub.bq} with the quadrature signals 223-{1, . . . , N.sub.bq} to generate a set of constituent signals with quasi or constant envelope signals 225-{1, . . . , N.sub.bq}. Signals 225-{1, . . . , N.sub.bq} are up converted to the RF frequency in 228-{1, . . . , N.sub.bq} through a multiplication by a periodic signal 227 with the desired RF frequency defined by clock 204. The signals 229-{1, . . . , N.sub.bq} with quasi or constant envelope are the inputs of the corresponding power amplifiers (PAs) 230-{1, . . . , N.sub.bq} of the amplification stage. In another embodiment PAs 230-{1, . . . , N.sub.bq} include power amplifiers of class A. In another embodiment PAs 230-{1, . . . , N.sub.bq} include power amplifiers of class AB, B and C.

(70) Each PA in the set of N.sub.bq amplifiers 231 has an unique V.sub.dd voltage value from the set of V.sub.dd values and their bias 242-{1, . . . , 2N.sub.bq} applied to the amplification stage with N.sub.bq amplifiers 231. The V.sub.dd values 242-{1, . . . , N.sub.bq} and their bias 242-{N.sub.bq+1, . . . ,2N.sub.bq}, that are applied to the N.sub.bq amplifiers 230-{1, . . . , N.sub.bq}, are the output of the power and V.sub.dd control block 243 composed by the fast and slow power control block 236, the lookup table 238 that sends the control signals 239-{1, . . . ,2N.sub.bq} to the DC/DC (Direct Current/Direct Current) converter 240 that define the set of V.sub.dd values 241-{1, . . . ,2N.sub.bq} to be generated by the DC/DC converter. Block 241a is an optional low-dropout regulator (LDO). When block 241a is absent signals 241-{1, . . . , 2N.sub.bq} and 242-{1, . . . , 2N.sub.bq} are equal. The supply signal 247 is used by the DC/DC converter 240 (and by the optional LDO 241a) to generate the set of V.sub.dd values and bias signals, used in the amplification stage 231.

(71) The outputs of PAs 232-{1, . . . , N.sub.bq} are coupled together in a combiner 233 using well known combining techniques such as active combiners or other techniques such as Wilkinson, hybrid or transformers. Alternatively, the outputs of PAs 232-{1, . . . , N.sub.bq} can be coupled through LC matching for a minimal power loss. Amplification stage embodiments according to power amplification methods and systems of the present invention will be further described in section 3.

(72) The phase control circuit 245 is employed to generate feedback control signals 246-{1, . . . , N.sub.bq} to blocks 212 and 213 to compensate phase mismatches among the amplifiers, based on the information signals 244-{1, . . . , N.sub.bq}.

(73) Block diagram 200B of FIG. 2B is an example that illustrates an exemplary embodiment of the MQDCPSVMASCS embodiment implementing the process flowchart 100 of FIG. 1, with the optional step 112. In the example of FIG. 2B, optional components are illustrated with dashed lines. In other embodiments, additional components may be optional. In this example is received a bandpass data signal with time varying envelope 201, a clock reference signal 202 for the sampling process, an intermediate channel clock 203, with the desired intermediate frequency, and a RF channel clock 204, with the desired frequency for the output signal, are received as inputs. In another embodiment the signal 201 can be the samples of a time-varying envelope signal and the S/H inside of the digital mapper 205 is not required. In other embodiments signal 201 can be a baseband signal, or IF signal. In FIG. 5 is illustrated an exemplary embodiment of the digital mapper 205.

(74) The clock reference signal 202 can be used by the digital mapper 205, by the delay phases shifters polar converters blocks 212 and 213, and by the amplitude adjustment blocks 216 and 217. The common clock signal 202 is used to ensure that the outputs of quantizer 206-{1, . . . , N.sub.bq} and 207-{1, . . . , N.sub.bq} are time aligned, to ensure that the outputs of blocks 212 and 213 are time synchronized and the outputs of blocks 216 and 217 are also synchronized. It can be understood by a person skilled in the art that the choice of the clock reference signal is made according to the bandwidth of the input signal and the desired output signal.

(75) In the digital mapper 205 the signal carrying the information is sampled according to a clock signal 202 and are generated the in-phase and quadrature components of each sample. Still referring to FIG. 2B, the in-phase and quadrature components of each sample are converted by the N.sub.bq bit quantizer of the digital mapper 205 into two sets of quantization bits signals 206-{1, . . . , N.sub.bq} and 207-{1, . . . , N.sub.bq}, respectively. The quantization bits 206-{1, . . . , N.sub.bq} and 207-{1, . . . , N.sub.bq} are used by an internal mapper in 205, that can be a lookup table, to generate the signals 208-{1, . . . , N.sub.bq} with the in-phase amplitude coefficients |c.sub.I,i| and the signals 209-{1, . . . , N.sub.bq} with the quadrature amplitude coefficients |c.sub.I,i|, that are used in amplitude adjustment blocks 216 and 217. In 205 a voltage mapper uses the signals 208-{1, . . . , N.sub.bq} and 209-{1, . . . , N.sub.bq} to generate a set N.sub.bq control signals and 210-{1, . . . , N.sub.bq} to select the set of V.sub.dd values in the lookup table 238. The set of V.sub.dd values is selected in 238 according the control signal 210-{1, . . . , N.sub.bq} and the control signal 237 provided by the fast/slow power control block 236. The digital mapper 205 also provides an optional control signal 211 to the fast/slow power control block 236, to be used in the selection of correct set of V.sub.dd values in 238.

(76) The signals 206-{1, . . . , N.sub.bq} and 207-{1, . . . , N.sub.bq} are provided to the delay phase shifters and polar converter blocks 212 and 213, to generate the phase rotations associated to each quantization bit and the corresponding polar representation and adjust the delays between the signals associated to the quantization bits. For illustration purposes and not limitation, for the quantization bits of the in-phase component 206-{1, . . . , N.sub.bq}, the bit 0 corresponds a phase of II and for the bit 1 a phase of 0. For the quantization bits of quadrature component 207-{1, . . . , N.sub.bq}, the bit 0 corresponds a phase of −π/2 and for the bit 1 a phase of π/2. The blocks 212 and 213 adjust the delays of the outputs signals 214-{1, . . . , N.sub.bq} and 215-{1, . . . , N.sub.bq} according the desired offset to be applied between the in-phase and quadrature signals 214-{1, . . . , N.sub.bq} and 215-{1, . . . , N.sub.bq} and the feedback information provided by the control signals 246-{1, . . . , N.sub.bq} from the multi amplifier amplification stage 231.

(77) In phase component signals 214-{1, . . . , N.sub.bq} are provided to the block 216 that adjusts the amplitude of each signal according the signals 208-{1, . . . , N.sub.bq} with the in-phase amplitude coefficients |c.sub.I,i| to generate the in-phase constituent signals 218-{1, . . . , N.sub.bq}. Also, the quadrature component signals 215-{1, . . . , N.sub.bq} are provided to the block 217 that adjusts the amplitude of each signal according the signals 209-{1, . . . , N.sub.bq} with the quadrature amplitude coefficients |c.sub.I,i| to generate the quadrature constituent signals 219-{1, . . . , N.sub.bq}. Both set of signals 218-{1, . . . , N.sub.bq} and 219-{1, . . . , N.sub.bq} could be submitted to a set of filters 220-{1, . . . , N.sub.bq} and 221-{1, . . . , N.sub.bq}, with the same impulsive response, to assure the desired spectral shape.

(78) In-phase signals 222b-{1, . . . , N.sub.bq} in an intermediate frequency are obtained by multiplying in 222a-{1, . . . , N.sub.bq} the signals 222-{1, . . . , N.sub.bq} by a pulse periodic signal 218b with the desired intermediate frequency provided by the oscillator 218a according the reference signal 203. IF quadrature signals 223b-{1, . . . , N.sub.bq} are obtained by multiplying in 223a-{1, . . . , N.sub.bq} the signals 223-{1, . . . , N.sub.bq} by the pulse periodic signal 218b. The in-phase signals 222b-{1, . . . , N.sub.bq} are combined in 224-{1, . . . , N.sub.bq} with the quadrature signals 223b-{1, . . . , N.sub.bq} to generate a set of constituent signals with quasi or constant envelope signals 225-{1, . . . , N.sub.bq}. The signals 225-{1, . . . , N.sub.bq} are up converted to the RF frequency in 228-{1, . . . , N.sub.bq} through a multiplication by a periodic signal 227 generated by the oscillator 226 with the desired RF frequency defined by clock 204. The signals 229-{1, . . . N.sub.bq} with quasi or constant envelope are the inputs of the corresponding PAs 230-{1, . . . , N.sub.bq} of the amplification stage. In another embodiment PAs 230-{1, . . . , N.sub.bq} include power amplifiers of class A. In another embodiment PAs 230-{1, . . . , N.sub.bq} include power amplifiers of class AB, B and C.

(79) Each PA in the set of N.sub.bq amplifiers 231 has an unique V.sub.dd voltage value from the set of V.sub.dd values and their bias 242-{1, . . . , 2N.sub.bq} applied to the amplification stage with N.sub.bq amplifiers 231. The V.sub.dd values 242-{1, . . . , N.sub.bq} and their bias 242-{N.sub.bq+1, . . . , 2N.sub.bq} that are applied to the N.sub.bq amplifiers 230-{1, . . . , N.sub.bq}, are the output of the power and V.sub.dd control block 243 composed by the fast and slow power control block 236, the lookup table 238 that sends the control signals 239-{1, . . . , 2N.sub.bq} to the DC/DC converter 240 that define the set of V.sub.dd values 241-{1, . . . , 2N.sub.bq} to be generated by the DC/DC converter. Block 241a is an optional LDO. When block 241a is absent signals 241-{1, . . . , 2N.sub.bq} and 242-{1, . . . , 2N.sub.bq} are equal. The supply signal 247 is used by the DC/DC converter 240 (and by the optional LDO 241a) to generate the set of V.sub.dd values and bias signals, used in the amplification stage 231.

(80) The outputs of PAs 232-{1, . . . , N.sub.bq} are coupled together in a combiner 233 using well known combining techniques such as active combiners or other techniques such as Wilkinson, hybrid or transformers. Alternatively, the outputs of PAs 232-{1, . . . , N.sub.bq} can be coupled through LC matching for a minimal power loss. Amplification stage embodiments according to power amplification methods and systems of the present invention will further described in section 3.

(81) In another embodiment a phase control circuit 245 could be employed to generate feedback control signals 246-{1, . . . , N.sub.bq} to blocks 212 and 213 to compensate phase mismatches among amplifiers, based on the information signals 244-{1, . . . , N.sub.bq}.

(82) 2.2 Multi Quantized Digitally Controlled Power Supply Voltage for Multi Amplifier Stages with Switched Amplifiers

(83) According to the Multi Quantized Digitally Controlled Power Supply Voltage for Multi Amplifier Stages with Switched Amplifiers (MQDCPSVMASSA) embodiment of the invention, for ease of illustration and not limitation, a time-varying envelope signal is decomposed into N.sub.bq quasi or constant envelope constituent signals with same amplitude and different phase belonging to a discrete alphabet. The constituent signals are amplified individually, and then summed to obtain an amplified version of the quantized time-varying complex envelope signal. It is noted that one quantizer with N.sub.bq quantization bits and N.sub.bq amplification branches are employed in these embodiments for purposes of illustration, and not limitation. Each V.sub.dd,i in the set of V.sub.dd values has different values proportional the corresponding set of coefficients c.sub.I,i and c.sub.q,i that are constant over time and the in-phase and quadrature components have the same amplitude and different phases, being the amplified version of the quantized envelope the result of the sum of all amplifiers outputs. In other embodiments, several sets of supply voltage values V.sub.dd are available and the set may change between data blocks. In other embodiment, the V.sub.dd may change between samples. The scope of the invention covers the use of other numbers of branches, multiple sets of V.sub.dd and DRi=DRq and DRi≠DRq and implementation of such variations will be apparent to persons skilled in the art based on the teachings contained herein.

(84) Operation of the MQDCPSVMASSA embodiments shall be described further with reference to the flowchart of FIG. 3. Optional steps are illustrated with dashed lines. The process starts at step 301, which includes receiving a time varying envelope bandpass signal. In another embodiment this involves receiving the desired input RF signal. In another embodiment, this involves receiving the desired IF signal. In another embodiment, this involves receiving a baseband signal. In another embodiment, this involves receiving the samples of the time varying envelope signal or receiving the samples the in-phase and quadrature components of a time varying envelope signal.

(85) Step 302 includes receiving a clock signal set according to the signal frequency of the input signal.

(86) Step 303 includes receiving a clock signal set according to a desired sample rate of the input signal. It is important to mention that, as understood by a person skilled in the art, the sampling rate may vary according to the bandwidth of the input signal and the desired time resolution of the sampling process.

(87) Step 304 includes receiving a clock signal in accordance with the frequency of the desired output RF signal.

(88) Step 305 includes receiving slow and fast power control information to control the power output level after the amplification stage by selecting different sets of V.sub.dd values over different information blocks or selecting different sets of V.sub.dd values for the different samples of the envelope of the input signal carrying the information to be sent.

(89) Step 306 includes sampling the input signal in accordance with the sampling rate to generate the samples of the input signal. In the embodiment example of FIG. 3, step 306 is implemented by a sampling circuit or a sample and hold (S/H) circuit. In embodiments with multicarrier signals, step 306 can be implemented by a fast Fourier transform (FFT) with a higher time resolution to fulfill the sampling rate requirement.

(90) Step 307 includes processing the signal to generate in-phase and quadrature components.

(91) Step 308 includes processing individually by a quantizer the in-phase and quadrature components to generate the quantization bits that correspond to the quantized value of the in-phase and the quantization bits that correspond to the quantized value of the quadrature component, respectively. As understood by a person skilled in the art based on the teaching herein, step 308 can be performed by a block using a single quantizer. Also, as understood by a person skilled in the art based on the teaching herein, step 308 can be performed by a comparator and a LUT with the corresponding quantization bits of the quantized values.

(92) Step 309 includes processing individually the quantization bits of the quantized in-phase component, to generate the corresponding V.sub.dd amplitude and phase associated to the polar representation of each quantization bit and processing individually the quantization bits of the quantized quadrature component to generate the corresponding V.sub.dd amplitude and phase associated to the polar representation of each quantization bit. The amplitude of each V.sub.dd associated to each component is obtained according to the decomposition of the quantized value into polar components with amplitudes given by the sets with N.sub.bq amplitudes |c.sub.I,i| and N.sub.bq amplitudes |c.sub.q,i| for the in-phase and quadrature component, respectively. As understood by a person skilled in the art based on the teaching herein, step 308 can be performed by a comparator and a LUT with the corresponding amplitudes and phases of each quantization bit. It is important to note that in certain embodiments of the present invention steps 307 and 308 can be done once by a block that quantizes and generates directly the bits, the V.sub.dd′s amplitudes associated to each polar component and the phases for the in-phase and quadrature components.

(93) Step 310A includes processing the polar in-phase components by multiplying by a pulse signal with the desired spectral shape.

(94) Step 310B includes processing the polar quadrature components by multiplying by a pulse signal with the desired spectral shape.

(95) Step 311 is optional and includes multiplying the resulting signals of steps 310A and 310B by a periodic signal with the frequency of the IF signal.

(96) Step 312 includes processing the in-phase signals and quadrature signals by summing pairs of signals with same amplitude to generate a set of N.sub.bq signals with constant envelope and a sum equal to the quantized version of the envelope.

(97) Step 313 includes multiplying the resulting signals of step 312 by a periodic signal with the frequency of the RF signal.

(98) Step 314 includes the biasing of the N.sub.bq amplifiers with the corresponding set of N.sub.bq values of V.sub.dd, defined in step 309 according to the mapping rule of the decomposition of the quantized values.

(99) Step 315 includes individually amplifying each of one of the constituent signals and summing the amplified signals to generate the desired output signal.

(100) Block diagram 400A of FIG. 4A is an example that illustrates an embodiment of the MQDCPSVMASSA, implementing the process flowchart 300 of FIG. 3, without optional step 311. In the example of FIG. 4A, optional components are illustrated with dashed lines. In other embodiments, additional components may be optional.

(101) In this example a time varying envelope signal 401, a clock reference signal 402 for the sampling process and a channel clock 404 with the desired frequency for the output signal are received as inputs. In another embodiment the signal 401 can be the samples of a time-varying envelope signal and the S/H inside of the digital mapper 405 is not required. In other embodiments signal 401 can be a baseband signal, or IF signal. In FIG. 5 is illustrated an exemplary embodiment of the digital mapper 405.

(102) The clock reference signal 402 can be used by the digital mapper 405, by the delay phases shifters polar converters blocks 412 and 413. The common clock signal 402 is used to ensure that the outputs of quantizer 406-{1, . . . , N.sub.bq} and 407-{1, . . . , N.sub.bq} are time aligned and to ensure that the outputs of blocks 412 and 413 are synchronized. It can be understood by a person skilled in the art that the choice of the clock reference signal 402 is made according the bandwidth of the input signal and the desired output signal.

(103) In the digital mapper 405 the signal carrying the information is sampled according to a clock signal 402 and are generated the in-phase and quadrature components of each sample. Still referring to FIG. 4A, the in-phase and quadrature components of each sample are converted by the N.sub.bq bit quantizer of the digital mapper 405 into two sets of quantization bits signals 406-{1, . . . , N.sub.bq} and 407-{1, . . . , N.sub.bq}, respectively. The quantization bits 406-{1, . . . , N.sub.bq} and 407-{1, . . . , N.sub.bq} are used by an internal mapper in 405, that can be a lookup table, to generate the in-phase amplitude coefficients |c.sub.I,i| and the quadrature amplitude coefficients |c.sub.q,i|, that are used in a voltage mapper in 405 to generate a set N.sub.bq control signals 410-{1, . . . , N.sub.bq} to select the set of V.sub.dd values in the lookup table 434. The set of V.sub.dd values is selected in 434 according to the control signals 410-{1, . . . , N.sub.bq} and the control signal 433 provided by the fast/slow power control block 432. The digital mapper 405 also provides an optional control signal 411 to the fast/slow power control block 432, to be used in the selection of correct set of V.sub.dd values in 434. Block 432 also receives a power control signal 431 from the system with information about the output power needed for the transmission.

(104) The signals 406-{1, . . . , N.sub.bq} and 407-{1, . . . , N.sub.bq} are provided to the delay phase shifters and polar converter blocks 412 and 413, to generate the phase rotations associated to each quantization bit and the corresponding polar representation and adjust the delays between the signals associated to the quantization bits. For illustration purposes and not limitation, for the quantization bits of the in-phase component 406-{1, . . . , N.sub.bq}, the bit 0 corresponds a phase of n and for the bit 1 a phase of 0. For the quantization bits of quadrature component 407-{1, . . . , N.sub.bq}, the bit 0 corresponds a phase of −π/2 and for the bit 1 a phase of π/2. The blocks 412 and 413 adjust the delays and polarities of the outputs signals 414-{1, . . . , N.sub.bq} and 415-{1, . . . , N.sub.bq} according the desired offset to be applied between the in-phase and quadrature signals 414-{1, . . . , N.sub.bq} and 415-{1, . . . , N.sub.bq} and the feedback information provided by the control signal 442-{1, . . . , N.sub.bq} from the multi amplifier amplification stage 427.

(105) Both set of signals 414-{1, . . . , N.sub.bq} and 415-{1, . . . , N.sub.bq} may be submitted to a set of filters 416-{1, . . . , N.sub.bq} and 417-{1, . . . , N.sub.bq}, with the same impulsive response, to assure the desired spectral shape.

(106) The in-phase signals 418-{1, . . . , N.sub.bq} are combined in 420-{1, . . . , N.sub.bq} with the quadrature signals 419-{1, . . . , N.sub.bq} to generate a set of constituent signals with quasi or constant envelope signals 421-{1, . . . , N.sub.bq}. Blocks 418c-{1, . . . , N.sub.bq} and 419c-{1, . . . , N.sub.bq} are optional, and when absent, the signals 418-{1, . . . , N.sub.bq} and 418d-{1, . . . , N.sub.bq}, and 419-{1, . . . , N.sub.bq} and 419d-{1, . . . , N.sub.bq}, are equal, respectively. The signals 421-{1, . . . , N.sub.bq} are up converted to the RF frequency in 424-{1, . . . , N.sub.bq} through a multiplication by a periodic signal 423 with the desired RF frequency defined by clock 404. The signals 425-{1, . . . , N.sub.bq} with quasi or constant envelope are the inputs of the corresponding power amplifiers (PAs) 426-{1, . . . , N.sub.bq} of the amplification stage. In another embodiment PAs 426-{1, . . . , N.sub.bq} include switched power amplifiers of class D. In another embodiment PAs 426-{1, . . . , N.sub.bq} include switched power amplifiers of class E, F, S, or other class of switched power amplifiers.

(107) Each PA in the set of N.sub.bq amplifiers 427 has a unique V.sub.dd voltage value from the set of V.sub.dd values 438-{1, . . . , N.sub.bq} applied to the amplification stage with N.sub.bq amplifiers 427. The V.sub.dd values 438-{1, . . . , N.sub.bq} applied to the N.sub.bq amplifiers 426-{1, . . . , N.sub.bq} are the outputs of the power and V.sub.dd control block 439 composed by the fast and slow power control block 432, the lookup table 434 that sends the control signals 435-{1, . . . , N.sub.bq} to the DC-DC converter 436 that define the set of V.sub.dd values 437-{1, . . . , N.sub.bq} to be generated by the DC/DC converter. Block 437a is an optional LDO. When block 437a is absent signals 437-{1, . . . , N.sub.bq} and 438-{1, . . . , N.sub.bq} are equal. The supply signal 443 is used by the DC/DC converter 436 (and by the optional LDO 437a) to generate the set of V.sub.dd values and bias signals, used in the amplification stage 427.

(108) The outputs of PAs 428-{1, . . . , N.sub.bq} are coupled together in a combiner 429 using well known combining techniques such as active combiners or other techniques such as Wilkinson, hybrid or transformers. Alternatively, the outputs of PAs 428-{1, . . . , N.sub.bq} can be coupled through LC matching for a minimal power loss. Amplification stage embodiments according to power amplification methods and systems of the present invention will further described in section 3.

(109) The phase control circuit 441 is employed to generate feedback control signals 442-{1, . . . , N.sub.bq} to blocks 412 and 413 to compensate phase mismatches among amplifiers, based on the information signals 440-{1, . . . , N.sub.bq}.

(110) In other embodiments the signal 423 can be a sinusoidal signal or a pulse train signal with frequency selected according to the desired frequency of the output signal.

(111) In other embodiments the combiner's output signal 430 is submitted to a bandpass filter with central frequency equal to the desired carrier frequency of the output signal.

(112) Block diagram 400B of FIG. 4B is an example that illustrates an embodiment of the MQDCPSVMASSA, implementing the process flowchart 300 of FIG. 3, with the optional step 311. In the example of FIG. 4B, optional components are illustrated with dashed lines. In other embodiments, additional components may be optional.

(113) In this example a time varying envelope signal 401, a clock reference signal 402 for the sampling process, an intermediate channel clock 403, with the desired intermediate frequency, and a RF channel clock 404 with the desired frequency for the output signal are received as inputs. In another embodiment the signal 401 can be the samples of a time-varying envelope signal and the S/H inside of the digital mapper 405 is not required. In other embodiments signal 401 can be a baseband signal, or IF signal. In FIG. 5 is illustrated an exemplary embodiment of the digital mapper 405.

(114) The clock reference signal 402 can be used by the digital mapper 405, by the delay phases shifters polar converters blocks 412 and 413. The common clock signal 402 is used to ensure that the outputs of quantizer 406-{1, . . . , N.sub.bq} and 407-{1, . . . , N.sub.bq} are time aligned and to ensure that the outputs of blocks 412 and 413 are synchronized. It can be understood by a person skilled in the art that the choice of the clock reference signal 402 is made according the bandwidth of the input signal and the desired output signal.

(115) In the digital mapper 405 the signal carrying the information is sampled according to a clock signal 402 and are generated the in-phase and quadrature components of each sample. Still referring to FIG. 4B, the in-phase and quadrature components of each sample are converted by the N.sub.bq bit quantizer of the digital mapper 405 into two sets of quantization bits signals 406-{1, . . . , N.sub.bq} and 407-{1, . . . , N.sub.bq}, respectively. The quantization bits 406-{1, . . . , N.sub.bq} and 407-{1, . . . , N.sub.bq} are used by an internal mapper in 405, that can be a lookup table, to generate the in-phase amplitude coefficients |c.sub.I,i| and the quadrature amplitude coefficients |c.sub.q,i| that are used in a voltage mapper in 405 to generate a set N.sub.bq control signals 410-{1, . . . , N.sub.bq} to select the set of V.sub.dd values in the lookup table 434. The set of V.sub.dd values is selected in 434 according the control signals 410-{1, . . . , N.sub.bq} and the control signal 433 provided by the fast/slow power control block 432. The digital mapper 405 also provides an optional control signal 411 to the fast/slow power control block 432, to be used in the selection of correct set of V.sub.dd values in 434.

(116) The signals 406-{1, . . . , N.sub.bq} and 407-{1, . . . , N.sub.bq} are provided to the delay phase shifters and polar converter blocks 412 and 413, to generate the phase rotations associated to each quantization bit and the corresponding polar representation and adjust the delays between the signals associated to the quantization bits. For illustration purposes and not limitation, for the quantization bits of the in-phase component 406-{1, . . . , N.sub.bq}, the bit 0 corresponds a phase of it and for the bit 1 a phase of 0. For the quantization bits of quadrature component 407-{1, . . . , N.sub.bq}, the bit 0 corresponds a phase of −π/2 and for the bit 1 a phase of π/2. The blocks 412 and 413 adjust the delays and polarities of the outputs signals 414-{1, . . . , N.sub.bq} and 415-{1, . . . , N.sub.bq} according the desired offset to be applied between the in-phase and quadrature signals 414-{1, . . . , N.sub.bq} and 415-{1, . . . , N.sub.bq} and the feedback information provided by the control signal 442-{1, . . . , N.sub.bq} from the multi amplifier amplification stage 427.

(117) Both set of signals 414-{1, . . . , N.sub.bq} and 415-{1, . . . , N.sub.bq} could be submitted to a set of filters 416-{1, . . . , N.sub.bq} and 417-{1, . . . , N.sub.bq}, with the same impulsive response, to assure the desired spectral shape.

(118) In-phase signals 418d-{1, . . . , N.sub.bq} in an intermediate frequency are obtained by multiplying in 418c-{1, . . . , N.sub.bq} the signals 418-{1, . . . , N.sub.bq} by a pulse periodic signal 418b with the desired intermediate frequency. IF quadrature signals 419d-{1, . . . , N.sub.bq} are obtained by multiplying in 419c-{1, . . . , N.sub.bq} the signals 419-{1, . . . , N.sub.bq} by a pulse periodic signal 418b with the desired intermediate frequency. The in-phase signals 418d-{1, . . . , N.sub.bq} are combined in 420-{1, . . . , N.sub.bq} with the quadrature signals 419d-{1, . . . , N.sub.bq} to generate a set of constituent signals with quasi or constant envelope signals 421-{1, . . . , N.sub.bq}. The signals 421-{1, . . . , N.sub.bq} are up converted to the RF frequency in 424-{1, . . . , N.sub.bq} through a multiplication by a periodic signal 423 with the desired RF frequency defined by clock 404. The signals 425-{1, . . . , N.sub.bq} with quasi or constant envelope are the inputs of the corresponding power amplifiers (PAs) 426-{1, . . . , N.sub.bq} of the amplification stage. In another embodiment PAs 426-{1, . . . , N.sub.bq} include switched power amplifiers of class D. In another embodiment PAs 426-{1, . . . , N.sub.bq} include switched power amplifiers of class E, F, S, or other class of switched power amplifiers.

(119) Each PA in the set of N.sub.bq amplifiers 427 has a unique V.sub.dd voltage value from the set of V.sub.dd values 438-{1, . . . , N.sub.bq} applied to the amplification stage with N.sub.bq amplifiers 427. The V.sub.dd values 438-{1, . . . , N.sub.bq} applied to the N.sub.bq amplifiers 426-{1, . . . , N.sub.bq} are the outputs of the power and V.sub.dd control block 439 composed by the fast and slow power control block 432, the lookup table 434 that sends the control signals 435-{1, . . . , N.sub.bq} to the DC/DC converter 436 that define the set of V.sub.dd values 437-{1, . . . , N.sub.bq} to be generated by the DC/DC converter. Block 437a is an optional LDO. When block 437a is absent signals 437-{1, . . . , N.sub.bq} and 438-{1, . . . , N.sub.bq} are equal. The supply signal 443 is used by the DC/DC converter 436 (and by the optional LDO 437a) to generate the set of V.sub.dd values and bias signals, used in the amplification stage 427.

(120) The outputs of PAs 428-{1, . . . , N.sub.bq} are coupled together in a combiner 429 using well known combining techniques such as active combiners or other techniques such as Wilkinson, hybrid or transformers. Alternatively, the outputs of PAs 428-{1, . . . , N.sub.bq} can be coupled through LC matching for a minimal power loss. Amplification stage embodiments according to power amplification methods and systems of the present invention will further described in section 3.

(121) In another embodiment a phase control circuit 441 could be employed to generate feedback control signals 442-{1, . . . , N.sub.bq} to blocks 412 and 413 to compensate phase mismatches among amplifiers, based on the information signals 440-{1, . . . , N.sub.bq}.

(122) In other embodiments the signal 423 can be a sinusoidal signal or a pulse train signal with frequency selected according to the desired frequency of the output signal.

(123) In other embodiments the combiner's output signal 430 is submitted to a bandpass filter with central frequency equal to the desired carrier frequency of the output signal.

(124) Block diagram 500 of FIG. 5 is an example that illustrates an embodiment of the digital mapper block of FIGS. 2A and 2B (block 205) and FIGS. 4A and 4B (block 405). In this example a time varying envelope signal 501, a clock reference signal 502 for the sampling process are received as inputs. In another embodiment 501 can be the samples of a time-variant envelope signal and the S/H 503 is not required. In another embodiment the input signal 501 can be the samples of the in-phase and quadrature components of a time varying envelope signal and the phase splitter 505 and the S/H are not required.

(125) The clock reference signal 502 can be used by the S/H block 503, by the I/Q block 505, by the quantizer 508, by the amplitude component mapper 513 and by the V.sub.dd voltage mapper 517. Samples 504 are provided to the phase splitter 505 that generates the in-phase and quadrature components 506 and 507 for each sample. Signals 506 and 507 are supplied to the quantizer 508, that generates the quantization bits 511-{1, . . . , N.sub.bq} and 512-{1, . . . , N.sub.bq}, which are used by the component amplitude mapper 513, that can be a lookup table, to generate the in-phase amplitude coefficients |c.sub.I,i| and the quadrature amplitude coefficients |c.sub.q,i|.

(126) The in-phase quantization bits 509-{1, . . . , N.sub.bq} and the quadrature quantization bits 510-{1, . . . , N.sub.bq} are the inputs of the blocks 212 and 213 of FIGS. 2A and 2B. Referring to FIGS. 4A and 4B, signals 509-{1, . . . , N.sub.bq} and 510-{1, . . . , N.sub.bq} correspond to inputs of blocks 412 and 413.

(127) Two sets of signals with amplitude coefficients 514-{1, . . . , N.sub.bq} and 515-{1, . . . , N.sub.bq} are generated according the decomposition rule applied to the quantized values of the in-phase and quadrature components into fixed amplitude components and sent to the blocks 216 and 217 of FIGS. 2A and 2B. Referring FIGS. 2A and 2B, signals 514-{1, . . . , N.sub.bq} and 515-{1, . . . , N.sub.bq} correspond to the signals 208-{1, . . . , N.sub.bq} and 209-{1, . . . , N.sub.bq}. Referring FIGS. 4A and 4B, signals 514-{1, . . . , N.sub.bq} and 515-{1, . . . , N.sub.bq} are not needed to control any amplitude adjustment of the signal components. Another set of control signals proportional to the amplitude coefficients are generated 516-{1, . . . , N.sub.bq} and delivered to the V.sub.dd voltage mapper 517. These signals are used at V.sub.dd voltage mapper in 517 to generate a set N.sub.bq control signals 518-{1, . . . , N.sub.bq} that correspond to the signals 210-{1, . . . , N.sub.bq} of FIGS. 2A and 2B or to the signals 410-{1, . . . , N.sub.bq} of FIGS. 4A and 4B. The set of V.sub.dd values 518-{1, . . . , N.sub.bq} is generated according the control signals 516-{1, . . . , N.sub.bq}. The V.sub.dd voltage mapper 517 also provides an optional control signal 519 (signal 211 in FIGS. 2A and 2B or signal 411 in FIGS. 4A and 4B) to the fast/slow power control block of FIGS. 2A and 2B.

(128) It can be understood by a person skilled in the art that the choice of the clock reference signal is made according the bandwidth of the input signal and the desired output signal. As understood by a person skilled in the art, other reference clock signals and different reference clock signals may be used by the different blocks. It is noted that one quantizer is employed together with two mappers for purposes of illustration, and not limitation. The scope of the invention covers the use of more quantizers and different number of mappers, and implementation of such variations will be apparent to persons skilled in the art based on the teachings contained herein. In yet another exemplary embodiment, an apparatus for digital mapper block may include a FPGA and lookup tables. The phase splitter may add an offset between the in-phase and quadrature samples.

(129) 3. Parallel Amplifier Stage Embodiments

(130) Block diagram 600 of FIG. 6, illustrates a parallel and multi power amplifier stage embodiment with transconductance based amplifiers, namely for class A operation, according to an embodiment of the present invention. In the example of FIG. 6, optional components are illustrated with dashed lines. In other embodiments, additional components may be optional. The amplifier stage embodiment 600 includes a plurality of PA branches 608-{1, . . . , N.sub.bq}. Signals 601-{1, . . . , N.sub.bq} incoming from respective mixing products of the constituent signals components by a periodic signal represent inputs for the overall amplification stage 600. Referring FIGS. 2A and 2B, the input signals are the signals 229-{1, . . . , N.sub.bq}.

(131) PA branches 608-{1, . . . , N.sub.bq} outputs have different power levels as the result of amplification of respective signals 601-{1, . . . , N.sub.bq} according the supply voltage value V.sub.dd, applied to each power amplifier branch. The power amplification level of each PA branch 608-{1, . . . , N.sub.bq} is set according to the input signal and the power supply signals and input control signals 242-{1, . . . ,2N.sub.bq} (see FIGS. 2A and 2B).

(132) The control signals 610-{1, . . . , N.sub.bq} are used by the bias and control circuit block 611-{1, . . . , N.sub.bq}. This block sets the desired operating point of the power amplifier cells 606-{1, . . . , N.sub.bq}. Referring FIGS. 2A and 2B, the control signals are signals 606-{1, . . . , N.sub.bq} that are provided by the LUT 238.

(133) In the embodiment of FIG. 6, each PA branch 608-{1, . . . , N.sub.bq} includes a limiter 602-{1, . . . , N.sub.bq}, an optional driver 603-{1, . . . , N.sub.bq}, an optional output matching network 604-{1, . . . , N.sub.bq} and a power amplifier unit cell 606-{1, . . . , N.sub.bq}. In other embodiments, an input matching network can be also used. In other embodiments, power drivers 603-{1, . . . , N.sub.bq} as illustrated in FIG. 6, may also be added in a PA branch prior to the power amplifier element to reinforce the input signal 605-{1, . . . , N.sub.bq}. When power drivers 603-{1, . . . , N.sub.bq} are not employed, the signals at the limiter output 602a-{1, . . . , N.sub.bq} are equal to signals 603a-{1, . . . , N.sub.bq}. In embodiments, power drivers are employed whenever a required output power level may not be achieved in a single amplifying stage due to insufficient driving power. According to embodiment 600, PAs 606-{1, . . . , N.sub.bq} include a transconductance based amplifier. In the example of FIG. 6, power amplifiers 606-{1, . . . , N.sub.bq} include transconductance devices, namely Field Effect Transistor (FET), T-{1, . . . , N.sub.bq}, inductors L-{1, . . . , N.sub.bq}, and supply voltages Vsupply-{1, . . . , N.sub.bq}, which are provided by signals 609-{1, . . . , N.sub.bq}. Referring FIGS. 2A and 2B, the supply and bias signals are the set of signals 242-{1, . . . , 2N.sub.bq} and the outputs of PA branches 607-{1, . . . , N.sub.bq} are coupled at the combiner 233 to generate the output signal 234.

(134) Block diagram 700 of FIG. 7 illustrates another multi power amplifier output stage with switched based amplifiers branches, namely on class D operation, according to an embodiment of the present invention. In the example of FIG. 7, optional components are illustrated with dashed lines. In other embodiments, additional components may be optional. Similarly to the embodiment of FIG. 6, the output stage 700 of FIG. 7 includes a plurality of PA branches 708-{1, . . . , N.sub.bq}. Signals 701-{1, . . . , N.sub.bq} incoming from respective the products of the constituent signals components by a periodic signal represent inputs for amplification stage 700. Referring FIGS. 4A and 4B, the input signals are the set of signals 425-{1, . . . , N.sub.bq}. According to this embodiment of the present invention, signals 701-{1, . . . , N.sub.bq} represent the constant envelope constituent signals at the inputs of the power amplifiers.

(135) Each of PA branch 708-{1, . . . , N.sub.bq} may include multiple power amplification stages represented by a limiter 702-{1, . . . , N.sub.bq} that provides a signal 702a-{1, . . . , N.sub.bq} to the power drivers in parallel 703-{1, . . . , N.sub.bq} and 704-{1, . . . , N.sub.bq} each one providing an input signal 703a-{1, . . . , N.sub.bq} and 704a-{1, . . . , N.sub.bq}, respectively, to the corresponding switches TP-{1, . . . , N.sub.bq} and TN-{1, . . . , N.sub.bq} of each power amplifier 706-{1, . . . , N.sub.bq}.

(136) Power amplifiers 706-{1, . . . , N.sub.bq} have power supply voltages Vsupply-{1, . . . , N.sub.bq}, which are provided by signals 709-{1, . . . , N.sub.bq}. Referring FIGS. 4A and 4B, these signals are the set of signals 438-{1, . . . , N.sub.bq}. To generate the desired output signal, the outputs of PA branches 707-{1, . . . , N.sub.bq} are coupled in the combiner 429 of FIGS. 4A and 4B to generate the output signal 430. Accordingly, minimal power loss is incurred in summing the outputs of PAs 707-{1, . . . , N.sub.bq}. In other embodiments, an input and output matching networks can be also used.

(137) Embodiments are not limited to switches based on type of FET channel N and P devices. A person skilled in the art will appreciate, for example, that embodiments of the present invention may be implemented using Bipolar Junction Transistors (BJTs), Complementary MOS (CMOS), N-type MOS (NMOS), P-channel MOS (PMOS), Laterally Diffused MOS (LDMOS), BiCMOS or other type of semiconductor based transistors. Furthermore, embodiments can be implemented using Gallium Arsenide (GaAs), Gallium Nitride (GaN) and/or Silicon-Germanium (SiGe) and silicon transistors with the desired transistor switching speed and ON-resistance.

(138) In embodiments, the number of transistors included within each PA is set according to a required maximum output power level of the power amplifier. In other embodiments, the number of transistors in the PA is such that the numbers of transistors in the pre-driver, driver, and PA stages conform to an optimized progression.

(139) While preferred embodiments of the present disclosure have been described above, the present disclosure is not limited to the specific configurations described above. Various variations and modifications may be made without departing from the scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

(140) 4. Summary

(141) Mathematical basis for a new concept related to processing signals to provide power amplification is provided herein. These new concepts allow arbitrary waveforms to be constructed from sums of waveforms which are substantially constant envelope in nature. Desired output signals and waveforms may be constructed from the amplified versions of substantially constant envelope constituent signals which can be created from the knowledge and quantization of the time varying envelope of the input signal and the use of a multiplicity of power amplifiers with a multiplicity of outputs powers. The amplified version of the quantized signal is generated by using multiple amplifiers with different power outputs which are summed using novel techniques not available commercially, not taught or found in literature or related art. Furthermore, the blend of various techniques and circuits provided in the disclosure provide unique aspects of the invention which permits superior linearity, power added efficiency, constant supply voltages on the power amplifiers and low cost. Embodiments of the invention can be implemented by a blend of hardware, software and firmware. Both digital and analog techniques can be used with or without microprocessors and DSP's (digital signal processors) or with or without FPGAs. The digital processing offers higher flexibility for the implementation of the multi V.sub.dd digital controlled system.

(142) Embodiments of the invention can be implemented for communications systems and electronics in general. In addition, and without limitation, mechanics, electro mechanics, electro optics, and fluid mechanics can make use of the same principles for efficiently amplifying and transducing signals.

(143) 5. Conclusions

(144) The present invention has been described above with the aid of functional building blocks illustrating the functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. Any such alternate boundaries are thus within the scope and spirit of the claimed invention. One person skilled in the art will recognize that these functional building blocks can be implemented by discrete components, application specific integrated circuits, processors executing appropriate software and the like and combinations thereof.

(145) While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments but should be defined only in accordance with the following claims and their equivalents.