DEVICES AND METHODS FOR PARALLELIZED RECURSIVE BLOCK DECODING

Abstract

A decoder for determining an estimate of a vector of information symbols carried by a signal received through a transmission channel represented by a channel matrix is provided. The decoder includes a block division unit configured to divide the vector of information symbols into two or more sub-vectors, each sub-vector being associated with a block level; two or more processors configured to determine, in parallel, candidate sub-vectors and to store the candidate sub-vectors in a first stack. Each processor is configured to determine at least a candidate sub-vector by applying a symbol estimation algorithm and to store each candidate sub-vector with a decoding metric and the block level associated with the candidate sub-vector. The decoding metric is lower than or equal to a decoding metric threshold. A processor among the two or more processors is configured to determine at least a candidate vector from candidate sub-vectors stored in the first stack, the candidate vector being associated with a cumulated decoding metric and to update the decoding metric threshold from the cumulated decoding metric.

Claims

1. A decoder for determining an estimate of a vector of information symbols carried by a signal, said signal being received through a transmission channel represented by a channel matrix, wherein the decoder comprises: a block division unit configured to divide said vector of information symbols into two or more sub-vectors of information symbols in accordance with a division of said channel matrix into sub-matrices, each sub-vector being associated with a block level representing a level of said sub-vector in said channel matrix; two or more processors configured to operate in parallel for determining candidate sub-vectors and storing said candidate sub-vectors in a first stack, each of said two or more processors being configured to determine at least a candidate sub-vector by applying a symbol estimation algorithm, a candidate sub-vector representing an estimate of a sub-vector of information symbols and to store said at least a candidate sub-vector of information symbols in said first stack with a decoding metric and the block level representing the level of said candidate sub-vector within said channel matrix, said decoding metric being lower than or equal to a decoding metric threshold, a processor among said two or more processors being configured to determine at least a candidate vector from candidate sub-vectors stored in said first stack, said candidate vector representing an estimate of said vector of information symbols and being associated with a cumulated decoding metric determined from the decoding metrics stored with said candidate sub-vectors and to update said decoding metric threshold from said cumulated decoding metric.

2. The decoder of claim 1, wherein the two or more processors comprise: a first processor configured to determine one or more candidate sub-vectors in association with each sub-vector of information symbols by recursively applying an estimation algorithm starting from the sub-vectors of information symbols associated with the highest block level until reaching the sub-vector of information symbols associated with the lowest block level, the first processor being configured to store each candidate sub-vector in said first stack; a second processor configured to determine one or more candidate sub-vectors by recursively selecting a sub-vector in the first stack associated with the lowest block level and determining a candidate sub-vector in association with each of the sub-vectors of information symbols that are associated with block levels lower than said lowest block level by applying a symbol estimation algorithm until reaching the lowest block level in the channel matrix, the second processor being further configured to determine a candidate vector from the selected candidate sub-vector and the candidate sub-vectors determined in association with the sub-vectors of information symbols that are associated with block levels lower than said lowest block level, said candidate vector representing an estimate of said vector of information symbols, the second processor being further configured to determine a cumulated metric associated with said candidate vector by adding the decoding metrics associated with said selected candidate sub-vector and the decoding metrics associated with the candidate sub-vectors determined in association with the sub-vectors of information symbols that are associated with block levels lower than said lowest block level, the second processor being configured to store said candidate vector in a second stack with said cumulated decoding metric, said decoding metric threshold being updated to said cumulated decoding metric.

3. The decoder of claim 2, wherein a processor among said two or more processors is configured to: order the first stack according to a given order of the decoding metrics associated with the candidate sub-vectors, update said decoding metric threshold to said cumulated decoding metric associated with said candidate vector, remove from said first stack the candidate sub-vectors that are associated with a decoding metric higher than the updated decoding metric threshold, and determine an estimate of a vector of information symbols from the candidate vector stored in the second stack that is associated with the lowest cumulated decoding metric.

4. The decoder of claim 1, wherein said symbol estimation algorithm is chosen in a group comprising a sequential lattice decoding algorithm, a Zero Forcing algorithm, a Minimum Mean Square Error algorithm, and a Zero Forcing Decision Feedback Equalizer.

5. The decoder of claim 4, wherein said symbol estimation algorithm comprises a preprocessing step using a lattice reduction algorithm and/or an MMSE-GDFE filtering.

6. The decoder of claim 1, wherein said symbol estimation algorithm is previously determined depending on a signal-to-noise ratio and/or on an outage capacity.

7. The decoder of claim 1, wherein said symbol estimation algorithm is previously determined depending on a target quality of service metric chosen in a group comprising a target achievable transmission rate.

8. The decoder of claim 1, wherein said block division unit is configured to divide said vector of information symbols according to a set of division parameters comprising a number of blocks at least equal to two and block lengths, said number of blocks representing the number of said sub-vectors of information symbols, a block length representing a number of information symbols comprised in a sub-vector of information symbols.

9. A method for determining an estimate of a vector of information symbols carried by a signal, said signal being received through a transmission channel represented by a channel matrix, wherein the method comprises: dividing said vector of information symbols into two or more sub-vectors of information symbols in accordance with a division of said channel matrix into sub-matrices, each sub-vector being associated with a block level representing a level of said sub-vector in said channel matrix; determining, by two or more processors operating in parallel, candidate sub-vectors and storing said candidate sub-vectors in a first stack, the step of determining candidate sub-vectors comprising: determining, by each of said two or more processors, at least a candidate sub-vector by applying a symbol estimation algorithm, a candidate sub-vector representing an estimate of a sub-vector of information symbols and, storing said at least a candidate sub-vector of information symbols in said first stack with a decoding metric and the block level representing the level of said candidate sub-vector within said channel matrix, said decoding metric being lower than or equal to a decoding metric threshold, the method further comprises determining at least a candidate vector from candidate sub-vectors stored in said first stack, said candidate vector representing an estimate of said vector of information symbols and being associated with a cumulated decoding metric determined from the decoding metrics stored with said candidate sub-vectors and updating said decoding metric threshold from said cumulated decoding metric.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, wherein:

[0044] FIG. 1 is a block diagram of an exemplary application of the invention in a communication system, according to some embodiments;

[0045] FIG. 2 is a block diagram of an exemplary application of the invention to wireless single-user MIMO systems, according to some embodiments;

[0046] FIG. 3 is a block diagram representing the structure of a Space-Time decoder, according to some embodiments in which parallelized recursive block decoding is used;

[0047] FIG. 4 is a flowchart depicting a method of parallelized recursive block decoding, according to some embodiments;

[0048] FIG. 5 illustrates a hardware architecture of a Space-Time decoder according to some embodiments.

DETAILED DESCRIPTION

[0049] Embodiments of the disclosure provide low-complexity and low-latency parallelized recursive block decoding devices and methods for decoding a signal carrying information symbols and received through a transmission channel with optimal diversity order and reduced decoding complexity and decoding delays. The transmission channel is represented by an upper triangular matrix obtained by applying a QR decomposition to a channel state matrix representative of the transmission channel.

[0050] Embodiments of the disclosure provide parallelized QR-based recursive decoding algorithms, the parallelization of the processing of the different blocks or sub-vectors of information symbols enables a drastic reduction of the decoding delays.

[0051] Devices and methods according to the various embodiments may be implemented in different types of systems. In particular, they may be implemented in communication systems to determine an estimate of a vector of information symbols conveyed from one or many transmitter devices to a receiver device.

[0052] The following description of some embodiments will be made with reference to communication systems, for illustration purposes only. However, the skilled person will readily understand that the various embodiments may be applied to other types of systems such as signal processing systems, cryptographic systems, and positioning systems.

[0053] FIG. 1 is a block diagram of an exemplary application to a communication system 100, according to some embodiments. The communication system 100 may be wired, wireless, or optical (e.g. optical fiber-based). The communication system 100 may comprise at least one transmitter device 11 (hereinafter referred to as a “transmitter”) configured to transmit a plurality of information symbols to at least one receiver device 15 (hereinafter referred to as “receiver”) through a transmission channel 13. The receiver 15 may include at a Space-Time decoder 10 to decode the information symbols sent by one or more transmitter devices 11. The transmission channel 13 may be any wired connection, wireless medium, or optical link.

[0054] In an application of the invention to radio communications, the communication system 100 may be a wireless single-user MIMO system comprising a wireless transmitter device 11 configured to communicate a flow of information symbols representing an input data and a wireless receiver device 15, configured to decode the conveyed symbols by the transmitter 11.

[0055] The transmitter device 11 may be equipped with one or more transmit antennas and the receiver device 15 may be equipped with one or more receive antennas, the number n.sub.t of transmit antennas the number n.sub.r of receive antennas being greater than or equal to one.

[0056] In another application of the invention to radio communications, the communication system 100 may be a wireless multi-user MIMO system in which a plurality of wireless transmitter devices 11 and receiver devices 15 communicate with each other. In such embodiments, the communication system 100 may further use, alone or in combination, any multiple access technique such as Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Code Division Multiple Access (CDMA), and Space-Division Multiple Access (SDMA).

[0057] In an application of the invention to optical communications, the communication system 100 may be an optical fiber-based communication system. The transmitter 11 and receiver 15 may be accordingly any optical transceiver capable of operating in optical fiber-based transmission systems. The transmission channel 13 may be any optical fiber link designed to carry data over short or long distances. Exemplary applications using optical fiber links over short distances comprise high-capacity networks such as data center interconnections. Exemplary applications using optical fiber links over long distances comprise terrestrial and transoceanic transmissions. In such embodiments, the information symbols conveyed by the transmitter 11 may be carried by optical signals polarized according to the different polarization states of the fiber. The optical signals propagate along the fiber-based transmission channel 11, according to one or more propagation modes, until reaching the receiver 15.

[0058] In another application of the invention to optical communications, the optical signal carrying the information symbols may be generated using a single wavelength lasers.

[0059] In other embodiments, wavelength division multiplexing (WDM) techniques may be used at the transmitter 11 to enable generating optical signals using a plurality of independent wavelengths.

[0060] In still another application of the invention to optical communication systems using multi-mode and/or multi-core fibers, space division multiplexing techniques may be used to multiplex the information symbols according to the various propagation modes.

[0061] Further, a multiple access technique such as WDMA (Wavelength Division Multiple Access) may be used in some applications of the invention to optical communication systems.

[0062] The transmission channel 13 may be any linear Additive White Gaussian Noise (AWGN) channel or a multipath channel using single-carrier or multi-carrier modulation formats such as OFDM (Orthogonal Frequency Division Multiplexing) and FBMC (Filter Bank Multi-Carrier) for mitigating frequency-selectivity, interference and delays.

[0063] In an application of the invention to wireless single-user MIMO systems, the tradeoff between complexity, performance, and decoding delays of QR-based sub-block decoding of a received signal may be optimized through an optimization of the sub-block division of the vector of information symbols taking into account the interference inter sub-vectors. Exemplary applications of the decoding methods and devices include, with no limitation, MIMO decoding in configurations that may be implemented in: [0064] power-line wired communications standardized in the ITU G.hn and HomePlug AV2 specifications; [0065] wireless standards such as the Wi-Fi (IEEE 802.11n and IEEE 802.11ac), the cellular WiMax (IEEE 802.16e), the cooperative WiMax (IEEE 802.16j), the Long Term Evolution (LTE), the LTE-advanced, and the 5G ongoing standardization.

[0066] For illustration purposes only, the following description will be made with reference to a wireless single-user MIMO system accommodating a transmitter device 11 equipped with n.sub.t≥1 transmit antennas and a receiver device 15 equipped with n.sub.r≥1 receive antennas for decoding information symbols sent by the transmitter 11. However, the skilled person will readily understand that embodiments of the invention apply to other communication systems such as wireless multi-user MIMO systems and optical MIMO systems. More generally, the invention may be applied to any communication system characterized by a linear representation (equivalently a lattice representation) of the channel output at receiver devices. In addition, although not limited to such embodiments, the invention has particular advantages in the presence of a number of transmit antennas greater than or equal to two n.sub.t≥2) and/or a number of receive antennas greater than or equal to two (n.sub.r≥2).

[0067] Referring to FIG. 2, there is shown an exemplary wireless single-user MIMO communication system 200 in which various embodiments of the present invention may be implemented. The wireless single-user MIMO communication system 200 may comprise a transmitter 20 implementing a Space-Time Block Code (STBC) to multiplex the information symbols over time and space dimensions (i.e. over the transmit antennas). Each transmitter 20 of a station may exchange data with a receiver 21 of another station according to the wireless communication system 200.

[0068] The wireless single-user MIMO communication system 200 may present a symmetric configuration. As used herein, a symmetric configuration refers to a configuration in which the transmitter 20 and the receiver 21 are equipped with the same number of antennas n.sub.t=n.sub.r. Alternatively, the MIMO configuration may be asymmetric, the number n.sub.r of receive antennas differing from the number n.sub.t of transmit antennas. In particular, in one embodiment, in order to avoid a rank deficiency problem, the number n.sub.r of receive antennas may be larger than the number n.sub.t of antennas at the transmitter. Exemplary asymmetric MIMO configurations comprise 2×4 (n.sub.t=2, n.sub.r=4) and 4×8 (n.sub.t=4, n.sub.r=8) supported for example in the LTE standard.

[0069] The transmitter 20 may convey a signal to a receiver 21 over a noisy wireless MIMO channel represented by a channel matrix H.sub.c. The transmitter 20 may be implemented in different devices or systems capable of operating in wireless environments. Exemplary devices adapted for such applications comprise mobile phones, drones, laptops, tablets, robots, IoT (Internet of Things) devices, base stations, etc. The transmitter 20 may be fixed or mobile. It may comprise for example: [0070] a channel encoder 201 implementing one or more Forward Error Correction (FEC) codes such as linear block codes, convolutional codes, polar codes, etc; [0071] a modulator 203 implementing a modulation scheme such as Quadrature Amplitude Modulation (QAM) delivering a modulated symbol vector s.sub.c; [0072] a Space-Time encoder 205 for delivering a codeword matrix X; [0073] n.sub.t transmit antennas 207, each transmit antenna being associated with a single-carrier or a multi-carrier modulator such as an OFDM or an FBMC modulator.

[0074] The transmitter 20 may be configured to encode a received flow of information bits as data input using a FEC encoder 201 implementing for example a linear block code, a convolutional code, or a polar code. The encoded binary signal may be then modulated into a symbol vector s.sub.c using the modulator 203. Different modulation schemes may be implemented such as 2.sup.q-QAM or 2.sub.q-PSK with 2.sup.q symbols or states. The modulated vector s.sub.c may be a complex-value vector comprising κ complex-value symbols s.sub.1, s.sub.2, . . . , s.sub.K with q bits per symbol.

[0075] An information symbol s.sub.j has a mean power E.sub.s, and can be written in the form:

s.sub.j=Re(s.sub.j)+ilm(s.sub.j)  (1)

[0076] In equation (1), i denotes the complex number such that i.sup.2=−1 and the Re(.) and Im(.) operators output respectively the real and imaginary parts of an input value.

[0077] When modulation formats such as 2.sup.q-QAM are used, the 2.sup.q symbols or states represent a sub-set of the integer field [i]. The corresponding constellation is composed of 2.sup.q points representing the different states or symbols. In addition, in the case of squared modulations, the real and imaginary parts of the information symbols belong to the same finite alphabet A=[−(q−1), (q−1)]. The minimum distance d.sub.min of a modulation scheme represents the Euclidean distance between two adjacent points in the constellation and is equal to 2 in such example.

[0078] A Space-Time Encoder 205 may be used to generate a codeword matrix X from the encoded symbols. The Space-Time Encoder 205 may use a linear STBC of length T and may deliver a codeword matrix X of dimension n.sub.t×T that belongs to a codebook C and is sent over T time slots. The coding rate of such codes is equal to κ/T complex symbols per channel use, where κ is the number of encoded complex-value symbols composing the vector s.sub.c=[s.sub.1, s.sub.2, . . . , s.sub.K].sup.t of dimension κ in this case. When full-rate codes are used, the Space-Time Encoder 205 encodes κ=n.sub.tT complex-value symbols. Examples of STBCs are the Perfect Codes. The Perfect Codes provide full coding rates by encoding a number κ=n.sub.t.sup.2 (T=n.sub.t) of complex information symbols and satisfy a non-vanishing determinant property.

[0079] In some embodiments, the Space-Time Encoder 205 may use a spatial multiplexing scheme known as V-BLAST scheme by multiplexing the received complex-value information symbols over the different transmit antennas, without performing a coding in the time dimension.

[0080] The codeword thus constructed may be converted from the time domain to the frequency domain using a multicarrier modulation technique, using for example OFDM or FBMC modulators, and spread over the transmit antennas 207. Signals may be sent from the transmit antennas 207 after optional filtering, frequency transposition and amplification.

[0081] The receiver 21 may be configured to receive and decode a signal communicated by the transmitter 20 in a wireless network through a transmission channel (also referred to as a “communication channel”) subject to fading and interference and represented by a complex-value channel matrixesH.sub.c. In addition, the communication channel may be noisy, affected for example by a Gaussian Noise.

[0082] The receiver 21 may be integrated in a base station such as a Node-B in a cellular network, an access point in a local area network or ad-hoc networks or any other interfacing device operating in a wireless environment. The receiver 21 may be fixed or mobile. In one exemplary embodiment, the receiver 21 may comprise: [0083] a Space-Time decoder 211 configured to deliver, from the channel matrix H.sub.c and the channel output signal Y.sub.c, an estimation ŝ.sub.c of the modulated symbol vector s.sub.c; [0084] a demodulator 213 configured to generate a binary sequence by performing a demodulation of the estimated symbol vector ŝ.sub.c; [0085] a channel decoder 215 configured to deliver, as an output, a binary signal which is an estimation of the transmitted bits, using for example the Viterbi algorithm.

[0086] The receiver 21 implements a reverse processing of the processing performed by the transmitter 20. Accordingly, if a single-carrier modulation is used at the transmitter rather than a multi-carrier modulation, then the n.sub.r OFDM of FBMC demodulators may be replaced by corresponding single-carrier demodulators.

[0087] FIG. 3 represents a block structure of a Space-Time decoder 300 (also referred to as ‘a decoder’) according to some embodiments in application to a wireless Rayleigh fading multiple antenna system, the decoder 300 being configured to receive and decode a signal sent from a transmitter equipped with n.sub.t transmit antennas, the decoder 300 being implemented in a receiver device equipped with n.sub.r receive antennas.

[0088] According to some embodiments in which Space-Time encoding has been performed at the transmitter using a Space-Time code of length T encoding κ symbols, the received complex-value signal may be written in the form:

Y.sub.c=H.sub.cX.sub.c+W.sub.c  (2)

[0089] In equation (2), Y.sub.c is a n.sub.r×T matrix representing the received signal, X.sub.c denotes the complex-value codeword matrix of dimensions n.sub.r×T.

[0090] According to some embodiments in which V-BLAST spatial multiplexing is used, the received complex-value signal may be written in the form:

y.sub.c=H.sub.cs.sub.c+w.sub.c  (3)

[0091] In equation (3), y.sub.c is a n.sub.r-dimensional vector, s.sub.c denotes the complex-value vector of transmitted information symbols of dimension n.sub.t.

[0092] The complex-value n.sub.r×n.sub.t matrix H.sub.c in equations (2) and (3) represents the channel matrix comprising the fading gains. In a Rayleigh fading channel, the entries of the channel matrix H.sub.c are of independent identically distributed (i.i.d) complex Gaussian-type. The channel matrix may be estimated in coherent transmissions at the receiver using estimation techniques such as least square estimators. In addition to the multipath fading effects, the transmission channel may be noisy. The noise may result from the thermal noise of the system components, inter-user interference and intercepted interfering radiation by antennas. The total noise may be modeled by a zero-mean Additive White Gaussian Noise of variance σ.sup.2 per real-value dimension modeled in equations (2) and (3) respectively by the n.sub.r×T complex-value matrix W.sub.c and the n.sub.r-dimensional complex-value vector w.sub.c.

[0093] The decoder may comprise a complex-to-real converter 301 configured to convert the complex-value channel matrix H.sub.c into a real-value equivalent channel matrix H, and convert the complex-value received signal into a real-value signal.

[0094] In one embodiment using a V-BLAST spatial multiplexing, the complex-to-real converter 301 may be configured to transform the system in equation (3) into:

[00001]$\begin{array}{cc}y=\left[\begin{array}{c}\mathrm{Re}\left(y_c\right)\\ \mathrm{Im}\left(y_c\right)\end{array}\right]=\left[\begin{array}{cc}\mathrm{Re}\left(H_c\right)& -\mathrm{Im}\left(H_c\right)\\ \mathrm{Im}\left(H_c\right)& \mathrm{Re}\left(H_c\right)\end{array}\right]\left[\begin{array}{c}\mathrm{Re}\left(s_c\right)\\ \mathrm{Im}\left(s_c\right)\end{array}\right]+\left[\begin{array}{c}\mathrm{Re}\left(w_c\right)\\ \mathrm{Im}\left(w_c\right)\end{array}\right]& \left(4\right)\end{array}$

[0095] The Re(.) and Im(.) operators in equation (4) designate the real and imaginary parts of each element composing the underlying vector or matrix. The complex-to-real conversion may be performed considering an arbitrary order of the elements of the vectors and is not limited to the exemplary conversion expressed in equation (4).

[0096] In another embodiments using linear Space-Time block coding at the transmitter, the complex-to-real converter 301 may be configured to transform the system in equation (2) into a real-value system that can be written in the linear representation form of equation (4) where the equivalent channel matrix is the real-value 2n.sub.rT×2κ matrix H.sub.eq given by:

H.sub.eq=(I.sub.T.Math.H)G  (5)

[0097] The 2n.sub.tT×2κ matrix G designates a real-value matrix known as a generator matrix or coding matrix of the linear Space-Time Block code used at the transmitter. I.sub.T denotes the identity matrix of dimension T and the operator .Math. is the Kronecker matrices product.

[0098] To facilitate the understanding of the following embodiments, the following description will be made with reference to a spatial multiplexing scheme and involving a symmetric MIMO configuration where the transmitter and receiver are equipped with the same number of antennas n.sub.t=n.sub.r, for illustration purposes only. Accordingly, the real-value system in equation (3) can be written in the linear form as:

y=Hs+w  (6)

[0099] In equation (6), the vectors y, s and w are n-dimensional vectors with n=2n.sub.t=2n.sub.r and the equivalent real-value channel matrix H is a square n×n matrix. The vector s comprises the real and imaginary parts of the original complex-value information symbols comprised in the vector s.sub.c.

[0100] The decoder 300 may comprise a QR decomposition unit 302 configured to generate an orthogonal matrix Q and an upper triangular matrix R by applying a QR decomposition to the real-value channel matrix such that H=QR. The components of the upper triangular matrix are denoted by R.sub.ij with i,j=1, . . . , n.

[0101] The decoder 300 may further comprise a multiplication unit 309 configured to determine an auxiliary signal {tilde over (y)} by scaling the real-value signal y by the transpose of the orthogonal matrix Q obtained from the QR decomposition of the real-value channel matrix such that:

{tilde over (y)}=Q.sup.ty=R.Math.s+{tilde over (w)}  (7)

[0102] In equation (7), {tilde over (w)}=Q.sup.tw designates a scaled noise vector. Given the orthogonality of the matrix Q, the system in equation (7) is equivalent to the one given in equation (6).

[0103] The parallelized QR-based recursive block decoding according to the various embodiments is based on the real-value system of equation (7).

[0104] ML decoding of the information symbols can be formalized by the optimization problem given by:

ŝ.sub.ML=argmin.sub.sϵA.sub.n∥{tilde over (y)}−Rs∥.sup.2   (8)

[0105] In equation (8), A designates the alphabet to which the real and imaginary parts of the complex-value vector s.sub.c composing the real vector s belong. An ML metric maybe defined in relation with the ML decoding problem as:

m(s)=∥{tilde over (y)}−Rs∥.sup.2  (9)

[0106] Recursive block decoding according to the embodiments of the disclosure is based on a division of the vector of information symbols into two or more sub-vectors in accordance with a division of the upper triangular matrix into a plurality of sub-matrices.

[0107] Accordingly, the decoder 300 may further comprise a block division unit 303 configured to perform vectors and matrix division according to a set of division parameters comprising a number of blocks at least equal to two denoted by N≥2 and block lengths denoted by l.sub.k with k=1, . . . , N such that the length l.sub.k≥1 corresponds to the length in terms of the number of elements/entries of the k.sup.th sub-vector of information symbols, the length being higher than or equal to one, i.e. each sub-vector of information symbols comprises one or more symbols. The lengths of the blocks satisfy the equality given by Σ.sub.k=1.sup.Nl.sub.k=n.

[0108] Using the set of division parameters, the block division unit 303 may be configured to divide the vector {tilde over (y)} into N sub-vectors such that

[00002]$\tilde{y}=\left[\begin{array}{c}{\tilde{y}}^{\left(1\right)}\\ \mathrm{.Math.}\\ {\tilde{y}}^{\left(N\right)}\end{array}\right],$

sub-vector {tilde over (y)}.sup.(k) of index k, for k=1, . . . , N has a lengths l.sub.k. Similarly, the block division unit 303 may be configured to divide the real-value vector of information symbols s and to the noise vector {tilde over (w)} respectively into N sub-vectors s.sup.(k) and N sub-vectors {tilde over (w)}.sup.(k) of lengths l.sub.k such that

[00003]$s=\left[\begin{array}{c}{s}^{\left(1\right)}\\ \mathrm{.Math.}\\ s^{\left(N\right)}\end{array}\right]\mathrm{and}\tilde{w}=\left[\begin{array}{c}{\tilde{w}}^{\left(1\right)}\\ \mathrm{.Math.}\\ {\tilde{w}}^{\left(N\right)}\end{array}\right].$

The division of the vectors {tilde over (y)}, s and {tilde over (w)} may be performed in accordance with a division of the upper triangular matrix R into sub-matrices according to

[00004]$\begin{array}{cc}R=\left[\begin{array}{cccc}{R}_{11}& \mathrm{.Math.}& R_{1,n-1}& R_{1n}\\ 0& \mathrm{.Math.}& \mathrm{.Math.}& \mathrm{.Math.}\\ 0& 0& R_{n-1,n-1}& R_{n­1,n}\\ 0& 0& 0& R_{nn}\end{array}\right]=\left[\begin{array}{cccc}{R}^{\left(1\right)}& \mathrm{.Math.}& B^{(1N­1)}& B^{(1N)}\\ 0& \mathrm{.Math.}& \mathrm{.Math.}& \mathrm{.Math.}\\ 0& 0& R^{(N­1)}& B^{(N­1N)}\\ 0& 0& 0& R^{\left(N\right)}\end{array}\right]& \left(10\right)\end{array}$

[0109] In equation (10): [0110] a square upper triangular sub-matrix R.sup.(k) is of dimension l.sub.k×l.sub.k; and [0111] a sub-matrix B.sup.(kj) is a rectangular matrix of dimensions l.sub.k×l.sub.j for j=k+1, . . . , N and represents the interference between the sub-vectors s.sup.(k) and s.sup.(j).

[0112] According to some embodiments, the block division unit 303 may be configured to previously determine the set of division parameters depending on the zero structure of the upper triangular matrix R such that the set of division parameters provides a division of the upper triangular matrix into sub-matrices that exploit the zero structure of the rectangular sub-matrices to reduce the error propagation due to the interference between the sub-vectors. Indeed, as the sub-matrix B.sup.(kj) represents the interference between the sub-vectors s.sup.(k) and s.sup.(j), the decoding of the sub-vector s.sup.(k) depends on the determined estimates on the sub-vectors s.sup.(j) for j=k+1, . . . , N. Any error on the estimation of the sub-vector s.sup.(j) may induce an error on the estimation of the sub-vector s.sup.(k). The error propagation due to the interference between the sub-vectors s.sup.(k) and s.sup.(j) for j=k+1, . . . , N depends on the zero structure of the rectangular sub-matrix B.sup.(kj). The lower the number of zeros in the rectangular sub-matrices, the lower the error propagation, and the better the decoding error performances.

[0113] Accordingly, the block division unit 303 may be configured to previously determine the set of division parameters enabling, for a given upper channel matrix, a minimization of the impact of the interference between the sub-vectors of information symbols. The set of division parameters may be determined based on the optimization (minimization or maximization) of a division metric representing the zero structure of the rectangular sub-matrices.

[0114] Given the set of division parameters, the divided sub-matrices R.sup.(k) and B.sup.(kj) of the upper triangular matrix R and the divided sub-vectors {tilde over (y)}.sup.(k) may be grouped into N blocks (SB).sub.k with k=1, . . . , N.

[0115] A block (SB).sub.k, for k=1, . . . , N−1, may be defined by a set of parameters such that (SB).sub.k={l.sub.k,s.sup.(k),R.sup.(k),{tilde over (y)}.sup.(k),{tilde over (y)}.sup.(k),{tilde over (w)}.sup.(k),D.sup.(k),B.sup.(kj), j=k+1, . . . ,N}, where:

{tilde over (y)}.sup.(k)=R.sup.(k)s.sup.(k)+Σ.sub.j=k+1.sup.NB.sup.(kj)s.sup.(j)+{tilde over (w)}.sup.(k)  (11)

{tilde over (y)}.sup.(k)={tilde over (y)}.sup.(k)−Σ.sub.j=k+1.sup.NB.sup.(kj)ŝ.sup.(j)  (12)

[0116] For k=N, the block of index N may be defined by (SB).sub.N={l.sub.N,s.sup.(N),R.sup.(N),{tilde over (y)}.sup.(N),{tilde over (w)}.sup.(N), D.sup.(N)} such that:

{tilde over (y)}.sup.(N)=R.sup.(N)s.sup.(N)+{tilde over (w)}.sup.(N)  (13)

[0117] D.sup.(k) designates a symbol estimation algorithm applied in the k.sup.th block to determine a candidate estimate of the sub-vector of information symbols s.sup.(k).

[0118] According to such groups, the ML decoding metric in equation (9) may be written as:

m(s)=∥{tilde over (y)}−Rs∥.sup.2=∥Σ.sub.k=1.sup.N{tilde over (y)}.sup.(k)−(R.sup.(k)s.sup.(k)+Σ.sub.j=k+1.sup.NB.sup.(kj)s.sup.(j))∥.sup.2   (14)

[0119] Accordingly, the ML optimization system of equation (8) can be expressed as:

[00005]$\begin{array}{cc}\hat{s}=\arg \min {.Math.{.Math.}_{k=1}^N{\tilde{y}}^{\left(k\right)}-\left(R^{\left(k\right)}{s}^{\left(k\right)}+{.Math.}_{j=k+1}^N{B}^{\left(kj\right)}{s}^{\left(j\right)}\right).Math.}^2& \left(15\right)\end{array}$

[0120] In equation (15), .sup.l.sup.k designates the alphabet to which belongs to sub-vector of information symbols s.sup.(k).

[0121] Parallelized recursive block decoding according to the embodiments of the disclosure is based on a parallelized determination of sets of candidate sub-vectors denoted by Γ.sub.1, . . . , Γ.sub.N, such that the set Γ.sub.k comprises one or more candidate sub-vectors ŝ.sub.1.sup.(k), . . . , ŝ.sub.Card(Γ.sub.k.sub.) of the k.sup.th sub-vector of information symbol s.sup.(k), with Card(Γ.sub.k) designating the cardinality of the set Γ.sub.k strictly inferior to the cardinality of the alphabet A to which belong the real and imaginary parts of the complex-value vector of information symbols. Accordingly, the sets of candidate sub-vectors may be determined in parallel using two or more processors (also referred to ‘processing units’) enabling a faster decoding and a lower decoding complexity. The two or more processors may be configured to operate in parallel for determining candidate sub-vectors and storing the candidate sub-vectors in a first stack 310, each processor being configured to determine at least a candidate sub-vector by applying a symbol estimation algorithm, a candidate sub-vector representing an estimate of a sub-vector of information symbols. Each processor may be further configured to store each determined candidate sub-vector in the first stack 310 with a decoding metric associated with the candidate sub-vector and the block level representing the level of the candidate sub-vector with the upper triangular channel matrix. A processor among the two or more processors may be configured to determine at least a candidate vector from candidate sub-vectors stored in the first stack 310, the candidate vector representing an estimate of the vector of information symbols and being associated with a cumulated decoding metric determined from the decoding metrics stored with the candidate sub-vectors and to update the decoding metric threshold from the cumulated decoding metric.

[0122] According to some embodiments, the decoder 300 may comprise, among the two or more processors, a first processor 304 and a second processor 305 configured to operate in parallel for filling a first stack 310 with candidate sub-vectors ŝ.sub.1.sup.(k), . . . , ŝ.sub.Card(Γ.sub.k.sub.).sup.(k) for k taking value between 1 and N, a candidate sub-vector ŝ.sub.t.sub.k.sup.(k) for t.sub.k=1, . . . , Card(Γ.sub.k) representing an estimate of the sub-vector of information symbols s.sup.(k).

[0123] A candidate sub-vector ŝ.sub.t.sub.k.sup.(k) stored in the first stack 310 may be associated with a decoding metric defined by:

m(ŝ.sub.t.sub.k.sup.(k))=∥{tilde over (y)}.sup.(k)−(R.sup.(k)s.sub.t.sub.k.sup.(k)+Σ.sub.j=k+1.sup.NB.sup.(kj)ŝ.sub.t.sub.j.sup.(j))∥.sup.2  (16)

[0124] In equation (16), the term B.sup.(kj)ŝ.sub.t.sub.j.sup.(j) corresponds to inter-symbol interference, the candidate sub-vector ŝ.sub.t.sub.j.sup.(j) for j=k+1, . . . , N being known from the previously determined candidate sub-vectors in the sets Γ.sub.j for j=k+1, . . . , N.

[0125] A candidate sub-vector ŝ.sub.t.sub.k.sup.(k) may be determined by applying the symbol estimation algorithm D.sup.(k) associated with the k.sup.th block according to the satisfaction of a decoding metric condition according to which the decoding metric m(ŝ.sub.t.sub.k.sup.(k)) associated with a candidate sub-vector is required to be lower than or equal to a decoding metric threshold denoted by m.sub.th such that m(ŝ.sub.t.sub.k.sup.(k))≤m.sub.th.

[0126] The candidate sub-vector ŝ.sub.t.sub.k.sup.(k) stored in the first stack 310 may be further associated with a block level representing the level of the sub-vector within the upper triangular channel matrix. Using the block division notation, the block level associated with the candidate sub-vector ŝ.sub.t.sub.k.sup.(k) is the index k.

[0127] The parallelized recursive block decoding according to the embodiments of the disclosure provides a parallelized processing of the different blocks such that the candidate sub-vectors corresponding to the different sub-vectors of information symbols are determined in parallel enabling a faster delivery of a complete vector candidate ŝ on the vector of information symbols. Moreover, the parallelized processing of the different blocks enables updating the decoding metric threshold to be respected during the estimation of the candidate sub-vectors, the decoding metric threshold being updated each time a global solution or estimate ŝ on the vector of information symbols s is determined once a candidate sub-vector is determined for each of the sub-vectors.

[0128] The parallelized recursive block decoding starts with the processing of the last block (SB).sub.N of block level equal to N for the determination of at least one candidate sub-vector ŝ.sub.1.sup.(N) estimate of the N.sup.th sub-vector of information symbols s.sup.(N) by applying a symbol estimation algorithm D.sup.(N) according to the satisfaction of the decoding condition on the decoding metric. Once a first candidate sub-vector ŝ.sub.1.sup.(N) is determined, the processing of the remaining blocks (SB).sub.k for k=N−1, . . . , 1 may be started. Multiple processors may be implemented to simultaneously process the different blocks (SB).sub.k for determining candidate sub-vectors ŝ.sub.t.sub.k.sup.(k) in the sets Γ.sub.k for k=N−1, . . . , 1.

[0129] Accordingly, the first processor 304 may be configured to determine one or more candidate sub-vectors in association with each sub-vector of information symbols by recursively applying an estimation algorithm starting from the sub-vectors of information symbols associated with the highest block level until reaching the sub-vector of information symbols associated with the lowest block level. This means that the first processor 304 may be configured to start with processing the N.sup.th block (SB).sub.N, the processing consisting in applying the symbol estimation algorithm D.sup.(N) to determine one or more sub-vector estimates ŝ.sub.t.sub.N.sup.(N) in the set Γ.sub.N with t.sub.N designating the index of the sub-vector estimate ŝ.sub.t.sub.N.sup.(N) taking value between 1 and Card (Γ.sub.N). Each time the first processor 304 determines a sub-vector estimate ŝ.sub.N.sub.k.sup.(N), the first processor 304 stores the found sub-vector estimate ŝ.sub.t.sub.N.sup.(N) in the first stack 310 together with the corresponding block level equal to N for the first processed block, and the decoding metric m(ŝ.sub.t.sub.N.sup.(N)). After finding a first sub-vector estimate ŝ.sub.1.sup.(N), the first processor 304 continues the estimation process for determining all candidate sub-vectors corresponding to the set Γ.sub.N. Once the first processor 304 terminates processing the N.sup.th block (SB).sub.N, it moves up with respect to the levels of the sub-vectors of information symbols in order to process the (N−1).sup.th block (SB).sub.N-1. The processing of the (N−1).sup.th block (SB).sub.N-l consists in determining, for each candidate sub-vector ŝ.sub.N.sup.(N) determined in the set Γ.sub.N, a candidate sub-vector ŝ.sub.N-1.sup.(N-1)(ŝ.sub.t.sub.N.sup.(N)) in the set. The first processor 304 may be configured to determine each candidate sub-vector ŝ.sub.N-1.sup.(N-1)(ŝ.sub.t.sub.N.sup.(N)) by: [0130] performing interference cancellation and determining the sub-vector {tilde over (y)}.sup.(k)=R.sup.(k)s.sup.(k)+Σ.sub.j=k+1.sup.NB.sup.(kj)ŝ.sub.t.sub.j.sup.(j)+{tilde over (w)}.sup.(k); [0131] applying a symbol estimation algorithm D.sup.(N-1) to determine a candidate sub-vector ŝ.sub.t.sub.N-1.sup.(N-1)(ŝ.sub.t.sub.N.sup.(N)) satisfying the metric condition m(ŝ.sub.t.sub.N-1.sup.(N-1)(ŝ.sub.t.sub.N.sup.(N))≤m.sub.th.

[0132] According to some embodiments, the decoding metric threshold m.sub.th may be initially set (for example by the first processor 304) to the Euclidean distance between the received signal and the ZF-DFE estimate determined by applying a Zero Forcing Decision Feedback Equalizer to the received signal.

[0133] Once the first processor ends with the processing of the (N−1).sup.th block (SB).sub.N-1 it moves up for processing the (N−2).sup.th block (SB).sub.N-2 and so on until reaching the first block (SB).sub.1. For a candidate sub-vector associated with a block level different from the highest block level equal to N, the first processor 304 may be configured to store the candidate sub-vector together with the candidate sub-vectors of the previously processed blocks that were used in the interference cancellation step to find said candidate sub-vector.

[0134] In parallel to the processing performed by the first processor 304, the second processor 305 may be configured to determine one or more candidate sub-vectors by recursively selecting a sub-vector in the stack associated with the lowest block level and determining a candidate sub-vector in association with each of the sub-vectors of information symbols that are associated with block levels lower than said lowest block level by applying an estimation algorithm until reaching the lowest block level in the channel matrix.

[0135] This means that once the first processor 304 determines a first candidate sub-vector {umlaut over (s)}.sub.1.sup.(N) and stores it in the first stack 310, the second processor 305 is activated. At this time, the first stack 310 comprises only the candidate sub-vector ŝ.sub.1.sup.(N), thus the lowest block level in this case corresponds to the block level N associated with the candidate sub-vector ŝ.sub.1.sup.(N). The second processor 305 selects the candidate sub-vector ŝ.sub.1.sup.(N) and moves up by processing each of the blocks (SB).sub.k of block levels k=N−1, . . . , 1 lower than the block level N associated with the selected candidate sub-vector ŝ.sub.1.sup.(N). The second processor 305 may be configured to recursively determine a candidate sub-vector ŝ.sub.1.sup.(k) when processing the k.sup.th block (SB).sub.k by: [0136] performing interference cancellation for determining the sub-vector {tilde over (y)}.sup.(k)=R.sup.(k)s.sup.(k)+Σ.sub.j=k+1.sup.NB.sup.(k)ŝ.sub.1.sup.(j)+{tilde over (w)}.sup.(k); [0137] applying a symbol estimation algorithm D.sup.(k) for determining a candidate sub-vector ŝ.sub.1.sup.(k)(ŝ.sub.1.sup.(j), j=k'1, . . . , N) satisfying the metric condition m(ŝ.sub.1.sup.(k)(ŝ.sub.1.sup.(j), j=k'1, . . . , N))≤m.sub.th.

[0138] By processing the first block of block level k=1, the second processor 305 determines a candidate vector ŝ=(ŝ.sub.1.sup.(1), ŝ.sub.1.sup.(2), . . . , ŝ.sub.1.sup.(N)) from the selected candidate sub-vector ŝ.sub.1.sup.(N) and the candidate sub-vectors ŝ.sub.1.sup.(k) determined in association with the sub-vectors of information symbols s.sup.(k) that are associated with block levels k=N−1, . . . , 1 lower than the block level N associated with the selected candidate sub-vector ŝ.sub.1.sup.(N). The candidate vector ŝ represents an estimate of the vector of information symbols s. The second processor 305 may be configured to determine a cumulated metric m(ŝ) associated with the candidate vector by adding the decoding metric m(ŝ.sub.1.sup.(N)) associated with the selected candidate sub-vector ŝ.sub.1.sup.(N) and the decoding metrics m(ŝ.sub.1.sup.(k)) for k=1, . . . , N−1 associated with the candidate sub-vectors ŝ.sub.1.sup.(N-1), ŝ.sub.1.sup.(N-2), . . . , ŝ.sub.1.sup.(1) determined in association with the sub-vectors of information symbols that are associated with block levels k=1, . . . , N−1 lower than the lowest block level equal to N associated with the selected candidate sub-vector ŝ.sub.1.sup.(N) such that:

m(ŝ)=Σ.sub.k-1.sup.Nm(ŝ.sub.1.sup.(k))  (17)

[0139] The second processor 305 may be further configured to store the determined candidate vector ŝ in a second stack 307 together with the cumulated decoding metric m(ŝ).

[0140] Advantageously, the parallelized recursive block decoding further enables an online update of the decoding metric threshold from the cumulated decoding metrics associated with the determined candidate vectors. Accordingly, a processor among the two or more processors comprised in the decoder 300 may be configured to order the first stack 310 according to a given order (increasing or decreasing) of the decoding metrics associated with the stored candidate sub-vectors and to update the decoding metric threshold m.sub.th to the cumulated decoding metric m(ŝ) associated with the candidate vector ŝ such that m.sub.th=m(ŝ). This processor may be further configured to remove from the first stack 310 the candidate sub-vectors that are associated with a decoding metric that is higher than the updated decoding metric threshold.

[0141] The online update of the decoding metric threshold may be performed by the second processor 305 or by a third processor 306 comprised in the decoder 300, the third processor 306 being activated each time a candidate vector ŝ is found. In an application to hard-output decoding, the third processor 306 may be configured to determine/deliver an estimate of the vector of information symbols from the candidate vector stored in the stack that is associated with the lowest cumulated decoding metric.

[0142] In an application to soft-output decoding, the third processor 306 may be configured to use the candidate vectors stored in the second stack 307 to calculate the log likelihood ratio values for approximating the extrinsic information of the different information bits carried by the original information symbols.

[0143] The decoder 300 may further comprise a real-to-complex converter 308 configured to deliver a complex-value vector ŝ.sub.c as an estimate of the original vector of complex-value symbols s.sub.c. Then, the obtained candidate vector ŝ may be converted into the complex-value vector ŝ.sub.c=[ŝ.sub.1, ŝ.sub.2 . . . , ŝ.sub.n/2].sup.t such that a component ŝ.sub.j for j=1, . . . , n/2 is given by:

ŝ.sub.j=(ŝ).sub.j+i(ŝ).sub.j+n/2  (18)

[0144] In equation (18), (u).sub.j denotes the j.sup.th element of a vector u.

[0145] According to some embodiments, a symbol estimation algorithms D.sup.(k) may be selected from one or more symbol estimation algorithms previously determined or loaded from storage means.

[0146] According to some embodiments, the symbol estimation algorithm(s) D.sup.(k) for k=1, . . . ,N may be previously determined, depending on a signal-to-noise ratio and/or on the computational capabilities of devices or systems implementing the parallelized recursive block decoding and/or on the outage capacity of the transmission channel. Further, the symbol estimation algorithm(s) D.sup.(k) for k=1, . . . , N may be previously determined depending on a target quality of service metric that is required such as a target achievable transmission rate.

[0147] According to one embodiment, the symbol estimation algorithms D.sup.(k) may be similar.

[0148] According to another embodiment, the symbol estimation algorithms D.sup.(k) may be different.

[0149] In some embodiments, a symbol estimation algorithm D.sup.(k) for k=1, . . . , N may be chosen in the group comprising a sequential decoding algorithm, a linear decoding algorithm such as the ZF or the MMSE decoders, or a non-linear ZF-DFE decoder.

[0150] In an embodiment in which a sequential decoding algorithm is used in a given sub-block (SB).sub.k, the corresponding symbol estimation algorithm D.sup.(k) may deliver an estimate ŝ.sup.(k) by minimizing the block metric m(s.sup.(k))=∥{tilde over (y)}.sup.(k)−R.sup.(k)s.sup.(k)∥.sup.2≤m.sub.th according to:

[00006]$\begin{array}{cc}{\hat{s}}^{\left(k\right)}={\arg \min }_{s^{\left(k\right)}\in A^{l_k}}m\left(s^{\left(k\right)}\right)=\underset{s^{\left(k\right)}\in A^{l_k}}{\mathrm{argmin}}{.Math.{\stackrel{\_}{y}}^{\left(k\right)}-R^{\left(k\right)}{s}^{\left(k\right)}.Math.}^2& \left(19\right)\end{array}$

[0151] Sequential decoding algorithms such as the Sphere Decoder (SD), the Stack decoder and the SB-Stack decoder (SB-Stack), may be used to solve equation (19).

[0152] Further, in some embodiments a preprocessing on the upper triangular sub-matrices R.sup.(k) may be performed prior to the estimation of the candidate sub-vector using for example a lattice reduction and/or an MMSE-GDFE filtering.

[0153] Referring to FIG. 4, there is also provided a method for determining an estimate of a vector of information symbols carried by a signal, the signal being received through a transmission channel represented by a channel matrix. The received signal may be written in a real-value system according to equation (6) and equivalently represented using the QR decomposition as expressed in equation (7).

[0154] At step 401, a division of the vector of information symbols {tilde over (y)} into two or more sub-vectors of information symbols may be performed in accordance with a division of the channel matrix R into sub-matrices. The vector {tilde over (y)} may be accordingly divided into N≥2 sub-vectors such that

[00007]$\tilde{y}=\left[\begin{array}{c}{\tilde{y}}^{\left(1\right)}\\ \mathrm{.Math.}\\ {\tilde{y}}^{\left(N\right)}\end{array}\right],$

the sub-vector {tilde over (y)}.sup.(k) of index k, for k=1, . . . , N has a lengths l.sub.k≥1. The upper triangular matrix R may be divided into two or more sub-matrices according to equation (10).

[0155] At step 403, sets of candidate sub-vectors denoted by Γ.sub.1, . . . , Γ.sub.N may be determined by applying symbol estimation algorithms such that the set Γ.sub.k comprises one or more candidate sub-vectors ŝ.sub.1.sup.(k), . . . , ŝ.sub.Card(Γ.sub.k.sub.).sup.(k) of the k.sup.th sub-vector of information symbol s.sup.(k), with Card(Γ.sub.k) designating the cardinality of the set Γ.sub.k strictly inferior to the cardinality of the alphabet A to which belong the real and imaginary parts of the complex-value vector of information symbols. The sets of candidate sub-vectors may be determined by two or more processors operating in parallel. The step 403 of determining candidate sub-vectors may comprise a sub-step for determining, by each of the two or more processors, at least a candidate sub-vector by applying a symbol estimation algorithm, a candidate sub-vector representing an estimate of a sub-vector of information symbols.

[0156] At step 405, at least a candidate sub-vector of information symbols may be stored in a first stack with a decoding metric and the block level representing the level of the candidate sub-vector within the channel matrix R, the decoding metric being lower than or equal to a decoding metric threshold.

[0157] At step 407, at least a candidate vector may be determined from the candidate sub-vectors stored in the first stack, the candidate vector representing an estimate of the vector of information symbols and being associated with a cumulated decoding metric determined from the decoding metrics stored with the candidate sub-vectors and updating the decoding metric threshold from the cumulated decoding metric.

[0158] The methods and devices described herein may be implemented by various means, for example in hardware, software, or a combination thereof. In a hardware implementation, the processing elements of the decoder 300 can be implemented for example according to a hardware-only configuration (for example, in one or more FPGA, ASIC or VLSI integrated circuits with the corresponding memory) or according to a configuration using both VLSI and DSP.

[0159] FIG. 5 represents an exemplary hardware architecture of the decoder 300, according to some embodiments of the invention. The hardware architecture may be implemented in a machine or computer executed device. As illustrated, the decoder 300 may include various computing, storage and communication units possibly interacting with each another through a data and address port 59 and comprising: [0160] Input peripherals 51 for receiving for example input data from the receive antennas; [0161] Processing peripherals 53 comprising one or more microprocessors (CPU) such as an FPGA or an ASIC configured for instance to execute the corresponding instructions to run the methods and algorithms according to the embodiments of the invention; [0162] Storage peripherals 55 possibly comprising a random access memory (RAM) or a read-only memory to store for example the first stack and the second stack comprising the candidate sub-vectors of information symbols and the candidate vectors of information symbols, and [0163] Output peripherals 57 comprising communication means such as displays enabling for example man-to-machine interaction between the receiver device 21 and a MIMO system administrator for configuration and maintenance purposes.

[0164] Although the embodiments of the invention have been described manly with reference to symmetric MIMO configurations characterized by a same number of transmit and receive antennas, it should be noted that the invention may also be applied to asymmetric MIMO configurations with n.sub.t<n.sub.r. A linear representation in the form of equation (6) can also be obtained by performing the complex-to-real conversion of step 601 to the equivalent system given by:

U.sup.†y.sub.c=DV.sup.†s.sub.c+U.sup.†w.sub.c  (20)

[0165] In equation (20), the matrices U and V are unitary matrices obtained, together with matrix D, from the singular value decomposition of the matrix H.sub.c=UDV.sup.t. D is a diagonal matrix having positive diagonal entries representing the singular values of the matrix H.sub.c. The superscript (.).sup.† designates the Hermitian transposition operator.

[0166] Further, while some embodiments of the invention have been described in relation to a wireless single-user MIMO system, it should be noted that the invention is not limited to such an application. The invention may be integrated in any receiver device operating in any linear communication system characterized by a linear representation of the channel output. The communication system may be wired, wireless or optical fiber-based accommodating single or multiple users, using single or multiple antennas, and single or multi-carrier communication techniques. For example, the present invention may be integrated in a receiver device implemented in a wireless distributed MIMO system. Distributed MIMO may be used for example in cellular communications applied in 3G, 4G, LTE, and future 5G standard or the like. Cooperative communications applied for example in ad-hoc networks (wireless sensor networks, machine-to-machine communications, internet of things (IoT), etc) are also examples of distributed MIMO systems. In addition to wireless networks, the present invention may be integrated in optical receiver devices implemented in optical fiber-based communication systems, such as Polarization Division Multiplexing-OFDM (PDM-OFDM) systems.

[0167] Further, the invention is not limited to communication devices and may be integrated into signal processing devices such as electronic filters of finite impulse response (FIR) used in audio applications like audio crossovers and audio mastering. Accordingly, some embodiments may be used to determine an estimate of an input sequence, given an output sequence of a FIR filter of order M.

[0168] In another application, methods, devices and computer program products according to some embodiments of the invention may be implemented in a Global Navigation Satellite System (GNSS), such as IRNSS, Beidou, GLONASS, Galileo; GPS comprising for instance at least a GPS receiver for estimating positioning parameters using for example carrier phase measurements.

[0169] Further, methods, devices and computer program products according to some embodiments of the invention may be implemented in cryptographic systems for determining estimates on private secret values used in a cryptographic algorithm for encrypting/decrypting data or messages during their storage, processing or communication. In lattice-based cryptography applications, data/messages are encrypted in the form of lattice points. The decryption of such encrypted data may be advantageously performed according to some embodiments of the invention, enabling for a high probability of success recovery of secret values with a reduced complexity.

[0170] Furthermore, the methods described herein can be implemented by computer program instructions supplied to the processor of any type of computer to produce a machine with a processor that executes the instructions to implement the functions/acts specified herein. These computer program instructions may also be stored in a computer-readable medium that can direct a computer to function in a particular manner. To that end, the computer program instructions may be loaded onto a computer to cause the performance of a series of operational steps and thereby produce a computer implemented process such that the executed instructions provide processes for implementing the functions specified herein.

[0171] While embodiments of the invention have been illustrated by a description of various examples, and while these embodiments have been described in considerable details, it is not the intent of the applicant to restrict or in any way limit the scope of the appended claims to such details. Additional advantages and modifications will readily appear to those skilled in the art. The invention in its broader aspects is therefore not limited to the specific details, representative methods, and illustrative examples shown and described.