ELECTRICAL POWER CONVERTER

Abstract

A converter for converting a three-phase AC input into a DC output may include three phase input terminals and two output terminals, a phase selector for connecting the three-phase AC input to an upper intermediate node, a lower intermediate node, and a middle intermediate node. The phase selector includes semiconductor switches for selectively connecting the middle intermediate node to the three phase input terminals, and a controller. The electrical converter includes a boost circuit and a buck-boost circuit. The boost circuit includes an upper boost circuit, a lower boost circuit, and a common node. The buck-boost circuit has an output connected to the two output terminals in parallel with an output of the boost circuit, and includes at least two semiconductor switches that are actively switchable and connected in series across the output terminals. The middle intermediate node is connected to a common node of the two second semiconductor switches.

Claims

1. An electrical converter for converting a three-phase AC input into a DC output, the electrical converter comprising: three phase input terminals and two output terminals, a phase selector for connecting the three-phase AC input provided at the three phase input terminals to an upper intermediate node, a lower intermediate node and a middle intermediate node of the electrical converter, the phase selector comprising three rectifier bridge legs connected to the upper intermediate node and the lower intermediate node and first semiconductor switches that are actively switchable for selectively connecting the middle intermediate node to the three phase input terminals, a controller configured to control switching of the first semiconductor switches according to a switching pattern in which the phase input terminal having an intermediate voltage between the highest voltage and the lowest voltage is continuously connected to the middle intermediate node, a boost circuit for converting a voltage at the upper intermediate node and the lower intermediate node to an output voltage at the two output terminals, a buck-boost circuit having an output connected to the two output terminals in parallel with an output of the boost circuit, the buck-boost circuit comprising at least two second semiconductor switches that are actively switchable, wherein the at least two second semiconductor switches are connected in series across the output terminals, wherein the middle intermediate node is connected to a first common node of the at least two second semiconductor switches, and an output filter, comprising a series of at least two filter capacitors connected across the output terminals; wherein the boost circuit comprises a second common node, an upper boost circuit comprising a third actively switchable semiconductor switch connected across the upper intermediate node and the second common node, and a lower boost circuit comprising a fourth semiconductor switch connected across the second common node and the lower intermediate node, wherein the second common node is connected to a midpoint of the output filter, wherein the electrical converter comprises an input filter, the input filter comprising inductors operably connected to each one of the upper boost circuit, the lower boost circuit and the buck-boost circuit, wherein the input filter comprises capacitors operably connected to the inductors, wherein the capacitors are interconnected in a star connection and wherein the second common node is connected to a star point of the star connection, wherein the controller comprises a first current controller configured to generate a first pulse width modulated control signal for the at least two second semiconductor switches, a second current controller configured to generate a second pulse width modulated control signal for the third semiconductor switch, and a third current controller configured to generate a third pulse width modulated control signal for the fourth semiconductor switch, and wherein the controller is configured to determine an offset value representative of a difference between a measured voltage of the second common node and a setpoint voltage of the second common node and to feed the offset value to an input of the first, second and third current controllers.

2. The electrical converter of claim 1, wherein the inductors are operably connected to each one of the upper intermediate node, the lower intermediate node and the middle intermediate node.

3. The electrical converter of claim 2, wherein the inductors are connected between a respective one of the upper intermediate node, the lower intermediate node, and the middle intermediate node and a respective one of the upper boost circuit, the lower boost circuit, and the buck-boost circuit.

4. The electrical converter of claim 2, wherein the capacitors are connected between the phase input terminals and the inductors.

5. The electrical converter of claim 1, comprising a first measurement unit configured to measure a current through at least one of the inductors, and wherein a first current control loop is configured to adapt the first pulse width modulation control signal fed to the at least two second semiconductor switches based on the current measured.

6. The electrical converter of claim 5, wherein the first measurement unit is configured to measure the current in respect of the phase input terminal having the intermediate voltage.

7. The electrical converter of claim 5, wherein the controller is configured to generate the second and third pulse width modulation control signals interleaved with the first pulse width modulation control signal.

8. The electrical converter of claim 1, comprising a second measurement unit configured to measure voltages at the three phase input terminals and a third measurement unit configured to measure a voltage at the output terminals, both the second and the third measurement units being coupled to the controller.

9. The electrical converter of claim 1, wherein the three bridge legs of the phase selector comprise fifth semiconductor switches that are actively switchable.

10. The electrical converter of claim 1, wherein the upper boost circuit and the lower boost circuit each comprise a sixth semiconductor switch between the respective upper and lower intermediate node and the respective one of the two output terminals that is actively switchable.

11. A wireless charging system comprising a power supply unit, the power supply unit comprising the electrical converter of claim 1.

12. A magnetic resonance imaging apparatus comprising a gradient amplifier, the gradient amplifier comprising the electrical converter of claim 1.

13. A method of converting a three phase AC input into a DC output, the method comprising: rectifying the three phase AC input to obtain a rectified intermediate voltage across an upper intermediate node, a lower intermediate node and a middle intermediate node, wherein a phase input of the three phase AC input having a highest voltage is continuously applied to the upper intermediate node, a phase input of the three phase AC input having a lowest voltage is continuously applied to the lower intermediate node, and a phase input of the three phase AC input having an intermediate voltage between the highest voltage and the lowest voltage is continuously applied to the middle intermediate node, and boosting the rectified intermediate voltage to obtain the DC output, wherein boosting the rectified intermediate voltage comprises connecting the middle intermediate node to a buck-boost circuit, and connecting a boost circuit across the upper and lower intermediate node, wherein outputs of the boost circuit and the buck-boost circuit are connected in parallel, wherein the boost circuit comprises an upper boost circuit connected between a common node and the upper intermediate node and a lower boost circuit connected between the lower intermediate node and the common node, wherein boosting the rectified intermediate voltage comprises operably connecting an input filter comprising inductors and star-interconnected capacitors to the upper intermediate node, the lower intermediate node and the middle intermediate node, and connecting a star point of the capacitors to the common node, connecting an output filter comprising a series of at least two filter capacitors across two output terminals, and connecting the common node to a midpoint of the output filter individually controlling pulse width modulated control signals fed to semiconductor switches of the upper boost circuit, the lower boost circuit and the buck-boost circuit, measuring a voltage at the common node and determining an offset value representative of a difference between the measured voltage of the common node and a setpoint voltage of the common node, and using the offset value to adapt the pulse width modulated control signals.

14. The method of claim 13, further comprising interleaving pulse width modulation control of semiconductor switches of the upper boost circuit, the lower boost circuit, and the buck-boost circuit.

15. The electrical converter of claim 2, wherein each of the inductors is connected between one of the phase input terminals and the phase selector.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Aspects of the present disclosure will now be described in more detail with reference to the appended drawings, wherein same reference numerals illustrate same features and wherein:

[0036] FIG. 1 schematically shows an electrical converter that is unidirectional according to an embodiment of the present disclosure.

[0037] FIGS. 2A-G show diagrams with respectively voltages (FIG. 2A, 2B, 2C), currents (FIG. 2D, 2E) and switching states of the phase-selector switches (FIG. 2F) and switching states of the switches of the boost (upper and lower) and buck-boost circuits (FIG. 2G) during a 360° period of the AC mains voltage, and illustrates the overall operating principle of the electrical converter according to an embodiment of the present disclosure.

[0038] FIG. 3 shows a block diagram of an advantageous implementation of a central control unit and control method according to an embodiment of the present disclosure.

[0039] FIG. 4A, 4B, 4C show diagrams with voltages, currents and switching states within five consecutive switching cycles of the boost (upper and lower) and buck-boost bridge legs of the electrical converter, and illustrates the PWM modulation of these bridge legs according to an embodiment of the present disclosure.

[0040] FIG. 5 schematically shows an electrical converter that is bidirectional according to an embodiment of the present disclosure.

[0041] FIG. 6 schematically shows an electrical converter that is unidirectional, and that has an input filter that is placed before instead of after the phase selector according to an embodiment of the present disclosure.

[0042] FIG. 7A shows a first variant of the phase selector that can be used in electrical converters of the present disclosure.

[0043] FIG. 7B shows a second variant of the phase selector that can be used in electrical converters of the present disclosure.

[0044] FIG. 8A shows another variant of a phase selector that can be used in electrical converters of the present disclosure.

[0045] FIG. 8B shows yet another variant of a phase selector that can be used in electrical converters of the present disclosure.

[0046] FIG. 9 represents an electrical converter according to aspects of the present disclosure that is unidirectional and comprises a connection terminal for connecting to the neutral conductor of the grid (fourth phase).

DETAILED DESCRIPTION

[0047] FIG. 1 shows an electrical converter 10, referred to as the DUTCH RECTIFIER, comprising two power stages 11, 12 in the form of a three-phase active phase selector 11 and an output power stage 12. Electrical converter 10 further comprises an input filter 13, and an output filter 15.

[0048] The electrical converter 10 is an AC-to-DC converter that has three phase inputs A, B, C which are connected to a three-phase voltage of a three-phase AC grid 21, and two DC outputs P, N which for example may be connected to a DC load 22 such as, for example, a high voltage (e.g. 800 V) battery of an electric car.

[0049] The phase selector 11 comprises three phase connections a, b, c that are connected to the three phase inputs A, B, C, and three outputs x, y, z. These outputs may be seen as an upper intermediate voltage node x, a lower intermediate voltage node y, and a middle intermediate voltage node z.

[0050] The phase selector 11 comprises, or consists of, three bridge legs 16, 17, 18 which each comprise two passive semiconductor devices (diodes D.sub.ax and D.sub.ya for leg 16, D.sub.bx and D.sub.yb for leg 17, D.sub.cx and D.sub.yc for leg 18) connected in the form of a half bridge configuration, and three selector switches (S.sub.aza, S.sub.bzb, and S.sub.czc) which each comprise two anti-series connected actively switchable semiconductor devices. Each such switchable semiconductor device advantageously has an anti-parallel diode. In this example, Metal Oxide Field Effect Transistors (MOSFETs) are used for the actively switchable semiconductor devices, and each includes an internal anti-parallel body diode that may replace an external anti-parallel diode.

[0051] The output power stage 12 comprises, or consists of, two stacked boost bridge legs 19, 20 and one buck-boost bridge leg 14. Each boost bridge leg (19, 20) comprises a boost switch (S.sub.xm for the upper boost bridge leg 19 and S.sub.my for the lower boost bridge leg 20) and boost diode (D.sub.xP for the upper boost bridge leg 19 and D.sub.Ny for the lower boost bridge leg 20) connected in a half-bridge configuration. The buck-boost bridge leg 14 comprises two buck-boost switches (S.sub.Pz and S.sub.zN) connected in a half-bridge configuration. The middle node r of the upper boost bridge leg 19 is connected to intermediate voltage node x via an upper boost inductor L.sub.x, the middle node s of the lower boost bridge leg 20 is connected to intermediate voltage node y via a lower boost inductor L.sub.y, and the middle node t of the buck-boost bridge leg 14 is connected to intermediate voltage node z via a middle buck-boost inductor L.sub.z.

[0052] The common node m of both boost bridge legs 19, 20 is connected to the midpoint of the output filter 15 which comprises two output filter capacitors C.sub.Pm, C.sub.mN that are connected in series between the upper output node P and the lower output node N.

[0053] The upper boost bridge leg 19 is connected between the upper output node P and the common node m (i.e. in parallel with the upper output filter capacitor C.sub.Pm), and is arranged in a way that current can flow from the intermediate voltage node x to the upper output node P via the diode D.sub.xP when the switch S.sub.xm is open (not conducting, off state), and current can flow from the intermediate voltage node x to the common node m (or vice versa) via the switch S.sub.xm when the switch S.sub.xm is closed (conducting, on state). The boost switch (S.sub.xm) of the boost bridge leg 19 is an actively switchable semiconductor device, for example a MOSFET.

[0054] The lower boost bridge leg 20 is connected between the common node m and the lower output node N (i.e. in parallel with the lower output filter capacitor C.sub.mN), and is arranged in a way that current can flow from the lower output node N to the intermediate voltage node y via the diode D.sub.Ny when the switch S.sub.my is open (not conducting, off state), and current can flow from the common node m to the intermediate voltage node y (or vice versa) via the switch S.sub.my when the switch S.sub.my is closed (conducting, on state). The boost switch (S.sub.my) of the boost bridge leg 20 is an actively switchable semiconductor device, for example a MOSFET.

[0055] The buck-boost bridge leg 14 is connected between the upper output node P and the lower output node N (i.e. in parallel with the DC load 22) and is arranged in a way that current can flow from the intermediate voltage node z to the upper output node P (or vice versa) when the switch S.sub.Pz is closed (conducting, on state) while the switch S.sub.zN is open (not conducting, off state), and current can flow from the intermediate voltage node z to the lower output node N (or vice versa) when the switch S.sub.zN is closed (conducting, on state) while the switch S.sub.Pz is open (not conducting, off state). The buck-boost switches (S.sub.Pz, S.sub.zN) of the buck-boost bridge leg 14 are actively switchable semiconductor devices, e.g. MOSFETs, which are controlled in a complementary way (i.e. the one is closed while the other is open and vice versa).

[0056] Advantageously, three high-frequency (HF) filter capacitors C.sub.x, C.sub.y, C.sub.z, which are part of the input filter 13, are interconnecting the intermediate voltage nodes x, y, z in the form of a star-connection. Generally, it is advantageous that the three capacitors C.sub.x, C.sub.y, C.sub.Z have substantially equal value so as to symmetrically load the AC grid.

[0057] The bridge leg of the phase selector 11 that is connected with the phase input A, B, or C that has the highest voltage of the three-phase AC input voltage is switched in a way that the corresponding phase input A, B, or C is connected to the upper intermediate voltage node x. To achieve this, the bridge leg connects the corresponding phase connection a, b, or c with the node x via the upper diode (D.sub.ax, D.sub.bx, D.sub.cx) of the bridge leg, while the corresponding selector switch (S.sub.aza, S.sub.bzb, S.sub.czc) of the bridge leg is open (not conducting, off state). The bridge leg of the phase selector 11 that is connected with the phase input A, B, or C that has the lowest voltage of the three-phase AC input voltage is switched in a way that the corresponding phase input A, B, or C is connected to the lower intermediate voltage node y. To achieve this, the bridge leg connects the corresponding phase connection a, b, or c with the node y via the lower diode (D.sub.ya, D.sub.yb, D.sub.yc) of the bridge leg, while the corresponding selector switch (S.sub.aza, S.sub.bzb, S.sub.czc) of the bridge leg is open (not conducting, off state). The bridge leg of the phase selector 11 that is connected with the phase input A, B, or C that has a voltage between the highest voltage and the lowest voltage of the three-phase AC input voltage is switched in a way that the corresponding phase input A, B, or C is connected to the middle intermediate voltage node z. To achieve this, the bridge leg connects the corresponding phase connection a, b, or c with the node z via the selector switch (S.sub.aza, S.sub.bzb, S.sub.czc) which is closed (conducting, on state).

[0058] In a three-phase AC grid with substantially balanced phase voltages, for example as shown in FIG. 2A, the three-phase AC input voltage (shown in FIG. 2A) is converted into three intermediate DC voltages (ν.sub.xz, ν.sub.zy, ν.sub.xy; shown in FIG. 2B) provided between the upper intermediate voltage node x, the lower intermediate voltage node y and the middle intermediate voltage node z. These DC voltages thus show piece-wise sinusoidal shapes. The conversion of the three-phase AC input voltage into three intermediate DC voltages is the result of the operation of the phase selector 11, as explained above. The switching states (switch on.fwdarw.S=1, switch off.fwdarw.S=0) of the selector switches (S.sub.aza, S.sub.bzb, S.sub.czc) are shown in FIG. 2F. It can be seen that the switches are ‘on’ or ‘off’ continuously during whole particular 60° sectors within the period (360°) of the AC mains voltage. Also the diodes of the phase selector are ‘conducting’ or ‘not conducting’ during whole particular sectors, e.g. of 60°, within the period (360°) of the AC mains voltage. The combination of states of the switches and diodes is unique for every 60° sector of the three-phase AC input voltage and depends on the voltage value of the phase inputs (A, B, C). The sequence of the 6 unique states of the switches and diodes repeats itself every period (360°) of the AC mains voltage.

[0059] Seen from the viewpoint of the intermediate voltage nodes x, y, z towards the output terminals P, N, a conventional DC-DC boost circuit (upper boost circuit) is formed, comprising the HF filter capacitor C.sub.x, the upper boost inductor L.sub.x, the upper boost bridge leg 19, and the upper output capacitor C.sub.Pm. The input voltage of this upper boost circuit is the voltage ν.sub.c, (shown in FIG. 2C) across capacitor C.sub.x and the output voltage of this upper boost circuit is the voltage V.sub.Pm across the upper output capacitor C.sub.Pm, having a voltage value that is substantially equal to half the total DC bus voltage (V.sub.Pm≈V.sub.Dc/2). The formed upper boost circuit may be operated by PWM modulation of the switch S.sub.xm at a specified, possibly variable, switching frequency f.sub.s so as to control the current in the upper boost inductor L.sub.x.

[0060] Seen from the viewpoint of the intermediate voltage nodes x, y, z towards the output terminals P, N, a conventional ‘inversed’ (negative input voltage and negative output voltage) DC-DC boost circuit (lower boost circuit) is formed, comprising the HF filter capacitor C.sub.y, the lower boost inductor L.sub.y, the lower boost bridge leg 20, and the lower output capacitor C.sub.mN. The input voltage of this lower boost circuit is the voltage ν.sub.Cy, (shown in FIG. 2C) across capacitor C.sub.y and the output voltage of this lower boost circuit is the voltage V.sub.Nm across the lower output capacitor C.sub.mN, having a voltage value that is substantially equal to minus half the total DC bus voltage (V.sub.Nm≈V.sub.Dc/2). The formed lower boost circuit may be operated by PWM modulation of the switch S.sub.my at a specified, possibly variable, switching frequency f.sub.s so as to control the current in the lower boost inductor L.sub.y.

[0061] Seen from the viewpoint of the intermediate voltage nodes x, y, z towards the output terminals P, N, a conventional DC-DC buck-boost circuit (middle buck-boost circuit) is formed, comprising the HF filter capacitor C.sub.Z, the middle buck-boost inductor L.sub.z, the buck-boost bridge leg 14, and the series connection of the output capacitors C.sub.Pm, C.sub.mN. This DC-DC buck-boost circuit may be seen as to be similar to a single-phase half-bridge voltage-source converter (VSC). The input voltage of this middle buck-boost circuit is the voltage ν.sub.Cz (shown in FIG. 2C) across capacitor C.sub.z and the output voltage of this middle buck-boost circuit is the output voltage V.sub.DC across the series connection of the output capacitors C.sub.Pm, C.sub.mN. The formed middle buck-boost circuit may be operated by PWM modulation of the switches S.sub.Pz, S.sub.zN at a specified, possibly variable, switching frequency f.sub.s so as to control the current in the middle buck-boost inductor L.sub.z.

[0062] FIG. 2G shows the state of the switch S.sub.xm of the upper boost bridge leg 19, the state of the switch S.sub.my of the lower boost bridge leg 20, and the state of the switch S.sub.Pz (note that the state of the switch S.sub.zN is the complement of the state of the switch S.sub.Pz) of the middle buck-boost bridge leg 14. The switches S.sub.xm, S.sub.my, S.sub.Pz, S.sub.zN are all PWM modulated as can be seen from the black-colored bars, indicating PWM modulation of the corresponding switch.

[0063] An example of the currents i.sub.Lx, i.sub.Ly, i.sub.Lz in the inductors L.sub.x, L.sub.y, L.sub.Z is shown in FIG. 2D. As can be seen, these currents are controlled to have piece-wise sinusoidal shapes and are transformed, i.e., as a result of the operation of the phase selector 11, into three sinusoidal AC phase currents i.sub.a, i.sub.b, i.sub.c which are shown in FIG. 2E.

[0064] Referring to FIG. 1 and FIG. 3, to accomplish the piece-wise sinusoidal shapes of inductor currents i.sub.Lx, i.sub.Ly, i.sub.Lz, a central control unit 40 may be used which controls all the controllable semiconductor devices (switches) of the electrical converter 10, sending control signals to each switch via a communication interface 50. In particular, semiconductor devices S.sub.aza, S.sub.bzb, S.sub.czc, S.sub.xm, S.sub.my, S.sub.Pz, S.sub.zN are controlled by controller 40. Furthermore, the control unit has measurement input ports (42, 43, 44, 45), for receiving measurements of: [0065] 42: the AC-grid phase voltages ν.sub.a, ν.sub.b, ν.sub.c; [0066] 43: the inductor currents i.sub.Lx, i.sub.Ly, i.sub.Lz; [0067] 44: the DC bus voltage V.sub.Dc; [0068] 45: the DC bus mid-point voltage V.sub.mn=−V.sub.nm,

[0069] and an input port 41 to receive a set-value, which may be a requested DC output voltage V.sub.DC*.

[0070] FIG. 3 shows a block diagram of an advantageous implementation of the central control unit 40 which is shown in a schematically way in FIG. 1. The electrical converter 10 is represented in FIG. 3 as a ‘single-wire’ equivalent circuit, wherein the annotations of the elements correspond with those given in FIG. 1. Three slashes in a signal line indicate the bundling of three phase signals, and may represent the transition to a vector representation.

[0071] The goal of the control unit 40 is to control the output voltage V.sub.DC to a requested set-value V.sub.DC* that is received from an external unit via input port 41, and to balance the voltage across the two output capacitors C.sub.Pm and C.sub.mN, for example by controlling the voltage across the lower output capacitor C.sub.mN to be substantially equal to half the DC bus voltage. Additionally, the current drawn from the phase inputs (a,b,c) needs to be shaped substantially sinusoidal and controlled substantially in phase with the corresponding phase voltage. As explained previously, this can also be achieved by controlling the inductor currents i.sub.Lx, i.sub.Lyi.sub.Lz) i.e., instead of directly controlling the phase currents i.sub.a, i.sub.b, i.sub.c, to have piece-wise sinusoidal shapes. In particular, the low-pass filtered values of the inductor currents are controlled while the high-frequency ripple of the inductor currents is filtered by the HF filter capacitors (C.sub.x, C.sub.y, C.sub.Z).

[0072] The control of the output voltage V.sub.DC is advantageously done using a cascaded control structure, comprising an outer voltage control loop 60 and inner current control loop 70. The set-value of the output voltage is input to a comparator 61 via input port 41, and is compared with the measured output voltage obtained from a measurement processing unit 95 (for example comprising a low-pass filter). The output of comparator 61 is the control-error signal of the output voltage, which is further input to a control element 62 (for example comprising a proportional-integral control block) that outputs the instantaneous set-values of the amplitudes of the phase currents. These amplitudes are input to multiplier 63, and multiplied with signals that are obtained from calculation element 64 that outputs normalized instantaneous values of the phase voltages. The input of calculation element 64 are the measured phase voltages obtained from a measurement processing unit 93 (for example comprising a low-pass filter). The output of the multiplier 63 are set-values i.sub.a*, i.sub.b*, i.sub.c* for the instantaneous, for example low-pass filtered, phase currents i.sub.a, i.sub.b, i.sub.c and co b) c) are shaped substantially sinusoidal and positioned substantially in phase with the corresponding phase voltages. The set-values i.sub.a*, i.sub.b*, i.sub.c* are input to the current controller 70 after passing an addition element 67 and a selection element 81 whose functions are further detailed in the following text.

[0073] The current controller 70 is split into three individual current controllers 71, 74, 77, wherein: [0074] individual current controller 71 is used for controlling the current in the middle buck-boost inductor L.sub.z. This control is done by PWM modulation of the switches S.sub.Pz, S.sub.zN of the middle buck-boost circuit containing middle buck-boost bridge leg 14. As a result of the operation of the phase selector 11, therewith, controller 71 controls the current of the phase input A,B,C, that has a voltage between the highest voltage and the lowest voltage of the three-phase AC voltage; [0075] individual current controller 74 is used for controlling the current in the upper boost inductor L.sub.x. This control is done by PWM modulation of the switch S.sub.xm of the upper boost circuit containing upper boost bridge leg 19. As a result of the operation of the phase selector 11, therewith, controller 74 controls the current of the phase input A,B,C, that has the highest voltage of the three-phase AC voltage; [0076] individual current controller 77 is used for controlling the current in the lower boost inductor L.sub.y. This control is done by PWM modulation of the switch S.sub.my of the lower boost circuit containing lower boost bridge leg 20. As a result of the operation of the phase selector 11, therewith, controller 77 controls the current of the phase input A,B,C, that has the lowest voltage of the three-phase AC voltage.

[0077] Selector element 81 is used to send the set-values i.sub.a*, i.sub.b*, i.sub.c* (shown in FIG. 2D) for the instantaneous phase currents to the correct individual current controller (71, 74, 77) depending on the voltage value of the phase inputs (A, B, C), resulting in inductor current set-values i.sub.Lx*, i.sub.Ly*, i.sub.Lz* (shown in FIG. 2E) for each inductor current controller, wherein: [0078] the set-value of the phase current of the phase input A,B,C, that has the highest voltage of the three-phase AC voltage is sent to individual current controller 74, resulting in set-value i.sub.Lx*; [0079] the set-value of the phase current of the phase input A,B,C, that has the lowest voltage of the three-phase AC voltage is sent to individual current controller 77, resulting in set-value i.sub.Ly*; [0080] the set-value of the phase current of the phase input A,B,C, that a voltage between the highest voltage and the lowest voltage of the three-phase AC voltage is sent to individual current controller 71, resulting in set-value i.sub.Lz*.

[0081] In each individual current controller the received set-value (i.sub.Lx*, i.sub.Ly*, i.sub.Lz*) for the instantaneous inductor current is input to a comparator, for example comparator 72 of individual current controller 71, and compared with the measured inductor current obtained from a measurement processing unit 94 (for example comprising a low-pass filter). The output of the comparator is the control-error signal of the current, which is further input to a control element, for example control element 73 of individual current controller 71, whose output is input to a PWM generation element, for example PWM generation element 54 of individual current controller 71. The PWM generation element of the individual current controllers generate the PWM-modulated control signals for the controllable semiconductor switches of the PWM-controlled bridge legs, i.e. the upper boost bridge leg 19 of the upper boost circuit, the lower boost bridge leg 20 of the lower boost circuit, and the middle buck-boost bridge leg 14 of the middle buck-boost circuit. These PWM-modulated control signals are sent to the appropriate bridge legs via communication interface 50.

[0082] The selector switches of the phase selector 11 are either ‘on’ or ‘off’ during each 60° sector of the three-phase AC input voltage, depending on the voltage value of the phase inputs (A, B, C). The control signals for the selector switches are generated by switch-signal generators 51, 52, 53.

[0083] DC bus mid-point balancing is done by adding an offset value to the set-values i.sub.a*, i.sub.b*, i.sub.c* for the instantaneous, for example low-pass filtered, phase currents i.sub.a, i.sub.b, i.sub.c, which are output by multiplier 63. The offset value is obtained by comparing the measured DC bus midpoint voltage obtained from a measurement processing unit 96 (for example comprising a low-pass filter) with a set-value (for example V.sub.DC/2) using comparator 65 and feeding the error signal output by the comparator 65 into a control element 66.

[0084] The phase currents i.sub.a, i.sub.b, i.sub.s shown in FIG. 2E are obtained by controlling the electrical converter 10 using such control unit 40 and control method detailed in the foregoing text. Also shown in FIG. 2E are the set-values i.sub.a*, i.sub.b*, i.sub.c* for the instantaneous, for example low-pass filtered, phase currents i.sub.a, i.sub.b, i.sub.c as input to selector element 81 shown in FIG. 3. As explained above, the phase currents i.sub.a, i.sub.b, i.sub.c are indirectly controlled, i.e., they are the result of the controlling of the inductor currents i.sub.Lx, i.sub.Ly, i.sub.Lz (shown in FIG. 2D) and the operation of the phase selector 11. The set-points for the inductor currents (i.sub.Lx*, i.sub.Ly*, i.sub.Lz*) are derived from set-values i.sub.a*, i.sub.b*, i.sub.c* by selector element 81 based on the measured phase voltages.

[0085] FIGS. 4A-4C show diagrams within five consecutive switching cycles (i.e., each having a switching period T.sub.s equal to 1/f.sub.s, with f.sub.s the switching frequency) of the bridge legs of the electrical converter 10, for a time interval around ωt=45° which lies within the sector of the three-phase AC input voltage where 0≤ωt<60° (see FIG. 2). Within this sector, the selector switches and diodes of the phase selector 11 are in the following switching states: [0086] Switch S.sub.aza=0 (off), diode D.sub.ax=1 (conducting), diode D.sub.ya=0 (blocking); phase connection a is connected with node x; [0087] Switch S.sub.bzb=0 (off), diode D.sub.bx=0 (blocking), diode D.sub.yb=1 (conducting); phase connection b is connected with node y; [0088] Switch S.sub.czc=1 (on), diode D.sub.cx=0 (blocking), diode D.sub.y, =0 (blocking); phase connection c is connected with node z;

[0089] The diagrams of FIGS. 4A-4C show voltages, currents, and switching signals on a milliseconds time axis. FIG. 4A corresponds with the operation of the upper boost circuit, showing the corresponding inductor current i.sub.Lx (and the set-value i.sub.Lx*, of this current), the inductor voltage ν.sub.Lx, and the control signal S.sub.xm of the switch of the PWM-modulated upper boost bridge leg 19. FIG. 4B corresponds with the operation of the lower boost circuit, showing the corresponding inductor current i.sub.Ly (and the set-value i.sub.Ly* of this current), the inductor voltage ν.sub.Ly, and the control signal S.sub.my of the switch of the PWM-modulated lower boost bridge leg 20. FIG. 4C corresponds with the operation of the middle buck-boost circuit, showing the corresponding inductor current i.sub.Lz (and the set-value i.sub.Lz* of this current), the inductor voltage ν.sub.Lz, and the control signal S.sub.Pz of the upper switch of the PWM-modulated bridge leg 14. Note that the control signal S.sub.zN of the lower switch of the PWM-modulated bridge leg 14 is the complement of the control signal S.sub.Pz.

[0090] To minimize the Total Harmonic Distortion (THD) of the AC input current of the electrical converter, the high-frequency ripple of phase currents i.sub.a, i.sub.b, i.sub.c is advantageously minimized.

[0091] An advantage of the electrical converter 10 is that the half-switching-period volt-seconds product/area of the upper boost inductor and of the lower boost inductor are smaller than the volt-seconds products/areas of the boost inductors of a conventional six-switch boost-type PFC rectifier. This is because the voltages applied to these inductors are smaller than the three AC phase voltages in the case of a conventional six-switch boost-type PFC rectifier. For the middle buck-boost inductor, the applied voltages are not necessarily smaller but the value of the current flowing in the inductor is smaller than the value of the currents flowing in inductors of a conventional six-switch boost-type PFC rectifier. As a result, smaller inductors with less magnetic energy storage are feasible, resulting in a higher power-to-volume ratio of the electrical three-phase AC-to-DC converter 10 that is provided by the present disclosure.

[0092] The electrical converter 10 shown in FIG. 1 is unidirectional since the phase selector 11 and the output power stage 12 contain diodes, only allowing power to be drawn from the electrical AC grid 21 and provide this power at the output to a load 22. FIG. 5, on the other hand, shows an electrical converter 200 that is bidirectional. Electrical converter 200 differs from converter 10 in that the diodes (D.sub.ax, D.sub.bx, D.sub.cx, D.sub.ya, D.sub.yb, D.sub.yc) of the phase selector 11 and the diodes (D.sub.xP, D.sub.Ny) of the output power stage 12 of the converter shown in FIG. 1 have been replaced with controllable semiconductor switches (S.sub.xa, S.sub.xb, S.sub.xc, S.sub.ay, S.sub.by, S.sub.cy) in the phase selector 211 and (S.sub.yN, S.sub.Px) in the output power stage 212 respectively.

[0093] In FIG. 6, an electrical converter 300 is shown which differs from converter 10 in that the input filter 13 is placed before (instead of after) phase selector 11, i.e. the input filter 13 is connected between the phase input terminals A, B, C and the phase selector 11. The phase selector 11 connects the phase input terminals A, B, C to the intermediate nodes x, y, z via the corresponding inductor L.sub.a, L.sub.b, L.sub.c of the input filter 13. Capacitors C.sub.a, C.sub.b, C.sub.c are arranged between the phase input terminals and the inductors. The capacitors are connected in a star configuration, advantageously with the star point connected to a midpoint of the output filter 15, just like in the previous examples. Alternatively, the capacitors C.sub.a, C.sub.b, C.sub.c can be arranged in a delta configuration across the three phase input lines. It will be convenient to note that in the example of FIG. 6, the voltage signal at the three intermediate nodes x, y, z is somewhat different as compared to the previous examples (FIG. 1, FIG. 5), since the phase selector will be switching high frequency voltages output by the input filter 13 rather than pure three phase sinusoidal signals supplied by source 21. As a result, high frequency currents will be flowing through the phase selector 11, whereas in the previous examples (FIG. 1 and FIG. 5) the high frequency currents only occur in the output power stage downstream of the input filter 13.

[0094] In either electrical converters 10, 200, and 300, diodes may be replaced by actively switchable semiconductor devices to allow for bidirectional power flow of the electrical converter.

[0095] In either electrical converters 10, 200 and 300, the HF capacitors C.sub.x, C.sub.y, C, (or C.sub.a, C.sub.b, C.sub.c in case of FIG. 6) are connected in a star configuration. The voltage in the star point connection is controlled by controlling the voltage at the common node m.

[0096] FIG. 7A, 7B show different variants of the three-phase phase selector 11, which may be used in the electrical converters of either FIG. 1, FIG. 5, FIG. 6. In FIGS. 8A-B yet other variants of the three-phase phase selector 11 are shown. In these variants, the three bridge legs 16, 17 and 18 of the phase selector are arranged as half-controlled thyristor legs (FIG. 10A), i.e. comprising thyristors Thy.sub.ax, Thy.sub.bx, Thy.sub.cx in the bridge leg portions connected to the upper intermediate node and diodes in the other bridge leg portion connected to the lower intermediate node (or vice versa), or as full-controlled thyristor legs (FIG. 10B), i.e. comprising a thyristor Thy.sub.ax, Thy.sub.bx, Thy.sub.cx, Thy.sub.ya, Thy.sub.yb, Thy.sub.yc, in each bridge half leg, instead of diodes. Such a phase selector allows for controllably pre-charging the output filter capacitors C.sub.Pm, C.sub.mN, or C.sub.PN without requiring an additional pre-charge circuit.

[0097] Referring to FIG. 9, the electrical converter 10 (and which may alternatively be the electrical converter 200 or 300) can comprise a connection terminal N for connecting the neutral conductor of the three-phase AC grid. In some applications, such as for example the charging of electric vehicles, it is often required that the amplitude of the sinusoidal current drawn from each phase of the three-phase grid can be independently controlled so as to be able to decrease the loading of a certain phase such that other consumer devices are still able to draw power from that particular phase during the charging of the vehicle's battery while not overloading the phase. In this case, the connection terminal N is advantageously connected to the neutral conductor of the three-phase grid, allowing a return current substantially equal to the sum of the three phase currents to flow back to the neutral conductor of the grid. In an advantageous aspect, the three phase currents can be fully independently controlled by providing a common node connected to the neutral conductor of the input.

[0098] The neutral connection terminal N is advantageously connected to the star-point of the AC capacitors C.sub.x, C.sub.y, C.sub.z and to the common node m of the stacked boost bridges 19, 20 (and thus also to the midpoint of the output filter 15). This results in a fully symmetrical converter structure. In this case, the voltage at the star-point and at the common node is equal to the voltage of the neutral conductor of the grid. Also in this case, the three current controllers 71, 74, 77 can be fed with an offset, e.g. a difference between the voltage of the common node m (voltage of neutral conductor) and a setpoint voltage. By so doing, a nonzero current can be injected in the neutral conductor, allowing to operate the converter with unbalanced phase currents and hence to control the three phase currents independently.

[0099] Other aspects of the present disclosure are set out in the following clauses:

[0100] A. Electrical converter (10) for converting a three-phase AC input into a DC output, comprising: [0101] three phase input terminals (A, B, C) and two output terminals (P, N), [0102] a phase selector (11) for connecting the three-phase AC input provided at the three phase input terminals to an upper intermediate node (x), a lower intermediate node (y) and a middle intermediate node (z) of the electrical converter, the phase selector comprising first semiconductor switches (S.sub.aza, S.sub.bzb, S.sub.czc) that are actively switchable for selectively connecting the middle intermediate node to the three phase input terminals, [0103] a boost circuit (19, 20, 423, 524) for converting a voltage at the upper intermediate node (x) and the lower intermediate node (y) to an output voltage at the two output terminals (P, N), and [0104] a controller (40) configured to control switching of the first semiconductor switches according to a switching pattern in which: [0105] the phase input terminal having a highest voltage is continuously connected to the upper intermediate node, [0106] the phase input terminal having a lowest voltage is continuously connected to the lower intermediate node, and [0107] the phase input terminal having an intermediate voltage between the highest voltage and the lowest voltage is continuously connected to the middle intermediate node,

[0108] wherein the electrical converter comprises a buck-boost circuit (14) having an output connected to the two output terminals (P, N) in parallel with an output of the boost circuit, the buck-boost circuit comprising at least two second semiconductor switches (S.sub.Pz, S.sub.zN) that are actively switchable, wherein the at least two second semiconductor switches are connected in series across the output terminals (P, N), and wherein the middle intermediate node (z) is connected to a common node (t) of the at least two second semiconductor switches.

[0109] B. Electrical converter of clause A, wherein the boost circuit comprises at least one third semiconductor switch (S.sub.xm, S.sub.my, S.sub.xy) that is actively switchable and at least one fourth semiconductor switch (D.sub.xP, D.sub.Ny, S.sub.Px, S.sub.yN), wherein the at least one third semiconductor switch and the at least one fourth semiconductor switch are connected in series across the output terminals (P, N).

[0110] C. Electrical converter of clause B, comprising an output filter (15) comprising a series of at least two filter capacitors (C.sub.Pm, C.sub.mN) connected across the output terminals (P, N), wherein the boost circuit comprises a common node (m), an upper boost bridge leg (19) comprising a first one (S.sub.xm) of the at least one third semiconductor switch connected across the upper intermediate node (x) and the common node (m), and a lower boost bridge leg (20) comprising a second one of the at least one third semiconductor switch (S.sub.my) connected across the common node (m) and the lower intermediate node (y), wherein the common node (m) is connected to a midpoint of the output filter.

[0111] D. Electrical converter of any one of the preceding clauses, comprising an input filter (13), the input filter comprising an inductor (L.sub.x, L.sub.y, L.sub.z, L.sub.a, L.sub.b, L.sub.c) operably connected to each one of the upper intermediate node (x), the lower intermediate node (y) and the middle intermediate node (z).

[0112] E. Electrical converter of clause D, wherein each of the inductors (L.sub.x, L.sub.y, L.sub.z, L.sub.a, L.sub.b, L.sub.c) is connected: [0113] between the respective intermediate node (x, y, z) and the boost circuit, respectively the buck-boost circuit (14), or [0114] between one of the phase input terminals (A, B, C) and the phase selector (11).

[0115] F. Electrical converter of clause D or E, wherein the input filter (13) comprises capacitors (C.sub.x, C.sub.y, C.sub.z, C.sub.a, C.sub.b, C.sub.c) operably connected to the inductors (L.sub.x, L.sub.y, L.sub.z, L.sub.a, L.sub.b, L.sub.a).

[0116] G. Electrical converter of clause F, wherein the capacitors (C.sub.x, C.sub.y, C.sub.z, C.sub.a, C.sub.b, C.sub.c) are connected between the phase input terminals (A, B, C) and the inductors (L.sub.x, L.sub.y, L.sub.z, L.sub.a, L.sub.b, L.sub.a).

[0117] H. Electrical converter of clause F or G, wherein the capacitors (C.sub.x, C.sub.y, C.sub.z, C.sub.a, C.sub.b, C.sub.c) are interconnected in the form of a delta connection or star connection.

[0118] I. Electrical converter of clause H in conjunction with clause C, wherein the capacitors (C.sub.x, C.sub.y, C.sub.z, C.sub.a, C.sub.b, C.sub.c) are interconnected in a star connection and wherein the common node (m) is connected to a star point of the star connection.

[0119] J. Electrical converter of any one of the clauses D to I, comprising means (94) for measuring a current (i.sub.Lx, i.sub.Ly, i.sub.Lz, i.sub.La, i.sub.Lb, i.sub.Lc) through at least one of the inductors (L.sub.x, L.sub.y, L.sub.z, L.sub.a, L.sub.b, L.sub.c), and wherein the controller (40) comprises a current control loop (70) configured to adapt a first pulse width modulation control signal fed to the at least two second semiconductor switches based on the current measured (i.sub.Lx, i.sub.Ly, i.sub.Lz, i.sub.La, i.sub.Lb, i.sub.Lc).

[0120] K. Electrical converter of clause J, wherein the means for measuring the current is configured to measure the current in respect of the phase input terminal having the intermediate voltage.

[0121] L. Electrical converter of clause J or K in conjunction with clause 2 or 3, wherein the controller (40) is configured to generate a second pulse width modulation control signal fed to the at least one third semiconductor switch (S.sub.xm, S.sub.my, S.sub.xy), wherein the first and second pulse width modulation control signals are interleaved.

[0122] M. Electrical converter of any one of the preceding clauses, comprising means (93) for measuring voltages at the three phase input terminals and means (96) for measuring a voltage at the output terminals, both being coupled to the controller (40).

[0123] N. Electrical converter of any one of the preceding clauses, wherein the phase selector comprises three selector legs (16, 17, 18) for interconnecting one of the three phase input terminals to the upper intermediate node (x), the lower intermediate node (y) and the middle intermediate node (z), wherein each of the three selector legs comprises a half bridge comprising fifth semiconductor switches (D.sub.ax, D.sub.bx, D.sub.cx, D.sub.ya, D.sub.yb, D.sub.yc, S.sub.xa, S.sub.xb, S.sub.xc, S.sub.ay, S.sub.by, S.sub.cy).

[0124] O. Electrical converter of clause N, wherein the fifth semiconductor switches are actively switchable (S.sub.xa, S.sub.xb, S.sub.xc, S.sub.ay, S.sub.by, S.sub.cy).

[0125] P. Electrical converter of any one of the clauses D to 0 in conjunction with clause B or C, wherein the at least one fourth semiconductor switch (S.sub.Px, S.sub.yN) is actively switchable.

[0126] Q. Wireless charging system, in particular for charging a battery of an electric vehicle, comprising a power supply unit, the power supply unit comprising the electrical converter of any one of the preceding clauses.

[0127] R. Magnetic resonance imaging apparatus comprising a gradient amplifier, the gradient amplifier comprising the electrical converter of any one of the clauses A to P.

[0128] S. Method of converting a three phase AC input into a DC output, comprising: [0129] rectifying the three phase AC input to obtain a rectified intermediate voltage across an upper intermediate node (x), a lower intermediate node (y) and a middle intermediate node (z), wherein a phase input of the three phase AC input having a highest voltage is continuously applied to the upper intermediate node (x), a phase input of the three phase AC input having a lowest voltage is continuously applied to the lower intermediate node (y), and a phase input of the three phase AC input having an intermediate voltage between the highest voltage and the lowest voltage is continuously applied to the middle intermediate node (z), and [0130] boosting the rectified intermediate voltage to obtain the DC output, [0131] wherein the boosting step comprises connecting the middle intermediate node (z) to a buck-boost circuit (14).

[0132] T. Method of clause S, wherein the boosting step comprises using a boost circuit (19, 20, 423, 524) connected across the upper and lower intermediate node and wherein outputs of the boost circuit and the buck-boost circuit (14) are connected in parallel.