MICRO-ACOUSTIC WAFER-LEVEL PACKAGE AND METHOD OF MANUFACTURE

Abstract

A wafer-level package for micro-acoustic devices and a method of manufacture is provided. The package comprises a base wafer with electric device structures. A frame structure is sitting on top of the base wafer enclosing particular device areas for the micro-acoustic devices. A cap wafer provided with a thin polymer coating is bonded to the frame structure to form a closed cavity over each device area and to enclose within the cavity the device structures arranged on the respective device area.

Claims

1. A micro-acoustic wafer-level package, comprising: a base wafer (BW) with electric structures (ES) for micro-acoustic devices on a top surface thereof, each electric structure being assigned to a respective device area (DA); a frame structure (FS) sitting on top of the base wafer enclosing each particular device area; and a cap wafer (CW) bonded to the frame structure to form a closed cavity (CV) over each device area and to enclose within the cavity the device structures arranged on the respective device area; wherein: the base wafer comprises a piezoelectric functional layer; the cap wafer comprises a glass wafer having a polymer coating (PC) on a bottom surface thereof; and the frame structure comprises a polymer.

2. The micro-acoustic wafer-level package of claim 1, wherein the polymer coating is formed from an UV-curable photoresist.

3. The micro-acoustic wafer-level package of claim 1, wherein the glass material of the cap wafer comprises additional elements chosen from first and second main group of the periodic system, to provide a CTE that is matched to the CTE of the base wafer.

4. The micro-acoustic wafer-level package of claim 1, wherein the electric structures comprise a SAW transducer, wherein the base wafer is a piezoelectric wafer, and wherein the glass material of the cap wafer has a CTE that is matched to the CTE of the piezoelectric wafer.

5. The micro-acoustic wafer-level package of claim 1, wherein the base wafer comprises a carrier wafer, wherein the electric structures comprise a SAW transducer or a BAW resonator realized within the piezoelectric functional layer, and wherein the CTE of the cap wafer is adapted to the CTE of the carrier wafer.

6. The micro-acoustic wafer-level package of claim 1, wherein the base wafer comprises a wafer of LiTaO.sub.3 or LiNbO.sub.3.

7. The micro-acoustic wafer-level package of claim 1, wherein the glass material of the cap wafer comprises Ba as an additional element.

8. The micro-acoustic wafer-level package of claim 1, wherein the micro-acoustic wafer-level package is used to singulate a micro-acoustic device, wherein each single device comprises exactly one cavity with respectively enclosed electric structures.

9. A method of forming a micro-acoustic wafer-level package, the method comprising: providing a base wafer with an array of device areas on a top surface thereof assigned to a respective micro-acoustic device each; forming a frame structure on the top surface that encloses each particular device area with the respective electric structures; providing a cap wafer having an CTE adapted to the CTE of the base wafer and being provided with a UV-curable polymer coating on an underside thereof; arranging the cap wafer on the frame structure; and wafer-bonding the cap wafer with the polymer coating to the frame structure and curing the polymer coating by exposing the arrangement to UV light.

10. The method of claim 9, wherein wafer-bonding of the cap wafer with the polymer coating to the frame structure comprises applying UV light and uni-axial pressure at the same time to the whole arrangement.

Description

[0028] In the following the invention is explained in more detail with regard to specific embodiments and the relating figures. The figures are schematic only and not drawn to scale. Hence, no absolute or relative dimensions can be taken from the figures.

[0029] FIG. 1 shows a cross sectional view of an arrangement of a base wafer and a cap wafer

[0030] FIG. 2 shows the arrangement of FIG. 1 after bonding the base wafer and the cap wafer to form a wafer level package

[0031] FIG. 3 shows in a cut-out of FIG. 2 how the two wafers are connected

[0032] FIGS. 4 to 6 show in a cross sectional view different process steps of a half-cut dicing process that facilitates the later singulation of particular packaged devices

[0033] FIG. 7 shows a perspective view of a singulated micro-acoustic device after packaging, further processing and singulation.

[0034] FIG. 1 shows an arrangement of a base wafer BW and a cap wafer CW in a cross sectional view. In this embodiment the base wafer BW is a piezoelectric wafer of LiNbO.sub.3 or LiTaO.sub.3. On the top surface of the base wafer metallic electric structures ES are provided comprising electrodes and transducers of a SAW device. A frame structure FS is formed on the top surface of the base wafer BW. This can be done by applying a photoresist to the entire top surface and lithographically structuring same. By this structuring step each device area DA on the base wafer BW that complies with the active chip area of the later device is completely surrounded by the frame structure FS.

[0035] The frame structure may comprise separated frames for each device area DA1, DA2 as shown. It is also possible that the frame structure has broader width that is may separated in a later singulation process at the edge of the later device. Electric contact areas (not shown in the figure) of the electric device structures may extend under the frame structure to an area on the surface of the base wafer that is not enclosed by the frame structure FS. In a variant the electric contact areas are provided under the frame structure and need to be exposed in a later step.

[0036] The cap wafer CW is a glass wafer that has a thin polymer coating PC at its bottom side.

[0037] The polymer may be an UV-curable photoresist that is applied with a layer thickness of e.g. 1000 nm to 1500 nm, which ends up to a final intermediate layer thickness in the order of 100 nm to 500 nm after Waferbonding.

[0038] Then the cap wafer CW is attached to the frame structure FS with its bottom side. To make a tight connection the cap wafer is exposed to UV light from the top for a period of about 100 seconds or more. Thereby uniaxial pressure is applied normal to the surface of cap wafer or base wafer the compress the arrangement that a tight bonding is achieved.

[0039] FIG. 2 shows the arrangement at this step. Cavities CV are formed between base wafer BW and cap wafer CW over each device area DA by the frame structure FS forming the side walls thereof. In the cavities the electric structures are enclosed keeping a gap to the cap wafer. Dotted separation lines SL indicate the later edges along which the single devices can be separated from the large area wafer package. Chip area CA indicates the area of a single device/chip after a later singulation process.

[0040] FIG. 3 is an enlarged cut-out at the edge of a later device to show the tight connection between frame structure FS and the cured polymer coating of the cap wafer CW.

[0041] FIGS. 4 to 6 show in a cross sectional view different process steps of a half-cut dicing process that facilitates the later singulation of particular packaged devices.

[0042] FIG. 4 to 6 show in a cross sectional view a base wafer BW having a top surface onto which a frame structure FS has been applied. The frame structure surrounds and encloses a device area DA on the surface of which electric structures for a micro acoustic device are formed (not shown in the figure). Each section of the frame structure FS may be assigned to one respective device area DA as shown. However it is also positive that a section of the frame structure FS separates two adjacent device areas and is hence common to both device areas. In those embodiments the later singulation of particular devices requires cutting through the frame structure such that the cavities of each device remain closed and tight.

[0043] In the bottom surface the cap wafer CW of a glass material that has to be bonded to the base wafer trenches TR are formed. These trenches comply with separation lines SL and are hence preforming the later device edge. Each trench is formed with a depth that is deeper than the later thickness of the cap where a cap is a section of the cap wafer CW that covers just one single device and closes one single cavity as a lid. A thin polymer coating PC of a UV curable polymer is applied to the entire bottom surface of the cap wafer CW and may extend to the sidewalls of the trench TR or may alternatively be applied to the bottom surface before forming the trench TR such that the sidewalls are free of polymer coating PC.

[0044] The cap wafer CW is then attached to the base wafer BW respectively to the frame structure FS on the top surface thereof. The entire arrangement is exposed to UV light for time sufficient to cure the polymer coating. By curing the polymer a tight and adhesive connection between frame structure and polymer forms.

[0045] In an embodiment a curing time of about 100 s is set. The process time is much shorter than the actual thermos-compression wafer bonding process that usually needs about 30 minutes.

[0046] After curing that is comparable with wafer bonding the cured polymer on the inner surface of the package/cavity offers an increased mechanical strength of the package by coating possible micro-cracks and precluding/minimizing subcritical crack growth. FIG. 5 shows the arrangement at this stage.

[0047] The so-formed wafer arrangement of the two wafers bonded together is subjected to a singulation process. In a first step thereof the cap wafer can be diced easily by grinding the top surface thereof until the bottom of the trenches is exposed. This can be done in a CMP (chemical mechanical polishing) process. FIG. 6 shows the arrangement at this stage. A further advantage of the thinning of the cap wafer the total height of the device is reduced. The final thickness of the cap is much thinner than the thickness of the cap wafer made of glass that is required to provide sufficient mechanical stability for secure handling of the cap wafer. When supported on the frame structures and after singulation the mechanical strength is high enough with the reduced final cap thickness of about 20 μm to 60 μm.

[0048] At the bottom of the now opened trenches TR the top surface of the base wafer BW is exposed between each two adjacent sections of the frame structures FS. Hence forming of contact pads from a metallization is possible at this (wafer level) stage. The contact pads KO of each later singulated micro-acoustic device are provided on the top surface of the cap/cap wafer.

[0049] According to an embodiment, an entire-surface base metallization is applied to the back of the cap wafer CW and the exposed surface of the base wafer BW. A structuring of the metallization follows that can be carried out with the help of an electroplating resist, which covers areas of the basic metallization that need not be reinforced. Thickening of the base metallization to the final layer thickness of the metallization is carried out by electroplating. Then the electroplating resist and the base metallization still existing in this area are removed, the latter by etching.

[0050] The formed metallization structure connects a pad of the device on the top surface of the base wafer BW to a contact pad KO on the top of the cap wafer CW. This contact pad KO is provided with a solderable top layer or a so-called under bump metallization.

[0051] This is followed by the selective application of bumps BU, for which the top layer of the metallization, which is for example a gold layer wetted with solder, is removed, except for those sections where the Bumps BU are to be applied. It is also possible to apply a resist that cannot be wetted with solder and structure it in such a way that openings are created in which the surface of the metallization that can be wetted with solder is exposed. The bumps BU themselves can be printed or electroplated. The bumps can also be applied as prefabricated balls and connected to the contacts by melting.

[0052] In the next step singulation of particular devices follows by dicing through the base wafer BW along the separation lines SL.

[0053] FIG. 7 shows an exemplary device in a perspective top view onto the cap. Six contact pads KO are provided for the device in the shown version, all of which are electrically conductively connected either to the electric structures ES on the top surface of the base wafer respectively the base substrate of the device after dicing. The number of contact pads KO equipped with bumps BU depends on the type of component. In the simplest case, two contact pads KO are sufficient to contact the micro-acoustic device encapsulated in the package. Especially for components working with acoustic waves, it is advantageous to provide a plurality of contacts for ground connections.

[0054] FIG. 7 shows a single micro-acoustic device in a package. This device can now be soldered to a final circuit by means of the bumps BU formed on the top surface of the cap wafer.

[0055] In alternative embodiments a contact to the electric structures of the devices is made by forming vias through the cap wafer (not shown). Similar to the trench-forming process these vias are preformed in an early step at the cap wafer before bonding it to the base wafer. The vias end up at the top surface of the cap and can also be covered with a contact pad and provided with bumps.

[0056] Though a number of variations of the process are possible all embodiments provide main advantages as follows: [0057] 1. A heterogeneous package solution for micro-acoustic devices like SAW filters on e.g. LiTaO3 or LiNbO3 with glass package is enabled [0058] 2. It is precluded that elements from the package material contaminate the cavity and hence the electric structures of the device [0059] 3. The mechanical strength of the glass package is increased [0060] 4. Compared to previous wafer-level packages only a very short processing time is required.

TABLE-US-00001 List of used reference symbols BU bump BW base wafer CA chip area CV cavity CW cap wafer DA device area ES electric structures FS frame structure KO contact pad PC polymer coating PL piezoelectric functional layer SL separation line TR trench