GATE VOLTAGE MAGNITUDE COMPENSATION EQUALIZATION METHOD AND CIRCUIT FOR SERIES OPERATION OF POWER SWITCH TRANSISTORS

Abstract

A gate voltage magnitude compensation equalization method and circuit for series operation of power switch transistors are provided. A dynamic voltage equalization of series-connected power switch transistors is implemented by using sampling principles where voltages of the power switch transistors are controlled by gate voltage magnitude and unbalanced voltage differentials are converted into unbalanced current differentials of buffer currents. The gate voltage magnitude compensation equalization method and circuit relates to differential control and works in a dynamic voltage change process of the series-connected power switch transistors, without having a negative effect on operation of the power switch transistors under normal operating conditions. Only adopting passive devices, the gate voltage magnitude compensation equalization circuit has a simple structure, is easy to integrate on a device drive board, implements response tracking of unbalanced voltage and voltage equalization of the series-connected power switch transistors, and improve speedability and stability of voltage equalization control.

Claims

1. A gate voltage magnitude compensation equalization circuit for series operation of power switch transistors, comprising: N power switch transistors, N sampling units, N gate voltage magnitude compensation units, and N gate drive circuits in series operation, wherein N is a natural number greater than or equal to two, each of the N power switch transistors is connected in parallel with a resistor-capacitor snubber circuit, and the each of the N power switch transistors corresponds to one sampling unit of the N sampling units, one gate voltage magnitude compensation unit of the N gate voltage magnitude compensation units, and one gate drive circuit of the N gate drive circuits; each of the N sampling units samples current values of the resistor-capacitor snubber circuits; each of the N gate voltage magnitude compensation units is connected to a corresponding sampling unit and obtains a sampling signal outputted by the corresponding sampling unit to obtain a current signal in direct proportion to a variation rate of an unbalanced voltage differential of a corresponding power switch transistor, and outputs the current signal to a corresponding gate drive circuit; and each of the N gate drive circuits adds a compensation voltage into a gate voltage of the corresponding power switch transistor, and outputs a voltage obtained by adding the compensation voltage into the gate voltage to the corresponding power switch transistor.

2. The gate voltage magnitude compensation equalization circuit according to claim 1, wherein the each of the N gate drive circuits comprises a drive voltage source and two gate drive resistors connected in series, two ends of either one of the two gate drive resistors are connected in parallel with the current signal introduced by a corresponding gate voltage magnitude compensation unit, and a drive compensation voltage in direct proportion to the variation rate of the unbalanced voltage differential is added into the gate voltage of the corresponding power switch transistor.

3. The gate voltage magnitude compensation equalization circuit according to claim 1, wherein the each of the N sampling units comprises N sampling inductors wound round a same magnetic ring, and a first sampling inductor of the N sampling inductors samples the current value of the resistor-capacitor snubber circuit connected in parallel with the corresponding power switch transistor, and remaining sampling inductors of the N sampling inductors sample the current values of the resistor-capacitor snubber circuits connected in parallel with remaining power switch transistors, respectively, the first sampling inductor is opposite to the remaining sampling inductors in a coil winding direction, and a number of turns of the first sampling inductor is N−1 times a number of turns of the remaining sampling inductors.

4. The gate voltage magnitude compensation equalization circuit according to claim 3, wherein the each of the N gate voltage magnitude compensation units comprises a drive voltage compensation inductor wound round the same magnetic ring, a coil winding direction of the drive voltage compensation inductor is identical to a coil winding direction of the first sampling inductor, the drive voltage compensation inductor, the first sampling inductor and the remaining sampling inductors are wound round the same magnetic ring to form a coupling transformer, and the drive voltage compensation inductor is connected in parallel to two ends of a gate drive resistor of the corresponding gate drive circuit.

5. The gate voltage magnitude compensation equalization circuit according to claim 1, wherein the N power switch transistors adopt insulation gate bipolar transistor (IGBT) modules, and an emitter of a (k−1).sup.th IGBT is connected to a collector of a k.sup.th IGBT, wherein k is a natural number and 2≤k≤N.

6. The gate voltage magnitude compensation equalization circuit according to claim 1, wherein the N power switch transistors adopt metal-oxide-semiconductor field-effect transistor (MOSFET) modules, and a source of a (k−1).sup.th MOSFET is connected to a drain of a k.sup.th MOSFET, wherein k is a natural number and 2≤k≤N.

7. The gate voltage magnitude compensation equalization circuit according to claim 1, wherein every two adjacent resistor-capacitor snubber circuits are in an overlapped layout, and electric currents flowing through snubber capacitors of the two adjacent resistor-capacitor snubber circuits are opposite in direction.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] FIG. 1 is a schematic diagram showing a voltage equalization circuit implementing series operation of a plurality of power switch transistors according to the present disclosure;

[0020] FIG. 2 is a schematic diagram showing a voltage equalization circuit implementing series operation of a plurality of IGBTs according to an embodiment of the present disclosure;

[0021] FIG. 3 is a schematic diagram showing a voltage equalization circuit implementing series operation of a plurality of SIC MOSFETs according to another embodiment of the present disclosure;

[0022] FIG. 4 is a schematic diagram showing a voltage equalization circuit implementing series operation of two SiC MOSFETs according to another embodiment of the present disclosure;

[0023] FIG. 5 is a layout chart showing a snubber capacitor for reducing parasitic capacitance according to an embodiment of the present disclosure; and

[0024] FIG. 6 is a diagram showing dynamic voltage equalization experiment verification results of series operation of two SiC MOSFETs according to an embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] To more specifically describe the present disclosure, the technical solutions of the present disclosure are described in detail below with reference to the accompanying drawings and the specific embodiments.

[0026] The present disclosure relates to a gate voltage magnitude compensation equalization circuit for series operation of power switch transistors, and the schematic diagram of this circuit is shown in FIG. 1. S.sub.1, S.sub.2, . . . , S.sub.N-1, and S.sub.N in FIG. 1 represent power switch transistors. The gate voltage magnitude compensation equalization circuit for the series operation of the power switch transistors includes; N power switch transistors, N sampling units, N gate voltage magnitude compensation units, and N gate drive circuits, which are all in series operation, wherein the number N is a natural number greater than or equal to 2. Each of the power switch transistors is connected in parallel with a resistor-capacitor (RC) snubber circuit, and each of the power switch transistors corresponds to one sampling unit, one gate voltage magnitude compensation unit, and one gate drive circuit. Each of the sampling units samples current values of all the resistor-capacitor snubber circuits. Each of the gate voltage magnitude compensation units is connected to a corresponding sampling unit and obtains a sampling signal outputted by the corresponding sampling unit to obtain a current signal in direct proportion to a variation rate of an unbalanced voltage differential of a corresponding power switch transistor, and outputs the current signal to a gate drive circuit corresponding to the gate voltage magnitude compensation unit. Each of the gate drive circuits adds a compensation voltage into a gate voltage of the corresponding power switch transistor, and outputs the voltage obtained by adding the compensation voltage into the gate voltage to the corresponding power switch transistor.

[0027] Where the power switch transistors are insulation gate bipolar transistors (IGBTs), a schematic diagram showing a voltage equalization circuit implementing the series operation of a plurality of IGBTs is shown in FIG. 2. IGBT.sub.1, IGBT.sub.2, . . . , IGBT.sub.N-1, and IGBT.sub.N in FIG. 2 represent insulation gate bipolar transistors. Where the power switch transistors are SiC metal-oxide semiconductor field-effect transistors (SiC MOSFETs), a schematic diagram showing a voltage equalization circuit implementing the series operation of a plurality of SiC MOSFETs is shown in FIG. 3. MOS.sub.1, MOS.sub.2, . . . , MOS.sub.N-1, and MOS.sub.N in FIG. 3 represent SiC metal-oxide semiconductor field-effect transistors.

[0028] A schematic diagram showing a voltage equalization circuit implementing the series operation of two power switch transistors S.sub.1 and S.sub.2 according to an embodiment of the present disclosure is shown in FIG. 4. The gate voltage magnitude compensation equalization circuit for the series operation of the power switch transistors in this embodiment includes two series-connected SiC MOSFETs, and each of the SIC MOSFETs is connected in parallel with an RC snubber circuit. In this embodiment, a snubber resistor R.sub.s1 and a snubber capacitor C.sub.s1 form a first snubber circuit, and a snubber resistor R.sub.s2 and a snubber capacitor C.sub.s2 form a second snubber circuit, i.e., the remaining snubber circuit(s). The first SIC MOSFET (i.e., MOS.sub.1) is connected in parallel with the first snubber circuit, and the second SiC MOSFET (i.e., MOS.sub.2) is connected in parallel with the second snubber circuit.

[0029] In this embodiment, each of the sampling units includes two sampling inductors wound round the same magnetic ring, and the number of the sampling inductors is the same as that of the power switch transistors. A sampling inductor L.sub.p11 and a sampling inductor L.sub.p12 constitute a first sampling unit, and a sampling inductor L.sub.p21 and a sampling inductor L.sub.p22 constitute a second sampling unit. In the first sampling unit, L.sub.p11 represents the first sampling inductor, and L.sub.p12 represents the second sampling inductor, i.e., the remaining sampling inductor(s). In the second sampling unit, L.sub.p21 represents the first sampling inductor, and L.sub.p22 represents the second sampling inductor, i.e., the remaining sampling inductor(s). The sampling inductor L.sub.p11 and the sampling inductor L.sub.p21 are connected in series into the first RC snubber circuit to sample the buffer current of the first snubber circuit. That is, the first SiC MOSFET is sampled, i.e., a variation rate of a dynamic switching voltage of the MOS.sub.1. The sampling inductor L.sub.p12 and the sampling inductor L.sub.p22 are connected in series into the second snubber circuit to sample the buffer current of the second snubber circuit. That is, the second SiC MOSFET is sampled, i.e., a variation rate of a dynamic switching voltage of the MOS.sub.2. The number of turns of the first sampling inductor of the sampling unit is N−1=2−1=1 time that of the remaining sampling inductor(s) (where N represents the number of the power switch transistors). That is, the number of turns of the two sampling inductors is the same, which is equal to N.sub.1.

[0030] In this embodiment, each of the gate voltage magnitude compensation unit includes a drive voltage compensation inductor. In the first gate voltage magnitude compensation unit, the drive voltage compensation inductor L.sub.g1, the sampling inductor L.sub.p11, and the sampling inductor L.sub.p12 are wound round the same magnetic ring to form a coupling transformer. In the second gate voltage magnitude compensation unit, the drive voltage compensation inductor L.sub.g2, the sampling inductor L.sub.p21, and the sampling inductor L.sub.p22 are wound round another magnetic ring to form a coupling transformer. In the first gate voltage magnitude compensation unit, a coil winding direction of the drive voltage compensation inductor L.sub.g1 is the same as that of the sampling inductor L.sub.p11 but is opposite to that of the sampling inductor L.sub.p12. In the second gate voltage magnitude compensation unit, the coil winding direction of the drive voltage compensation inductor L.sub.g2 is the same as that of the sampling inductor L.sub.p22 but is opposite to that of the sampling inductor L.sub.p21. The number of turns of the drive voltage compensation inductor L.sub.g1 is the same as that of the drive voltage compensation inductor L.sub.g2, which is equal to N.sub.2. In this embodiment, the drive voltage compensation inductor and the two sampling inductors are wound round the same magnetic ring, such that components can be saved and costs can be reduced, but the present disclosure is not limited thereto. In other embodiments, the sampling inductors may separately sample by winding coils round another magnetic ring.

[0031] When the voltages of the two series-connected SiC MOSFETs change dynamically, the buffer current differential between the two RC snubber circuits is fed back to the gate voltage magnitude compensation units through the sampling inductors, and the drive voltage compensation inductors induce the induced currents in direction proportion to the current differential between the snubber circuits. The currents i.sub.Lg1 and i.sub.Lg2 flowing through the two drive voltage compensation inductors are separately as follows:

[00001]$\hspace{1em}\{\begin{array}{c}{i}_{\mathrm{Lg}1}=-\frac{N_1}{N_2}.Math.\left(i_{S1}-i_{S2}\right)\\ i_{\mathrm{Lg}2}=-\frac{N_1}{N_2}.Math.\left(i_{S2}-i_{S1}\right)\end{array}$

[0032] In this embodiment, each of the gate drive circuits includes a drive voltage source and two gate drive resistors connected in series. The first gate drive circuit includes a drive voltage source V.sub.g1 and gate drive resistors R.sub.g11 and R.sub.g12. The second gate drive circuit includes a drive voltage source V.sub.g2 and gate drive resistors R.sub.g21 and R.sub.g22. Two ends of the gate drive resistors R.sub.g12 and R.sub.g22 are respectively connected in parallel with the corresponding coupling transformers to introduce feedback signals, such that drive compensation voltages in direct proportion to the unbalanced voltage differential can be added into the gate voltages of the power switch transistors. In an embodiment, the drive voltage compensation inductor may be equivalent to a controlled current source, and the drive voltage compensation inductor L.sub.g1 is connected in parallel to the two ends of the drive resistor R.sub.g12 to generate a compensation voltage V.sub.com1. The drive voltage compensation inductor L.sub.g2 is connected in parallel to the two ends of the drive resistor R.sub.g22 to generate a compensation voltage V.sub.com2. The compensation voltage V.sub.com1 and the compensation voltage V.sub.com2 are respectively as follows:

[00002]$\hspace{1em}\{\begin{array}{c}{v}_{\mathrm{com}1}=-i_{\mathrm{Lg}1}{R}_{g2}=\frac{N_1}{N_2}{R}_{g12}.Math.\left(i_{S1}-i_{S2}\right)\\ v_{\mathrm{com}2}=-i_{\mathrm{Lg}2}{R}_{g2}=\frac{N_1}{N_2}{R}_{g22}.Math.\left(i_{S2}-i_{S1}\right)\end{array}$

[0033] The buffer current differentials of the snubber circuits reflects differentials among variation rates of the unbalanced voltage differentials in the dynamic process of a plurality of SiC MOSFET devices connected in series. Unbalanced voltage closed-loop control is implemented by compensating the differentials among the variation rates of the unbalanced voltage differentials to the gate drive signal of each SiC MOSFET through the drive voltage compensation inductors, such that voltage equalization is implemented.

[0034] The snubber circuit at the power-side of the circuit is connected in series with the coupling transformer, which may increase the parasitic inductance of the snubber circuit and have a negative effect on absorption characteristics of the snubber circuit. At the gate-side of the circuit, the coupling transformer output may be equivalent to a controlled current source, and thus the parasitic impedance of the loop only has a limited effect on the gate. Therefore, in order to reduce effects of non-ideal parameters, it is necessary to focus on reducing the parasitic inductance of the loop at the power-side. For the RC snubber circuit, an external current may charge or discharge a snubber capacitor when a device is turned on or off. The parasitic inductance existing in the actual RC circuit may hinder the variation of a charging current and partially offset the voltage equalization effect of the snubber circuit. Therefore, the parasitic inductance of the buffer circuit needs to be as small as possible.

[0035] For a device with two transistors connected in series, coupling inductance may exist between an upper-transistor snubber circuit loop and a lower-transistor snubber circuit loop. In an embodiment, the snubber circuit is arranged on a side of the power module, the snubber circuit of the first SiC MOSFET and the snubber circuit of the second SiC MOSFET are in an overlapped layout, and thus a loop coupling coefficient is relatively large. Meanwhile, because the currents of the snubber capacitors in the two snubber circuits are opposite in direction, this coupling inductance has an offset effect on the coupling inductance of the original loop. If the coupling coefficient of this coupling inductance is 1, the leakage inductance of the snubber circuit does not work at all. Therefore, in practical applications, the layout as shown in FIG. 5 may be used, and the coupling coefficients of the snubber circuits with two transistors connected in series are increased as much as possible.

[0036] To illustrate the effectiveness of the present disclosure, two ROHM's high-power SiC MOSFET devices (rated voltage 1200V, rated current 180 A, model BSM180D12P2E002) connected in series are taken as an example to perform experimental verification on the circuit voltage equalization method of the present disclosure. In this embodiment, resistors of 5Ω are selected as the snubber resistors R.sub.s1 and R.sub.s2 of the RC snubber circuits, and capacitors of 4.7 nF are selected as the snubber capacitors C.sub.s1 and C.sub.s2. resistors of 1.55Ω are selected as the drive resistors R.sub.g11 and R.sub.g21 of the gate drive circuits, and resistors of IQ are selected as the drive resistors R.sub.g12 and R.sub.g22. The drive voltage sources V.sub.g1 and V.sub.g2 are uniformly controlled by a global control circuit.

[0037] In an embodiment, when a bus voltage is 1300V and a load current is 200 A, series voltage test results are shown in FIG. 6. The abscissa in FIG. 6 represents time, the ordinate represents an magnitude of voltage or current, and the lower part of FIG. 6 is an enlarged schematic diagram of the circled portion in the upper part. The voltages corresponding to two switch transistors S.sub.1 and S.sub.2 are V.sub.ds1 and V.sub.ds2, respectively. In order to more intuitively reflect that the technical solutions of the present disclosure can ensure voltage equalization of the power switch transistors connected in series, voltage waves measured by the two switch transistors are stacked together, and waveforms of the current I.sub.ds are also superimposed. After testing, it is found that the voltage differential between the two SIC MOSFET devices connected in series is only about 2V, and the voltage equalization is still maintained after 10 switching cycles. That is, the voltage equalization has better stability. When the solution of this embodiment is not used, under the same test conditions, the voltage differential between the two series-connected SiC MOSFET devices is about 100V. In this way, it verifies the correctness and reliability of the gate voltage magnitude compensation equalization method for series operation of power switch transistors in the present disclosure.

[0038] In this embodiment, in the turn-off process of the SiC MOSFET devices, when a drain-source voltage V.sub.ds1 of the first SIC MOSFET (MOS.sub.1) is greater than a drain-source voltage V.sub.ds2 of the second SIC MOSFET (MOS.sub.2), a current i.sub.s1 of the snubber circuit is also greater than a current i.sub.s2 of the snubber circuit, and the current differential therebetween is compensated to gate drive signals of the two SiC MOSFETs through the coupling transformers, such that the magnitude of the drive signal of the first SiC MOSFET (MOS.sub.1) is slightly reduced, whereas the magnitude of the drive signal of the second SiC MOSFET (MOS.sub.2) slightly rises, and correspondingly a voltage rise rate of the first SiC MOSFET (MOS.sub.1) is slightly reduced, and the voltage rise rate of the second SiC MOSFET (MOS.sub.2) is slightly increased. In this way, the dynamic voltage equalization is implemented.

[0039] The above description of the embodiments is to facilitate those of ordinary skill in the art to understand and apply the present disclosure. Obviously, those skilled in the art can easily make various modifications to the above-mentioned embodiments, and apply the general principles described here to other embodiments without creative labor. Therefore, the present disclosure is not limited to the above-mentioned embodiments. Based on the disclosure of the present disclosure, all improvements and modifications made by those skilled in the art to the present disclosure should fall within the protection scope of the present disclosure.