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POWER CONVERTER

20210399642 · 2021-12-23

    Inventors

    Cpc classification

    International classification

    Abstract

    A power converter can include: N switching power stage circuits, where output terminals of the N switching power stage circuits are connected in parallel, and N is a positive integer; an energy storage element coupled between an input terminal and the output terminal of the power converter, where the energy storage element is configured to periodically store energy for delivery to the output terminal of the power converter; and where after a main transistor of an M-th switching power stage circuit is turned off, a main transistor of the (M+1)-th switching power stage circuit is turned on, in order to realize zero-voltage-switching (ZVS) of the main transistor of (M+1)-th switching power stage circuit, where M is a positive integer less than N.

    Claims

    1. A power converter, comprising: a) N switching power stage circuits, wherein output terminals of the N switching power stage circuits are connected in parallel, and N is a positive integer; b) an energy storage element coupled between an input terminal and the output terminal of the power converter, wherein the energy storage element is configured to periodically store energy for delivery to the output terminal of the power converter; and c) wherein after a main transistor of an M-th switching power stage circuit is turned off, a main transistor of the (M+1)-th switching power stage circuit is turned on, in order to realize zero-voltage-switching (ZVS) of the main transistor of (M+1)-th switching power stage circuit, wherein M is a positive integer less than N.

    2. The power converter of claim 1, wherein the main transistor of the (M+1)-th switching power stage circuit is controlled to be turned on after a controlled time has elapsed from the main transistor of the M-th switching power stage circuit being turned off in one switching cycle.

    3. The power converter of claim 2, wherein the length of the controlled time is adaptively adjusted to realize the ZVS of the main transistor of the (M+1)-th switching power stage circuit.

    4. The power converter of claim 3, wherein the controlled time is a dead time having a duration that is not greater than a freewheeling time of a current flowing through a parasitic inductor of the energy storage element.

    5. The power converter of claim 3, wherein the controlled time is a dead time having a duration that is not greater than a freewheeling time of a current flowing through an auxiliary inductor connected in series with the energy storage element.

    6. The power converter of claim 1, wherein after the main transistor of the M-th switching power stage circuit corresponding to the energy storage element is turned off, a current corresponding to the energy storage element freewheels through a body diode of the main transistor of the (M+1)-th switching power stage circuit, in order to realize the ZVS of the main transistor of the (M+1)-th switching power stage circuit.

    7. The power converter of claim 6, wherein the energy storage element is configured to periodically store energy for delivery to the output terminal of the power converter through the switching power stage circuit corresponding to the energy storage element.

    8. The power converter of claim 1, wherein a duty ratio of the main transistor in each switching power stage circuit is less than 1/N.

    9. The power converter of claim 1, wherein N switching power stage circuits are interleaved to alternately operate, and a phase difference between two adjacent switching power stage circuits is less than 360°/N.

    10. The power converter of claim 1, wherein the energy storage element is coupled with two different switching power stage circuits.

    11. The power converter of claim 10, wherein the energy storage element is coupled with the main transistors of two adjacent switching power stage circuits, and with the magnetic element of at least one of the N switching power stage circuits.

    Description

    BRIEF DESCRIPTION OF THE DRAWINGS

    [0004] FIG. 1 is a schematic block diagram of an example power converter.

    [0005] FIG. 2 is a waveform diagram of example operation of the power converter of FIG. 1.

    [0006] FIG. 3 is a schematic block diagram of a first example power converter, in accordance with embodiments of the present invention.

    [0007] FIG. 4 is a waveform diagram of example operation of the power converter in the first example, in accordance with embodiments of the present invention.

    [0008] FIG. 5 is a schematic block diagram of a second example power converter, in accordance with embodiments of the present invention.

    [0009] FIG. 6 is a schematic block diagram of a third example power converter, in accordance with embodiments of the present invention.

    [0010] FIG. 7 is a schematic block diagram of a fourth example power converter, in accordance with embodiments of the present invention.

    [0011] FIG. 8 is a schematic block diagram of a fifth example power converter, in accordance with embodiments of the present invention.

    [0012] FIG. 9 is a waveform diagram of example operation of the power converter in the fifth example, in accordance with embodiments of the present invention.

    [0013] FIG. 10 is a schematic block diagram of a sixth example power converter, in accordance with embodiments of the present invention.

    [0014] FIG. 11 is a schematic block diagram of a seventh example power converter, in accordance with embodiments of the present invention.

    DETAILED DESCRIPTION

    [0015] Reference may now be made in detail to particular embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention may be described in conjunction with the preferred embodiments, it may be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it may be readily apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, processes, components, structures, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention.

    [0016] With continuous societal development, the shortage of energy is becoming increasingly problematic. Power electronics technology has developed by leaps and bounds in recent years. At present, the high-gain power converter is an indispensable part of energy utilization. In some approaches, a cascade connection can be applied, in order to achieve high gain of the power converter. However, this can bring about a larger ripple in the output voltage and a larger output capacitor can be required.

    [0017] Referring now to FIG. 1, shown is a schematic block diagram of an example power converter. In this example, a power converter including two switching power stage circuits is shown. For example, the first switching power stage circuit can include transistor Q.sub.1, transistor Q.sub.SR1, and magnetic element L.sub.O1, which forms a buck converter. The second switching power stage circuit can include transistor Q.sub.2, transistor Q.sub.SR2, magnetic component L.sub.O2, and energy storage element C.sub.f. Energy storage element C.sub.f can connect between one power terminal of transistor Q.sub.2, and the common terminal of transistor Q.sub.SR2 and magnetic component L.sub.O2. In addition, the phase difference between the two switching power stage circuits can be configured as 180°, in order to alternately operate the two switching power stage circuits Moreover, the duty cycle of transistors Q.sub.1 and Q.sub.2 can be adjusted to adjust output voltage Vout of the power converter, thereby maintaining the stability of output voltage Vout.

    [0018] Referring now to FIG. 2, shown is a waveform diagram of example operation of the power converter. When control signal G.sub.1 is at a high level, transistors Q.sub.1 and Q.sub.SR2 can be turned on, and transistors Q.sub.2 and Q.sub.SR1 turned off. In this case, the current flowing through magnetic element L.sub.O1 can be increased, and the current flowing through magnetic element L.sub.O2 may be decreased. When control signal G.sub.2 is at a high level, transistors Q.sub.2 and Q.sub.SR1 can be turned on, and transistors Q.sub.1 and Q.sub.SR2 turned off. In this case, the current flowing through magnetic element L.sub.O1 can be decreased, and the current flowing through magnetic element L.sub.O2 may be increased. In this example, the ripple of the output voltage can be reduced, and the required output capacitor also reduced due to an interleaved parallel connection of the two switching power stage circuits and the phase-shifted control operation. Since the phase difference between control signals G.sub.1 and G.sub.2 can be 180° in order to alternately operate the two switching power stage circuits, each transistor in the power converter can be controlled by hard switching, which can cause larger losses.

    [0019] In particular embodiments, a power converter can include: N switching power stage circuits, where the output terminals of the N switching power stage circuits are connected in parallel and N is a positive integer; and an energy storage element coupled between the input terminal and the output terminal of the power converter. After the main transistor of the last switching power stage circuit is turned off, the main transistor of the next switching power stage circuit can be controlled to be turned on immediately, in order to realize zero-voltage-switching (ZVS) of the main transistor of the next switching power stage circuit. That is, after the main transistor of the M-th switching power stage circuit is turned off, the (M+1)-th switching power stage circuit can be turned on immediately after a controlled time in one switching cycle. For example, the controlled time is the dead time. Further, the length of the dead time can be adaptively adjusted according to system requirements. For example, the length of the dead time may not be greater than the freewheeling time of the current flowing through the parasitic inductor of the energy storage element, or not greater than the freewheeling time of the current flowing through the auxiliary inductor connected in series with the energy storage element.

    [0020] Referring now to FIG. 3, shown is a schematic block diagram of a first example power converter, in accordance with embodiments of the present invention. In this particular example, shown is a power converter including two switching power stage circuits. For example, the first switching power stage circuit can include transistor Q.sub.1, transistor Q.sub.SR1, and magnetic element L.sub.O1, which forms a buck converter. The second switching power stage circuit can include transistor Q.sub.2, transistor Q.sub.SR2, magnetic component L.sub.O2, and energy storage element C.sub.f. Energy storage element C.sub.f can connect between one power terminal of transistor Q.sub.2, and the common terminal of transistor Q.sub.SR2 and magnetic component L.sub.O2.

    [0021] In this example, inductor L.sub.stray is a parasitic inductor of energy storage element C.sub.f. In other examples, an auxiliary inductor connected in series with energy storage element C.sub.f can be applied in the switching power stage circuit, and the inductance value of the auxiliary inductor may be greater than that of parasitic inductor L.sub.stray, in order to increase the freewheeling time of the inductor current. In addition, inductor L.sub.stray can be a parasitic inductor of the wiring. For example, transistors Q.sub.SR1 and Q.sub.SR2 can be rectifying transistors (e.g., MOSFET, BJT, IGBT, etc.). In another example, transistors Q.sub.SR1 and Q.sub.SR2 can instead be diodes.

    [0022] Referring now to FIG. 4, shown is a waveform diagram of example operation of the power converter in the first example, in accordance with embodiments of the present invention. In this example, control signals G.sub.1 and G.sub.SR1 are complementary, and control signals G.sub.2 and G.sub.SR2 are complementary. Further, control signal G.sub.2 can become a high level after dead time T.sub.d has elapsed from control signal G.sub.1 going to a low level. When control signals G.sub.1 and G.sub.SR2 are at high levels, transistors Q.sub.1 and Q.sub.SR2 can be turned on, and transistors Q.sub.2 and Q.sub.SR1 turned off. In this case, energy storage element C.sub.f can be discharged to supply power for the first switching power stage circuit, and thus the current flowing through magnetic element L.sub.O1 can be increased and the current flowing through magnetic element L.sub.O2 decreased.

    [0023] After dead time T.sub.d from control signal G.sub.1 going low, when control signals G.sub.2 and G.sub.SR1 are both at high levels, transistors Q.sub.2 and Q.sub.SR1 can be turned on, and transistors Q.sub.1 and Q.sub.SR2 turned off. In this case, energy storage element C.sub.f can be charged by input voltage V.sub.in, and thus the current flowing through magnetic element L.sub.O1 may be decreased, and the current flowing through magnetic element L.sub.O2 increased. In this example, the ripple of the output voltage can be reduced and the required output capacitor also reduced due to the interleaved parallel connection of the two switching power stage circuits and the phase-shifted control operation. Moreover, since dead time T.sub.d can be set to avoid that the two switching power stage circuits being turned on at the same time and the time length of dead time T.sub.d is relatively short, the current flowing through the auxiliary inductor or parasitic inductor L.sub.stray can freewheel through the body diode of transistor Q.sub.2 after transistor Q.sub.1 has turned off. In that case, the voltage across the power terminals of transistor Q.sub.2 can be 0. When transistor Q.sub.1 is turned off, transistor Q.sub.2 may be turned on after dead time T.sub.d, in order to realize the zero-voltage-switching (ZVS) of transistor Q.sub.2.

    [0024] After the main transistor of the switching power stage circuit corresponding to energy storage element C.sub.f is turned off, the current flowing through the auxiliary inductor or parasitic inductor L.sub.stray may freewheel through the body diode of the main transistor of a next switching power stage circuit. Accordingly, the ZVS of the main transistor of the next switching power stage circuit can be realized by turning on the main transistor of the next switching power stage circuit after a dead time has elapsed. Here, energy storage element C.sub.f may periodically store energy and transmit the energy to the output of the power converter through the switching power stage circuit corresponding to energy storage element C.sub.f.

    [0025] It should be noted that since N switching power stage circuits are interleaved to alternately operate, the duty ratio of the main transistor of each switching power stage circuit can be less than 1/N in one cycle. In this example, after the main transistor of one switching power stage circuit has turned off, the current flowing through the auxiliary inductor or parasitic inductor L.sub.stray may freewheel through the body diode of the main transistor of a next switching power stage circuit. Therefore, the ZVS of the main transistor of the next switching power stage circuit can be realized by turning on the main transistor of the next switching power stage circuit after a dead time. In such a case, the phase difference between the two adjacent switching power stage circuits can be less than 360°/N.

    [0026] Referring now to FIG. 5, shown is a schematic block diagram of a second example power converter, in accordance with embodiments of the present invention. In this particular example transistor Q.sub.3 can connect between the input terminal of the power converter and transistor Q.sub.2, and energy storage element C.sub.f2 can connect between the common terminal of transistors Q.sub.2 and Q.sub.3 and one power terminal of transistor Q.sub.SR1 that is not connected with ground. It should understood that the number of energy storage elements can be adjusted in order to adjust a voltage conversion ratio of input voltage V.sub.in, and output voltage Vout. In this second example, the voltage conversion ratio of input voltage V.sub.in, and output voltage Vout can be different from that in the first example, and the principle of realizing the ZVS of the main transistor in the second example may be the same as that in the first example.

    [0027] The waveform diagram of the operation of the power converter in this second example is the same as that shown in FIG. 4. Referring back to FIG. 4, when control signals G.sub.1 and G.sub.SR2 are at high levels, transistors Q.sub.1, Q.sub.3, and Q.sub.SR2 can be turned on, and transistors Q.sub.2 and Q.sub.SR1 turned off. In this case, energy storage element C.sub.f1 can be discharged to supply power for the first switching power stage circuit, and magnetic element L.sub.O1 may be charged by input voltage V.sub.in, through transistor Q.sub.3 and energy storage element C. In addition, energy storage element C.sub.f2 can be charged by input voltage V.sub.in. Accordingly, the current flowing through magnetic element L.sub.O1 can be increased, and the current flowing through magnetic element L.sub.O2 decreased.

    [0028] After dead time T.sub.d has elapsed from control signal G.sub.1 going to a low level, when control signals G.sub.2 and G.sub.SR1 are both at high levels, transistors Q.sub.2 and Q.sub.SR1 can be turned on, and transistors Q.sub.1, Q.sub.3, and Q.sub.SR2 turned off. In this case, energy storage element C.sub.f2 can be discharged, and energy storage element C.sub.f1 may be charged. Also, energy storage element C.sub.f2 can be discharged to supply power for magnetic element L.sub.O2 through transistor Q.sub.SR1 and energy storage element C.sub.f1. Therefore, the current flowing through magnetic element L.sub.O1 can be decreased, and the current flowing through magnetic element L.sub.O2 increased. Similarly, the current flowing through the parasitic inductor (not shown in FIG. 5) of energy storage element C.sub.f1, and the current flowing through the parasitic inductor (not shown in FIG. 5) of energy storage element C.sub.f2 can freewheel through the body diode of transistor Q.sub.2 after transistors Q.sub.1 and Q.sub.3 are turned off. In that case, the voltage across the power terminals of transistor Q.sub.2 can be 0. When transistor Q.sub.1 is turned off, transistor Q.sub.2 may be turned on after dead time T.sub.d has elapsed, in order to realize the ZVS of transistor Q.sub.2.

    [0029] In this example, the duty ratio of the main transistors (e.g., transistors Q.sub.1 and Q.sub.2) is D, the voltage across energy storage element C.sub.f1 is VC.sub.f1, and the voltage across energy storage element C.sub.f2 is VC.sub.f2. The following formulas can be obtained: (Vin−VC.sub.f2)*D=Vout; VC.sub.f1*D=Vout; and (VC.sub.f2−VC.sub.f1)*D=Vout. Therefore, it can be obtained that VC.sub.f2=2/3Vin; and Vout=1/3Vin*D. It can be seen that the number of energy storage elements can be adjusted, in order to achieve a voltage conversion ratio that meets the requirements.

    [0030] Referring now to FIG. 6, shown is a schematic block diagram of a third example power converter, in accordance with embodiments of the present invention. In this particular example transistor Q.sub.4 can connect between the input terminal of the power converter, transistor Q.sub.3 can be included, and energy storage element C.sub.f3 can connect between the common terminal of transistors Q.sub.3 and Q.sub.4 and one power terminal (that is not connected to ground) of transistor Q.sub.SR2.

    [0031] Referring back to FIG. 4, which may also be applied to this third example. When control signals G.sub.1 and G.sub.SR2 are at high levels, transistors Q.sub.1, Q.sub.3, and Q.sub.SR2 can be turned on, and transistors Q.sub.4, Q.sub.2, and Q.sub.SR1 turned off. In this case, energy storage element C.sub.f1 can be discharged through transistors Q.sub.1 and Q.sub.SR2 to supply power for magnetic element L.sub.O1, and energy storage element C.sub.f3 can also be discharged to supply power for magnetic element L.sub.O1 at the same time. During this process, energy storage element C.sub.f2 can be charged, and energy storage elements C.sub.f1 and C.sub.f3 may be discharged. Accordingly, the current flowing through magnetic element L.sub.O1 can be increased, and the current flowing through magnetic element L.sub.O2 decreased.

    [0032] After dead time T.sub.d has elapsed from control signal G.sub.1 going to a low level, when control signals G.sub.2 and G.sub.SR1 are both at high levels, transistors Q.sub.4, Q.sub.2, and Q.sub.SR1 can be turned on, and transistors Q.sub.1, Q.sub.3, and Q.sub.SR2 turned off. In this case, energy storage element C.sub.f2 can be discharged through energy storage element C.sub.f1 and transistor Q.sub.SR1 to supply power for magnetic element L.sub.O2. In addition, input voltage V.sub.in, may supply power for magnetic element L.sub.O2 through transistor Q.sub.4 and energy storage element C.sub.f3. During this process, energy storage element C.sub.f2 can be discharged, and energy storage elements C.sub.f1 and C.sub.f3 may be charged. Accordingly, the current flowing through magnetic element L.sub.O1 can be decreased, and the current flowing through magnetic element L.sub.O2 increased.

    [0033] Similarly, after the transistors controlled by control signal G.sub.1 are turned off, the current flowing through the parasitic inductor of energy storage element C.sub.f1 and the current flowing through the parasitic inductor of energy storage element C.sub.f2 can freewheel through the body diode of transistor Q.sub.2. The current flowing through the parasitic inductor of energy storage element C.sub.f3 may freewheel through the body diode of transistor Q.sub.4. In that case, the voltage across the power terminals of transistor Q.sub.2 and the voltage across the power terminals of transistor Q.sub.4 may be 0. When transistors Q.sub.1 and Q.sub.3 are turned off, transistors Q.sub.2 and Q.sub.4 can be turned on after dead time T.sub.d has elapsed so as to realize the ZVS of transistors Q.sub.2 and Q.sub.4.

    [0034] In this example, similarly, the duty ratio of the main transistors (e.g., transistors Q.sub.1 and Q.sub.2) is D, the voltage across energy storage element C.sub.f1 is VC.sub.f1, the voltage across energy storage element C.sub.f2 is VC.sub.f2, and the voltage across energy storage element C.sub.f3 is VC.sub.f3. Therefore, the following formulas can be obtained: VC.sub.f3=3/4Vin; VC.sub.f1=1/4Vin; and Vout=1/4Vin*D. It should be understood that the number of energy storage elements may be adjusted in order to achieve a voltage conversion ratio of input voltage V.sub.in, and output voltage Vout that meets the requirements.

    [0035] Referring now to FIG. 7, shown is a schematic block diagram of a fourth example power converter, in accordance with embodiments of the present invention. In this particular example, a cross structure is shown, which aims to couple the energy storage element with two adjacent switching power stage circuits, and each energy storage element can connect between the corresponding main transistors of the two adjacent switching power stage circuits and with the magnetic element of at least one switching power stage circuit. In this example, transistors Q.sub.3 and Q.sub.4 can connect in series between the input terminal of the power converter and magnetic element L.sub.O2. Also, extra energy storage element C.sub.f2 can connect between the common terminal of transistors Q.sub.3 and Q.sub.4 and one power terminal (that is not connected to the ground) of transistor Q.sub.SR1.

    [0036] The waveform diagram of the operation of the fourth example power converter may be the same as that in the first example shown in FIG. 4. Referring back to FIG. 4, when control signals G.sub.1 and G.sub.SR2 are at high levels, transistors Q.sub.1, Q.sub.3, and Q.sub.SR2 can be turned on, and transistors Q.sub.2, Q.sub.4, and Q.sub.SR1 turned off. In this case, energy storage element C.sub.f1 can be discharged through transistor Q.sub.1 to supply power for magnetic element L.sub.O1. In addition, input voltage V.sub.in may supply power to magnetic element L.sub.O1 through energy storage element C.sub.f2 and transistor Q.sub.3. During this process, energy storage element C.sub.f2 may also be charged by input voltage V.sub.in. Accordingly, the current flowing through magnetic element L.sub.O1 can be increased, and the current flowing through magnetic element L.sub.O2 decreased.

    [0037] After dead time T.sub.d has elapsed from the falling edge of control signal G.sub.1, control signals G.sub.2 and G.sub.SR1 may both be at high levels, and then transistors Q.sub.2, Q.sub.4, and Q.sub.SR1 can be turned on, and transistors Q.sub.1, Q.sub.3, and Q.sub.SR2 turned off. In this case, energy storage element C.sub.f2 can be discharged, and energy storage element C.sub.f1 may be charged. For example, energy storage element C.sub.f2 can be discharged to supply power for magnetic element L.sub.O2 through transistors Q.sub.SR1 and Q.sub.4. Also, input voltage V.sub.in may supply power for magnetic element L.sub.O2 through transistor Q.sub.2 and energy storage element C.sub.f1 at the same time. Therefore, the current flowing through magnetic element L.sub.O1 can be decreased, and the current flowing through magnetic element L.sub.O2 increased.

    [0038] Similarly, after transistors Q.sub.1 and Q.sub.3 are turned off, the current flowing through the parasitic inductor (not shown in FIG. 7) of energy storage element C.sub.f1 may freewheel through the body diode of transistor Q.sub.2, and the voltage across the two power terminals of transistor Q.sub.2 can be zero. Also, the current flowing through the parasitic inductor (not shown in FIG. 7) of energy storage element C.sub.f2 may freewheel through the body diode of transistor Q.sub.4, and the voltage across the two power terminals of transistor Q.sub.4 can be zero. That is, when transistors Q.sub.1 and Q.sub.3 are turned off, transistors Q.sub.2 and Q.sub.4 may be turned on after dead time T.sub.d, in order to realize the ZVS of transistors Q.sub.2 and Q.sub.4.

    [0039] Referring now to FIG. 8, shown is a schematic block diagram of a fifth example power converter, in accordance with embodiments of the present invention. In this particular, the power converter can be extended to multi-phase applications, and the power converter may include four switching power stage circuits. In this example, a cross structure is shown, which aims to couple the energy storage element with two adjacent switching power stage circuits, and each energy storage element can connect between the main transistors of the two adjacent switching power stage circuits, and to the magnetic element of at least one switching power stage circuit.

    [0040] Referring now to FIG. 9, shown is a waveform diagram of an example operation of the power converter in the fifth example, in accordance with embodiments of the present invention. When control signals G.sub.1, G.sub.SR2, G.sub.SR3, and G.sub.SR4 are at high levels, transistors Q.sub.4, Q.sub.5, Q.sub.SR2, Q.sub.SR3, and Q.sub.SR4 can be turned on, and other transistors turned off. In this case, energy storage element C.sub.f1 can be discharged through transistor Q.sub.5 to supply power for magnetic element L.sub.O1. Also, input voltage V.sub.in, may supply power for magnetic element L.sub.O1 through transistor Q.sub.4 and energy storage element C.sub.f4 at the same time. Energy storage element C.sub.f4 may also be charged by input voltage V.sub.in, during this process. Therefore, current I1 flowing through magnetic element L.sub.O1 can be increased. Also, current I2 flowing through magnetic element L.sub.O2, current I3 flowing through magnetic element L.sub.O3, and current I4 flowing through magnetic element L.sub.O4 may be decreased.

    [0041] After a dead time T.sub.d has elapsed from control signal G.sub.1 going to a low level, when control signals G.sub.2, G.sub.SR1, G.sub.SR3, and G.sub.SR4 are at high levels, transistors Q.sub.1, Q.sub.6, Q.sub.SR1, Q.sub.SR3, and Q.sub.SR4 can be turned on and other transistors turned off. In this case, energy storage element C.sub.f2 may be discharged through transistor Q.sub.6 to supply power for magnetic element L.sub.O2. Also, input voltage V.sub.in, may supply power for magnetic element L.sub.O2 through transistor Q.sub.1 and energy storage element C.sub.f1, and energy storage element C.sub.f1 can be charged by input voltage V.sub.in, during this process. Therefore, current I2 flowing through magnetic element L.sub.O2 can be increased. Also, current I1 flowing through magnetic element L.sub.O1, current I3 flowing through magnetic element L.sub.O3, and current I4 flowing through magnetic element L.sub.O4 may be decreased.

    [0042] After dead time T.sub.d has elapsed from control signal G.sub.2 going to a low level, when control signals G.sub.3, G.sub.SR1, G.sub.SR2, and G.sub.SR4 are at high levels, the operation process of the power converter can be similar to the process mentioned above until one operation cycle ends. Similarly, the ZVS of the transistors controlled by control signals G.sub.2, G.sub.3, and G.sub.4 can be realized. In this example, control G.sub.1 may transition to be at a high level in a next switching cycle after control signal G.sub.4 transitions to be at a low level. Accordingly, transistor Q.sub.4 may not be turned on before the process during which the current flowing through parasitic inductor L.sub.stray (not shown in FIG. 9) of energy storage element C.sub.f4 freewheels through the body diode of transistor Q.sub.4 ends. Also, transistor Q.sub.5 may not be turned on before the process during which the current flowing through parasitic inductor L.sub.stray (not shown in FIG. 9) of energy storage element C.sub.f1 freewheels through the body diode of transistor Q.sub.5 ends. In this case, the ZVS of transistors Q.sub.4 and Q.sub.5 may not be realized. Therefore, only the ZVS of the transistors controlled by control signal G.sub.1 may not be realized, and the switching loss reduced for the multi-phase power converter.

    [0043] Referring now to FIG. 10, shown is a schematic block diagram of a sixth example power converter, in accordance with embodiments of the present invention. In this particular example, the power converter can be extended to multi-phase applications, and can include four switching power stage circuits. This example aims to couple the energy storage element with two different switching power stage circuits, and each energy storage element can connect between two main transistors of two different switching power stage circuits, and to the magnetic element of at least one switching power stage circuit.

    [0044] The waveform diagram of the operation of the power converter in this example can be the same as that shown in FIG. 9. Referring back to FIG. 9, when control signals G.sub.1, G.sub.SR2, G.sub.SR3, and G.sub.SR4 are at high levels, transistors Q.sub.1, Q.sub.SR2, Q.sub.SR3, and Q.sub.SR4 can be turned on, and other transistors are turned off. In this case, energy storage element C.sub.f1 can be discharged through transistors Q.sub.1 and Q.sub.SR2 to supply power for magnetic element L.sub.O1. Accordingly, current I1 flowing through magnetic element L.sub.O1 can be increased, and the currents flowing through other magnetic elements decreased.

    [0045] After dead time T.sub.d has elapsed from control signal G.sub.1 going to a low level, when control signals G.sub.2, G.sub.SR1, G.sub.SR3, and G.sub.SR4 are at high levels, transistors Q.sub.2, Q.sub.SR1, Q.sub.SR3, and Q.sub.SR4 can be turned on, and other transistors turned off. In this case, energy storage element C.sub.f2 can be discharged, energy storage element C.sub.f1 may be charged. For example, energy storage element C.sub.f2 can be discharged to supply power for magnetic element L.sub.O2 through transistor Q.sub.SR1 and energy storage element C.sub.f1. Accordingly, current I2 flowing through magnetic element L.sub.O2 can be increased, and the currents flowing through other magnetic elements decreased.

    [0046] After dead time T.sub.d has elapsed from control signal G.sub.2 going to a low level, when control signals G.sub.3, G.sub.SR1, G.sub.SR2, and G.sub.SR4 are at high levels, transistors Q.sub.3, Q.sub.SR1, Q.sub.SR2, and Q.sub.SR4 can be turned on, and other transistors turned off. In this case, energy storage element C.sub.f3 can be discharged, energy storage element C.sub.f2 may be charged. For example, energy storage element C.sub.f3 can be discharged to supply power for magnetic element L.sub.O3 through transistor Q.sub.SR4 and energy storage element C. Accordingly, current I3 flowing through magnetic element L.sub.O3 can be increased, and the currents flowing through other magnetic elements may be decreased.

    [0047] After dead time T.sub.d has elapsed from control signal G.sub.3 going to a low level, when control signals G.sub.4, G.sub.SR1, G.sub.SR2, and G.sub.SR3 are at high levels, transistors Q.sub.4, Q.sub.SR1, Q.sub.SR2, and Q.sub.SR3 can be turned on, and other transistors may be turned off. In this case, energy storage element C.sub.f3 can be charged. For example, input voltage V.sub.in, may supply power for magnetic element L.sub.O3 through transistor Q.sub.4 and energy storage element C.sub.f3. Accordingly, current I4 flowing through magnetic element L.sub.O4 can be increased, and the currents flowing through other magnetic elements may be decreased.

    [0048] In particular embodiments, after the main transistor of the last switching power stage circuit is turned off, the main transistor of the next switching power stage circuit can be turned off after the dead time has elapsed. Since the current flowing through the parasitic inductor of the energy storage element freewheels through the main transistor of the next switching power stage circuit, the voltage across the power terminals of the main transistor of the next switching power stage circuit may be zero, such that the ZVS of the main transistor of the next switching power stage circuit can be realized. Therefore, in this example, the ZVS of transistors Q.sub.2, Q.sub.3, and Q.sub.4 can be realized.

    [0049] Referring now to FIG. 11, shown is a schematic block diagram of a seventh example power converter, in accordance with embodiments of the present invention. In this particular example, each switching power stage circuit is a boost circuit and the operation process and principle is substantially similar to that in the first example above.

    [0050] The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with modifications as are suited to particular use(s) contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.