Semiconductor Structure and Method for Manufacturing the Same

Abstract

The present application provides a semiconductor structure and a method for manufacturing the same, which solves a problem that an existing semiconductor structure is difficult to deplete a carrier concentration of a channel under a gate to realize an enhancement mode device. The semiconductor structure includes: a channel layer and a barrier layer superimposed in sequence, wherein a gate region is defined on a surface of the barrier layer; a plurality of trenches formed in the gate region, wherein the plurality of trenches extend into the channel layer; and a P-type semiconductor material filling the plurality of trenches.

Claims

1. A semiconductor structure, comprising: a channel layer and a barrier layer superimposed in sequence; a plurality of trenches formed in a gate region of the barrier layer, wherein the plurality of trenches extend into the channel layer; and a P-type semiconductor material filling the plurality of trenches.

2. The semiconductor structure according to claim 1, wherein a material of the channel layer comprises GaN, and a material of the barrier layer comprises AlGaN.

3. The semiconductor structure according to claim 1, wherein the P-type semiconductor material comprises P-type GaN or P-type InGaN.

4. The semiconductor structure according to claim 1, further comprising: a dielectric layer superimposed on a surface of the barrier layer, wherein the dielectric layer covers the barrier layer.

5. The semiconductor structure according to claim 4, wherein a material of the dielectric layer comprises one or a combination of following materials: SiO.sub.2 and SiN.

6. The semiconductor structure according to claim 1, further comprising: a gate electrode located in a gate region above the barrier layer, a source electrode located in a source region above the barrier layer and a drain electrode located in a drain region above the barrier layer.

7. The semiconductor structure according to claim 1, further comprising: a nucleation layer and a buffer layer, located between a substrate and the channel layer.

8. The semiconductor structure according to claim 7, wherein the plurality of trenches extend into the buffer layer.

9. The semiconductor structure according to claim 1, wherein sidewalls of the plurality of trenches are perpendicular to an upper surface of the barrier layer.

10. The semiconductor structure according to claim 1, wherein sidewalls of the plurality of trenches are not perpendicular to an upper surface of the barrier layer.

11. The semiconductor structure according to claim 1, wherein the plurality of trenches are evenly arranged in the gate region.

12. The semiconductor structure according to claim 1, wherein the P-type semiconductor material partially fills a part of each of the plurality of trenches corresponding to the channel layer.

13. The semiconductor structure according to claim 1, wherein the P-type semiconductor material fills a part of each of the plurality of trenches corresponding to the channel layer.

14. The semiconductor structure according to claim 1, wherein the P-type semiconductor material fills a part of each of the plurality of trenches corresponding to the channel layer, and partially fills a part of each of the plurality of trenches corresponding to the barrier layer.

15. The semiconductor structure according to claim 1, wherein the P-type semiconductor material fills a part of each of the plurality of trenches corresponding to the channel layer, and fills a part of each of the plurality of trenches corresponding to the barrier layer.

16. The semiconductor structure according to claim 1, wherein an upper surface of the P-type semiconductor material is higher than an upper surface of the barrier layer.

17. A method for manufacturing a semiconductor structure, comprising: preparing a channel layer and a barrier layer superimposed in sequence; preparing a plurality of trenches extending into the channel layer in a gate region of the barrier layer; and filling the plurality of trenches with a P-type semiconductor material respectively.

18. The method for manufacturing a semiconductor structure according to claim 17, further comprising: preparing a dielectric layer on a surface of the barrier layer, wherein the dielectric layer covers the barrier layer.

19. The method for manufacturing a semiconductor structure according to claim 17, further comprising: preparing a gate electrode in a gate region above the barrier layer, a source electrode in a source region above the barrier layer and a drain electrode in a drain region above the barrier layer.

20. The method for manufacturing a semiconductor structure according to claim 17, further comprising: growing a nucleation layer and a buffer layer between a substrate and the channel layer.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0022] FIGS. 1a-1c, 2a-2e, 3a-3b, 4a-4b, 5a-5b, 6a-6e, 7a-7d, 8a-8c, 9a-9c, 10a-10c, 11a-11c, 12a-12d and 13a-13d are schematic diagrams of a semiconductor structure provided by an embodiment of the present application during a manufacturing process respectively.

[0023] FIG. 14 is a schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of the present application.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] The technical schemes of the present application will be described in detail below in combination with specific embodiments shown in the accompanying drawings. However, it cannot consider that these embodiments constitute a limitation to the scope of the present application. It should be noted that, and all these structural, method, or functional changes made by those of ordinary skill in the art according to these embodiments fall into the protection scope of the present application.

[0025] In addition, repeated reference numbers or labels may be used in different embodiments. These repetitions are only to describe the present application simply and clearly, and do not represent any correlation between the different embodiments and/or structures discussed.

[0026] An embodiment of the present application provides a method for manufacturing a semiconductor structure. As shown in FIG. 14, the method for manufacturing a semiconductor structure includes following contents.

[0027] Step 101: as shown in FIG. 1a, a channel layer 23 and a barrier layer 24 superimposed in sequence are prepared on a substrate 1.

[0028] The substrate 1 may be selected from semiconductor materials, ceramic materials, or polymer materials. For example, the substrate 1 is preferably selected from diamond, sapphire, silicon carbide, silicon, lithium niobate, silicon on insulator (SOI), gallium nitride, or aluminum nitride.

[0029] The channel layer 23 and the barrier layer 24 may be heterojunction semiconductor materials capable of forming two-dimensional electron gas. For example, taking a GaN-based material as an example, the channel layer 23 may be GaN, and the barrier layer 24 may be AlGaN. Due to the piezoelectric polarization effect, the channel layer 23 and the barrier layer 24 constitute a heterostructure to form a two-dimensional electron gas.

[0030] In an embodiment of the present application, as shown in FIG. 1b, before the channel layer 23 is grown, a nucleation layer 21 and a buffer layer 22 may be grown on the substrate 1 in sequence. Taking a GaN-based semiconductor structure as an example, the nucleation layer 21 can reduce dislocation density and defect density, and improve crystal quality. The nucleation layer 21 may be one or more of AlN, AlGaN, and GaN. The buffer layer 22 can buffer the stress in an epitaxial structure above the substrate and prevent the epitaxial structure from cracking. The buffer layer 22 may include one or more of AlN, GaN, AlGaN, and AlInGaN.

[0031] FIG. 1c is a top view of the semiconductor structure shown in FIG. 1a, and FIG. 1a is a cross-sectional view of the semiconductor structure shown in FIG. 1c along the B-B section line.

[0032] Step 102: a plurality of trenches 3 are prepared in a gate region of the barrier layer 24, and the trenches extend into the channel layer 23.

[0033] As shown in FIGS. 2a-2c, FIG. 2a is a top view of FIGS. 2b and 2c, FIG. 2b is a cross-sectional view of FIG. 2a along the B-B section line, and FIG. 2c is a cross-sectional view of FIG. 2a along the A-A section line.

[0034] The gate region in the present application is a region used to prepare a gate. A person of ordinary skill in the art should understand that the gate region can be defined and determined according to design requirements of related devices.

[0035] FIG. 2b is a cross-sectional view of the semiconductor structure shown in FIG. 2a along the B-B section line, and FIG. 2c is a cross-sectional view of the semiconductor structure shown in FIG. 2a along the A-A section line.

[0036] In the embodiment shown in FIG. 2a, a shape of the trench 3 viewing from top to bottom is rectangular, but the shape of the trench 3 viewing from top to bottom is not particularly limited in the present application. As shown in FIGS. 3a and 3b, the shape of the trench 3 viewing from top to bottom may be designed according to specific design requirements.

[0037] In the embodiment shown in FIGS. 2b and 2c, the cross-sectional shapes of the trench 3 along the B-B section line and the A-A section line shown in FIG. 2a are rectangular, respectively, but which are not particularly limited in the present application. As shown in FIGS. 4a and 4b, the shape of the trench 3 viewing from top to bottom may be determined according to specific design requirements.

[0038] In the embodiment shown in FIGS. 2b and 2c, sidewalls of the trench 3 are perpendicular to an upper surface of the barrier layer 24, but which are not particularly limited in the present application. In other embodiments, as shown in FIGS. 2d and 2e, the sidewalls of the trench 3 are not perpendicular to the upper surface of the barrier layer 24, and an angle between a sidewall of the trench 3 and the upper surface of the barrier layer 24 may be adjusted according to design requirements.

[0039] A depth of the trench 3 is shown in FIGS. 2a-2c, and the trench 3 extends into the channel layer 3. In other embodiments, as shown in FIGS. 5a and 5b, FIG. 5a corresponds to FIG. 2b, and FIG. 5b corresponds to FIG. 2c. When a buffer layer is provided, the trench 3 may also extend into the buffer layer 22. Of course, according to design requirements, the trench 3 may not extend into the buffer layer 22.

[0040] In the embodiment of the present application in FIGS. 2a-2c, the trenches 3 are evenly arranged in the gate region. The trench 3 may be formed by an etching process such as chlorine-based plasma etching. Of course, the width and spacing of the trench 3 are not strictly limited in the present application. The width and spacing of the trench 3 may be determined according to design requirements, and the two-dimensional electron gas may be depleted by cooperating the P-type semiconductor material 4 described below.

[0041] In the embodiment of FIGS. 2a-2c of the present application, the number of trenches 3 is 7. However, the present application is not limited thereto. The number of trenches 3 may be determined according to design requirements, and may be more or less, and the two-dimensional electron gas may be depleted by cooperating the depth, width, spacing of trench 3 and the P-type semiconductor material 4 described below.

[0042] Step 103: the trench 3 is filled with a P-type semiconductor material 4.

[0043] As shown in FIGS. 6a-6c, FIG. 6a is a top view of FIGS. 6b and 6c, FIG. 6b is a cross-sectional view of FIG. 6a along the B-B section line, and FIG. 6c is a cross-sectional view of FIG. 6a along the A-A section line.

[0044] The P-type semiconductor material 4 may be, for example, P-type GaN, P-type InGaN, or the like.

[0045] The filling of the trench 3 with the stress applying material 4 may be specifically achieved by directly filling the trench 3 in a selective filling manner, for example. As shown in FIG. 6d, which corresponds to FIG. 6b, a protective layer 25 may be prepared on the barrier layer 24 first, and then the trench 3 may be directly filled with the P-type semiconductor material 4. The protective layer 25 may be specifically, for example, SiN or SiO.sub.2 or a combination thereof. The filling of the trench 3 with the P-type semiconductor material 4 may be specifically achieved, for example, by selectively etching a full-wafer growth stress applying material 4. As shown in FIG. 6e, the stress applying material 4 is first grown on a full wafer, for example, the stress applying material 4 is first grown in the trenches 3 and on the upper surface of the barrier layer 24, and then selectively etched to form the structure shown in FIG. 6b.

[0046] In FIG. 6c, the P-type semiconductor material 4 may fill a part of the trench 3 corresponding to the channel layer 23. It should be understood that the filling depth of the P-type semiconductor material 4 in the trench 3 may be adjusted according to actual application scenarios. As shown in FIGS. 7a-7c, FIGS. 7a-7c correspond to FIG. 6c, and the difference is only that the filling depth of the P-type semiconductor material 4 in the trench 3 is different. As shown in FIG. 7a, the P-type semiconductor material 4 may only partially fill a part of the trench 3 corresponding to the channel layer 23; or as shown in FIG. 7b, the P-type semiconductor material 4 may fill the part of the trench 3 corresponding to the channel layer 23, while partially filling a part of the trench 3 corresponding to the barrier layer 24; or as shown in FIG. 7c, the P-type semiconductor material 4 may fill the part of the trench 3 corresponding to the channel layer 23, while filling a part of the trench 3 corresponding to the barrier layer 24. Since it is difficult to control the stress applying material 4 to fill the part of the trench 3 corresponding to the channel layer 23 and the barrier layer 24, an upper surface of the stress applying material 4 may also be slightly higher than an upper surface of the barrier layer 24, as shown in FIG. 7d.

[0047] Step 104: a dielectric layer 5 is prepared above the barrier layer 24.

[0048] As shown in FIGS. 8a-8c, FIG. 8a is a top view of FIGS. 8b and 8c, FIG. 8b is a cross-sectional view of FIG. 8a along the B-B section line, and FIG. 8c is a cross-sectional view of FIG. 8a along the A-A section line.

[0049] The material of the dielectric layer 5 may include one or a combination of following materials: SiO.sub.2 and SiN.

[0050] In FIG. 8c, the P-type semiconductor material 4 only fills the part of the trench 3 corresponding to the channel layer 23. The specific form of the dielectric layer 5 depends on the filling of the trench 3 with the P-type semiconductor material 4. As shown in FIGS. 9a-9c, FIGS. 9a-9c correspond to FIG. 8c. The difference between FIGS. 9a-9c and FIG. 8c is that as the filling depth of the P-type semiconductor material 4 in the trench 3 changes, the morphology of the dielectric layer 5 also changes.

[0051] Step 105: as shown in FIGS. 10a-10c, FIG. 10a is a top view of FIGS. 10b and 10c, FIG. 10b is a cross-sectional view of FIG. 10a along the B-B section line, and FIG. 10c is a cross-sectional view of FIG. 10a along the A-A section line. A gate electrode 7 is prepared in a gate region, a source electrode 6 is prepared in a source region, and a drain electrode 8 is prepared in a drain region.

[0052] The gate electrode may be directly prepared on the dielectric layer 5; before the source electrode 6 and the drain electrode 8 are prepared, the dielectric layer 5 in the source region and the drain region needs to be etched first, so that the source electrode 6 and the drain electrode 8 form ohmic contact with the barrier layer 24. An electrode material is made of a metal material such as a nickel alloy, and may also be made of a metal oxide or semiconductor material. The electrode material is not limited in the present application.

[0053] FIGS. 11a-11c correspond to FIG. 10c. The difference between FIGS. 11a-11c and FIG. 10c is that as the filling depth of the P-type semiconductor material 4 in the trench 3 changes, the morphology of the gate electrode 7 also changes.

[0054] FIGS. 12a-12c are related to the morphological changes of the gate electrode 7 in another embodiment. FIG. 12a is a top view of FIGS. 12b and 12c, FIG. 12b is a cross-sectional view of FIG. 12a along the B-B section line, and FIG. 12c is a cross-sectional view of FIG. 12a along the A-A section line. The difference between FIG. 12c and FIG. 10c is that a position corresponding to the trench 3 is not provided with a gate electrode.

[0055] In an embodiment of the present application, as shown in FIG. 12d, the gate may also be directly disposed on the P-type semiconductor material 4.

[0056] In an embodiment of the present application, step 104: preparing a dielectric layer 5 above the barrier layer 24, which can be omitted. As shown in FIG. 13a, the gate electrode 7 is prepared directly above the barrier layer 24. As shown in FIG. 13b, the gate electrode may only be provided on the barrier layer 24. Or as shown in FIG. 13c, when the filling depth of the P-type semiconductor 4 is relatively shallow, a cap layer 25 may be first prepared on the barrier layer 24, and then the gate electrode 7 is prepared. The cap layer 25 may be formed of a GaN-based semiconductor material. As shown in FIG. 13d, the gate electrode 7 may be directly prepared on the P-type semiconductor 4.

[0057] In an embodiment of the present application, a semiconductor structure is also provided. As shown in FIG. 1a, the semiconductor structure includes: a channel layer 23 and a barrier layer 24 superimposed in sequence on a substrate 1.

[0058] The substrate 1 may be selected from semiconductor materials, ceramic materials, or polymer materials. For example, the substrate 1 is preferably selected from diamond, sapphire, silicon carbide, silicon, lithium niobate, silicon on insulator (SOI), gallium nitride, or aluminum nitride. The channel layer 23 and the barrier layer 24 may be semiconductor materials capable of forming two-dimensional electron gas. For example, taking a GaN-based material as an example, the channel layer 23 may be GaN, and the barrier layer 24 may be AlGaN or GaN. The channel layer 23 and the barrier layer 24 constitute a heterostructure to form a two-dimensional electron gas.

[0059] In a further embodiment of the present application, in order to improve device performance and meet related technical requirements, as shown in FIG. 1b, the semiconductor structure may further include a nucleation layer 21 and a buffer layer 22 disposed under the channel layer 23. Taking a GaN-based semiconductor structure as an example, in order to reduce dislocation density and defect density, and improve crystal quality and other technical requirements, a nucleation layer 21 prepared on the substrate 1 may be further included. The nucleation layer 21 may be one or more of AlN, AlGaN, and GaN. In addition, in order to buffer the stress in an epitaxial structure above the substrate and prevent the epitaxial structure from cracking, the GaN-based semiconductor structure may further include a buffer layer 22 prepared above the nucleation layer 21. The buffer layer 22 may include one or more of GaN, AlGaN, and AlInGaN.

[0060] In an embodiment of the present application, as shown in FIGS. 2a-2c, the semiconductor structure further includes a plurality of trenches 3 formed in a gate region.

[0061] The trenches 3 extend into the channel layer 23. As shown in FIGS. 5a-5b, when the buffer layer 22 is provided, the trench 3 also extends into the buffer layer 22.

[0062] In an embodiment of the present application, as shown in FIGS. 6a-6c, the semiconductor structure further includes a P-type semiconductor material 4 filling the plurality of trenches 3.

[0063] In an embodiment of the present application, the material of the channel layer 23 may include GaN, the material of the barrier layer 24 may include AlGaN, and the material of the P-type semiconductor material 4 may include P-type GaN or P-type InGaN.

[0064] In an embodiment of the present application, as shown in FIGS. 8a-8c, the semiconductor structure may further include a dielectric layer 5, and the dielectric layer 5 is covered with a layer on the surface of the barrier layer. The material of the dielectric layer 5 may include one or a combination of the following materials: SiO.sub.2 and SiN.

[0065] In an embodiment of the present application, as shown in FIGS. 10a-10c, the semiconductor structure may further include a gate electrode 6 located in a gate region, a source electrode 7 located in a source region, and a drain electrode 8 located in a drain region.

[0066] The electrode material is made of a metal material such as a nickel alloy, and may also be made of a metal oxide or semiconductor material. The electrode material is not limited in the present application.

[0067] It should be understood that although this specification is described according to embodiments, not each embodiment only includes one independent technical solution. The way of describing is only for clarity purpose, and those skilled in the art should deem the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other embodiments that may be understood by those skilled in the art.

[0068] The series of detailed descriptions listed above are only specific descriptions of feasible embodiments of the present application. They are not intended to limit the protection scope of the present application. Any equivalent embodiments or modifications made within the technical spirit of the present application shall be included in the protection scope of the present application.