METHOD AND APPARATUS FOR THE POST-MANUFACTURING ADJUSTMENT OF THE CHARACTERISTIC IMPEDANCE OF PCB TRACES CARRYING HIGH-SPEED DATA SIGNALS

Abstract

A method for adjusting the value of the characteristic impedance Zo of a microstrip transmission line printed on an outer layer of a printed circuit board (PCB) comprises performing a post-manufacturing process directly on the artwork of a production PCB.

Claims

1. A method for adjusting the value of the characteristic impedance Zo of a microstrip transmission line printed on an outer layer of a printed circuit board (PCB), comprising performing a post-manufacturing process directly on the artwork of a production PCB.

2. A method according to claim 1, wherein the width of the microstrip is designed taking into account the tolerances of the copper-etching process, so to yield a production value of Zo which is larger than the target value.

3. A method according to claim 2, wherein the value of Zo on at least one sample out of a production lot of PCBs is measured, and then the microstrip trace on the PCB is coated with a suitable dielectric material of controlled thickness and width, and the value of Zo is corrected and measured, until Zo is reduced to the target value.

4. A method according to claim 3, wherein the dielectric material is a solder mask.

5. A method according to claim 2, wherein the value of Zo on at least one sample out of a production lot of PCBs is measured, and then the microstrip trace on the PCB is made wider by means of a controlled metal deposition so that the value of Zo is corrected and measured, until Zo is reduced to the target value.

6. A method according to claim 2, wherein correction procedures using dielectric material, and metal deposition, are applied to the same PCB.

7. A method according to claim 3, wherein the correction procedures are repeatedly applied to the same PCB so to iteratively refine the adjustment of the value of Zo.

8. A method according to claim 3, wherein the resulting dimensions of the controlled thickness and width of the dielectric material are set-up in a post-manufacturing correction process that can be applied to the whole production lot of PCBs.

9. A method according to claim 5, wherein the resulting dimensions of the controlled add-on width of the metal deposition are set-up in a post-manufacturing correction process that can be applied to the whole production lot of PCBs.

10. A method according to claim 7, where the correction parameters resulting from the correction procedures are set-up in a post-manufacturing correction process that can be applied to the whole production lot of PCBs.

11. A PCB comprising a microstrip trace which is coated with a material of controlled thickness and width, adapted to bring the value of Zo to a target value.

12. The PCB of claim 11, wherein the material of controlled thickness is a dielectric material.

13. The PCB of claim 12, wherein the dielectric material is a solder mask.

14. A PCB comprising a microstrip trace the width of which was adjusted by adding a controlled amount of material adapted to bring the value of Zo to a target value.

15. The PCB of claim 14, wherein the material a controlled amount of which was added is a deposed metal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In the drawings:

[0015] FIG. 1 is simplified schematic picture of a microstrip structure built on a PCB;

[0016] FIG. 2 is the data sheet of the PCB material Roger 1200, used in the illustrative embodiment;

[0017] FIG. 3 is a Flow-Chart describing the PCB production process;

[0018] FIG. 4 is a snapshot of the user interface of the simulation program developed by Polar Instruments Ltd., and used in the illustrative example;

[0019] FIG. 5 is a snapshot of the top layer of an exemplary PCB including microstrip traces;

[0020] FIG. 6 is a simulation of the dependence of the characteristic microstrip impedance Zo on the trace width W, used in the illustrative example;

[0021] FIG. 7 is an eye pattern of the illustrative example for the Zo=100Ω matched;

[0022] FIG. 8 is an eye pattern of the illustrative example for Zo=70Ω;

[0023] FIG. 9 is an eye pattern of the illustrative example for Zo=130Ω;

[0024] FIG. 10 is a plot of the insertion loss (IL) of the microstrip in the illustrative example;

[0025] FIG. 11 is a plot of the return loss (RL) of the microstrip in the illustrative example;

[0026] FIG. 12 is a plot of the jitter vs. Zo in a 4-PCM system;

[0027] FIG. 13 is the plot of the eye-opening amplitude vs. Zo in a 4-PCM system; and

[0028] FIG. 14 is the summary of an exemplary design process adapted to use the invention. After the basic Polar examination, deep simulations were conducted both in the Frequency and Time domain, in order to emphasize the impact on the performance of the Transmission Line Modelling (TLM).

[0029] The Frequency and Time domain simulations were conducted using Q3D, HFSS 3D Layout software tools.

DETAILED DESCRIPTION OF THE INVENTION

[0030] The invention addresses the two main disadvantages of the development approach currently employed in the industry: the investment in the design effort and prototyping cost required for refining the development by means of multiple PCB re-design cycles and multiple prototyping runs, and the consequent substantial delay in the completion of the development, resulting in a substantial increase in the time-to-market of new-developed products.

[0031] FIG. 5 shows the top layer of an exemplary PCB including microstrip traces. According to an embodiment of the invention, the width W of the microstrip traces is designed to be somewhat narrower than the design value corresponding to the optimal characteristic impedance Zo. The width W has to be designed narrow enough with respect to the average dimension that would result in production from an exact design, due the effect of the (statistically known) random tolerances of the copper-etching process, so that the actual value of Zo in the production PCBs will always turn out somewhat larger than the target value. Then, after running a production lot, the impedance Zo is measured, for example by means of a Time Domain Reflectometer (TDR), and corrected in one of the two following ways: the microstrip traces on one sample from the manufactured PCBs are either coated with a suitable dielectric material of controlled thickness and width, such as SM, or are made wider by means of a controlled Metal Deposition (MD) process, for instance, a Laser Metal Deposition (LMD). In either case the result is a controlled decrease in the value of the characteristic impedance. The correction process is repeatedly carried out and its result is checked until Zo reaches its optimal value. Then the resulting dimensions of the coating material, or the resulting add-on width of the MD, are set-up in a post-manufacturing line adapted to either performing coating or/and MD accordingly, so that the PCBs out of production may be corrected by means of an automatic post-production process, without requiring PCB redesign or additional prototyping. Since the deviation in the microstrip width W due to the copper-etching process remains fairly constant along the same production lot, the method subject of the invention results in a precise correction that yields the target value of Zo over the whole production lot of PCBs.

[0032] Hereinafter a brief description of the various stages required in order to carry out one design cycle and one prototyping run is described, and the skilled person will easily appreciate the substantial savings provided by the invention therefrom.

[0033] PCB Design Process

[0034] Most existing development processes proceed along the following lines: [0035] 1. Pick-up a suitable PCB material adapted to fulfill the requirements at the given operating frequency. Several materials can be used for the same purpose, and should be evaluated for suitable electrical and mechanical characteristics, as well as for cost. In the illustrative example, the base PCB material chosen was Roger 1200, which has a relative dielectric constant ε.sub.r=3.05, and whose data sheet is shown in FIG. 2; [0036] 2. Design the trace geometry of the various microstrips to accommodate the various impedance matching requirements; [0037] 3. Simulate the topology at pre-layout stage in order to validate the topology; [0038] 4. Build the topology with the cad tool and create a PCB design; [0039] 5. Perform a post layout simulation in order to validate the design before building the first prototype; [0040] 6. Manufacture of the first prototype of the PCB; [0041] 7. Validate the PCB under lab conditions and test the fully-assembled board functionality; [0042] 8. If any issue is found following the testing and measurements, perform a second round of layout corrections; [0043] 9. Perform a second round of post layout simulation in order to validate the layout corrections; [0044] 10. Manufacture of the second prototype based on the corrected PCB; [0045] 11. Validate the corrected PCB under lab conditions and test the fully-assembled board functionality; [0046] 12. If the validation of the corrected PCB is successful, then set-up the production line with the corrected design data and start production, else go back to step 8.

[0047] PCB Prototype Manufacturing Process

[0048] Most PCB prototype manufacturing runs require the following steps for each run: [0049] 1. The design group generates the PCB GERBER files (the files required to set-up the PCB manufacturing machinery) and hands them over to the engineering department; [0050] 2. The engineering department prepares the manufacturing documentation; [0051] 3. Production engineering prepares the multilayer PCB stack-up based on the row material in hand; [0052] 4. Production engineering prepares the copper layers for etching, by adding some thickness to the traces in order to compensate for the etching process and meet the impedance requirements; [0053] 5. Based on the GERBER files a photo resist process starts and coats the copper before the etching process, so only the coated traces are left; [0054] 6. The PCB panel enters the etching process and the traces reach their final thickness; [0055] 7. The above process is carried out for all PCB layers and then the circuit is laminated (In multi-layer boards, the layers of material are laminated (joined together) in a stack-up topology under extreme temperature and pressure); [0056] 8. Some additional processes, such as component symbols printing, are conducted to finalize the PCB.

[0057] FIG. 3 shows a Flow-Chart describing the above PCB production process

[0058] For clarity and ease of understanding, the method and apparatus of the invention will now be described with reference to an illustrative example. The computer program used for the design in the example is the “Polar” simulation of Polar Instruments Ltd., which is a commercial program used in actual product design, and the user interface of which is shown in FIG. 4.

[0059] The Scenario

[0060] In the following example, the tolerance of the copper-etching process used in production, is known to result in a microstrip width W that has a deviation ΔW of up to ±5% with respect to the target value Wo. When manufacturing a newly designed PCB, the deviation ΔW will remain fairly constant within the same production lot, however, the actual width W out of production is not known a-priori, and will be in the range 0.95Wo≤W≤1.05Wo. When manufacturing many unrelated production lots (i.e. at different times, with different machines, etc.), the deviation ΔW measured across different lots is a random variable which, for ease of understanding, is reasonably assumed to be uniformly distributed over the ±5% range with zero mean. Therefore, although each production lot will yield a different value of W (within the ±5% range), the average value of W over different production lots will be equal to the target value Wo. The present example assumes that the production line includes machinery capable to perform a LMD metal deposition process.

An Embodiment of the Invention

[0061] According to an embodiment of the invention, as applied to the present example, the design value Wdes of the microstrip width is set to be 5% below the target value Wo, namely Wdes=0.95Wo.

[0062] It follows from the above description, that the resulting width W out of a production lot will exhibit a width 0.95Wdes≤W≤1.05Wdes, from which, by substituting Wdes=0.95Wo it follows that 0.95(0.95Wo)≤W≤1.05(0.95Wo), namely, this will always obtain 0.9Wo<W<Wo. Then, in order to increase the value of W to the target value Wo (and therefore to reduce the characteristic impedance to the target value Zo), one should increase the width W of the microstrip by adding at most 10% width to the trace using a LMD process, which can be done in an iterative way, repetitively adding a small metal width to the trace, and then measuring the characteristic impedance Zo using, for instance, a TDR, until Zo reaches the target value. Then the value of the LMD add-on width, is set-up in the LMD post-manufacturing line, and the LMD process is carried out on the whole PCB production lot.

[0063] The Design

[0064] The dependency of the characteristic impedance Zo as a function on the trace width W is obtained, according to one embodiment of the invention, using the “Polar” simulation as shown in FIG. 6. The figure also shows the target trace width Wo≈7.2 [mil] corresponding to the target impedance Zo=100[Ω], and the design trace width Wdes≈6.8 [mil] whose value is 5% below Wo.

[0065] The Impact on System Performance

[0066] To better appreciate the substantial advantages of the invention, as shown in the illustrative example, it is assumed that the assembled PCB operates as part of an electro-optical system running data symbols through a microstrip at 53 Giga-Baud using 4-level PCM modulation, corresponding to a data rate of 106 Gbit/sec. The impedance of the load into which the microstrip should deliver the signal is fixed at the value Rload=100Ω.

[0067] The system performance is estimated using a 4-level “eye pattern”, which is a time-domain diagram in which a signal consisting of digital symbols, each of amplitude equal to one of 4 possible levels, is repetitively sampled on the load impedance Rload placed at the end of the microstrip, during consecutive time frames of identical duration, and the sampled values in each time frame, are superimposed and displayed on the vertical axis of the diagram, while the time sweep is triggered by the symbol rate, and displayed on the horizontal axis, which results in the “eye-like” picture. Several measurements on the eye pattern are used to estimate the probability of mistakenly recognizing the wrong level for a symbol value, thus decoding erroneous data. However, a general impression of the quality of the signal and the probability of error can be obtained by just looking at the shape of the eye. If the eye is “wide open”, as seen in the eye pattern of FIG. 7 where the microstrip impedance is Zo=100Ω, namely, is “matched” to the load impedance Rload=100Ω, there is only a small probability of decoding the wrong PCM level in presence of noise, because the 4 PCM levels are well separated. However, as the value of Zo deviates from the value of Rload, the eye becomes more and more “closed”, and the probability of decoding a wrong symbol increases, as seen in FIG. 8 and FIG. 9 where, to better emphasize the effect, the microstrip impedance has been substantially mismatched, setting Zo=70Ω and Zo=130Ω respectively.

[0068] In order to further illustrate how critical the effect of the microstrip impedance even for a moderate mismatch is, the Insertion Loss (IL) and the Return Loss (RL) for a microstrip terminated with Rload=100Ω are plotted as a function of the microstrip impedance, in FIG. 10 and in FIG. 11 respectively, for signals of frequency 12.5 GHz and 25 GHz. The IL is the power loss due to heat dissipation occurring because the conductivity of the metallic microstrip trace is finite, as well as because the dielectric constant of the dielectric layer has an imaginary part. The RL is the power loss due the mismatch between Zo and Rload, which causes part of the incident power to be reflected, so that not all the signal power reaches the load. FIG. 10 shows that, for a fixed frequency, the IL exhibits moderate variations of the order of 0.5 dB even under substantial mismatch, while FIG. 11 shows that RL exhibits extreme variations, of the order of 20 dB and more, as the value of Zo deviates even moderately from the value of Rload. A microstrip mismatch not only causes power losses, which degrade the signal-to-noise ratio, but also may produce phase distortion, which often results in an overall system degradation that cannot be corrected even by a substantial increase of signal power. Such phase distortion results in an uncertainty in the zero-crossing instant of the symbols, denoted as “jitter”. Although jitter may be partially compensated by means of Clock and Data Recovery (CDR) circuits, if it becomes comparable to symbol duration, it eventually results in incorrect sampling instants of the symbols. FIGS. 12 and 13 respectively, show the value of the jitter and the eye amplitude as a function of Zo in a 4-PCM system. Beside a low jitter, good operating conditions require also to simultaneously keep the eye pattern as “open” as possible. Looking at the eye amplitude shown in FIG. 13, and the jitter values shown in FIG. 12, it is apparent that fair eye opening and low jitter are simultaneously obtained only when the microstrip is well matched, namely close to Zo=100Ω.

[0069] FIG. 14 shows an exemplary case of a design process adapted to use the invention: [0070] a) First a preliminary ballpark design simulation, shown in the “original design” table, is carried out in order to determine reasonable ranges for the many parameters involved; [0071] b) Then, the design simulation is refined to meet the target value of Zo, as shown in the “coupon results” table under the “simulation” column. Then, a “coupon PCB” is built for testing purposes. A coupon PCB is a representative test PCB containing only the critical elements, in this case, just the microstrip. The impedance Zo on the coupon is tested using a TDR setup, and the measured value is shown under the column “TDR measurement”. The discrepancy in Zo value between the simulation and the manufactured coupon is shown under the column “impedance gap”. [0072] c) Finally, an actual PCB design is refined so that, in view of the impedance gap, the predicted outcome of the Zo value, shown under the column “simulation+gap,” yields an actual production value that can be corrected according to the invention.

[0073] All the above description and examples have been provided for the purpose of illustration and are not intended to limit the invention in any way, except as provided for in the appended claims. Many variations can be performed in embodiments of the invention. For instance, different solder masks and/or dielectric materials may be employed, alternative measurements can be used, leading to other parameters that can be used to estimate variations in the procedures, different deposition processes can be employed, all without exceeding the scope of the invention.