Structures and methods for RF de-embedding

Abstract

Electrical structures, methods, and computer program products for radio frequency (RF) de-embedding are provided. A structure includes a first test device, a first through structure corresponding to the first test device, and a first open structure corresponding to the first test device. The structure also includes a second test device having at least one different physical dimension than the first test device but otherwise identical to the first test device, a second through structure corresponding to the second test device, and a second open structure corresponding to the second test device. A method includes determining a first electrical parameter of the first test device in a first DUT structure and a second electrical parameter of the second test device in a second DUT structure based on measured electrical parameters of the first and the second DUT structures, through structures, and open structures.

Claims

1. A computer program product, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a computing device to cause the computing device to: measure first scattering parameters (S-parameters) of a first set of structures comprising a first device under test (DUT) structure; measure second S-parameters of a second set of structures comprising a second device under test (DUT) structure; determine a first electrical parameter of a first test device in the first DUT structure and a second electrical parameter of a modified version of the first test device in the second DUT structure based on a difference between results of calculations based on the first S-parameters and results of calculations based on the second S-parameters, wherein the first test device has a first length, the modified version of the first test device has a second length, and the second length is different than the first length.

2. The computer program product of claim 1, further comprising program instructions executable by the computing device to determine first admittance parameters (Y-parameters) of the first test device in the first DUT structure and second Y-parameters of the modified version of the first test device in the second DUT structure based on the first and the second S-parameters.

3. The computer program product of claim 1, further comprising program instructions executable by the computing device to: determine first admittance parameters (Y-parameters) of the first set of structures based on the first S-parameters; determine second Y-parameters of the second set of structures based on the second S-parameters; and determine the first and the second electrical parameters based on the first and the second Y-parameters.

4. The computer program product of claim 2, further comprising program instructions executable by the computing device to: determine open-corrected Y-parameters of the first and the second DUT structures and first and second through structures corresponding to the first and second DUT structures based on the first and the second Y-parameters; determine open-corrected impedance parameters (Z-parameters) of the first and the second through structures based on the open-corrected Y-parameters; and determine the first and the second electrical parameters based on the open-corrected Y-parameters and the open-corrected Z-parameters.

5. The computer program product of claim 4, further comprising program instructions executable by the computing device to: determine a difference between the open-corrected Z-parameters; and determine the first and the second electrical parameters based on the difference between the open-corrected Z-parameters.

6. The computer program product of claim 4, further comprising program instructions executable by the computing device to: determine a difference between admittances to ground in the first and the second through structures based on the open-corrected Z-parameters, wherein non-capacitive impedances to ground of padset parasitics in the first and the second through structures are approximated to a zero value; and determine the first and the second electrical parameters based on the difference between the admittances to ground.

7. The computer program product of claim 4, further comprising program instructions executable by the computing device to: determine a difference between admittances to ground in the first and the second through structures based on the open-corrected Z-parameters, wherein inductance parts of impedances to ground of padset parasitics in the first and the second through structures are approximated to a zero value; and determine the first and the second electrical parameters based on the difference between the admittances to ground.

8. The computer program product of claim 4, further comprising program instructions executable by the computing device to: determine a difference between impedances to ground in the first and the second through structures based on the open-corrected Z-parameters; and determine the first and the second electrical parameters based on the difference between the impedances to ground.

9. The computer program product of claim 1, wherein: the first test device comprises a first capacitor having a first length; and the modified version of the first test device comprises a second capacitor having a second length different than the first length but otherwise identical to the first capacitor.

10. The computer program product of claim 9, wherein: the first capacitor comprises a first vertical natural capacitor (VNCAP); and the second capacitor comprises a second vertical natural capacitor (VNCAP).

11. The computer program product of claim 10, wherein: the first VNCAP has a first width; and the second VNCAP has a second width equal to the first width.

12. A computer-implemented method, comprising: measuring, by a computer device, first scattering parameters (S-parameters) of a first set of structures comprising a first device under test (DUT) structure; measuring, by the computer device, second S-parameters of a second set of structures comprising a second device under test (DUT) structure; determining, by the computer device, a first electrical parameter of a first test device in the first DUT structure and a second electrical parameter of a modified version of the first test device in the second DUT structure based on a difference between the results of calculations based on the first S-parameters and results of calculations based on the second S-parameters, wherein the first test device has a first length, the modified version of the first test device has a second length, and the second length is different than the first length.

13. The computer-implemented method of claim 12, further comprising determining first admittance parameters (Y-parameters) of the first test device in the first DUT structure and second Y-parameters of the modified version of the first test device in the second DUT structure based on the first and the second S-parameters.

14. The computer-implemented method of claim 12, further comprising: determining first admittance parameters (Y-parameters) of the first set of structures based on the first S-parameters; determining second Y-parameters of the second set of structures based on the second S-parameters; and determining the first and the second electrical parameters based on the first and the second Y-parameters.

15. The computer-implemented method of claim 13, further comprising: determining open-corrected Y-parameters of the first and the second DUT structures and first and second through structures corresponding to the first and second DUT structures based on the first and the second Y-parameters; determining open-corrected impedance parameters (Z-parameters) of the first and the second through structures based on the open-corrected Y-parameters; and determining the first and the second electrical parameters based on the open-corrected Y-parameters and the open-corrected Z-parameters.

16. A system comprising: a processor, a computer readable memory, and a computer readable storage medium; program instructions to measure first scattering parameters (S-parameters) of a first set of structures comprising a first device under test (DUT) structure; program instructions to measure second S-parameters of a second set of structures comprising a second device under test (DUT) structure; program instructions to determine a first electrical parameter of a first test device in the first DUT structure and a second electrical parameter of a modified version of the first test device in the second DUT structure based on a difference between results of calculations based on the first S-parameters and results of calculations based on the second S-parameters, wherein the first test device has a first length, the modified version of the first test device has a second length, and the second length is different than the first length, and the program instructions are stored on the computer readable storage medium for execution by the processor via the computer readable memory.

17. The system of claim 16, further comprising: the first DUT structure; and the second DUT structure.

18. The system of claim 17, further comprising: a first through structure; a first open structure; a second through structure; and a second open structure.

19. The system of claim 16, further comprising program instructions to: determine first admittance parameters (Y-parameters) of the first test device in the first DUT structure; and determine second Y-parameters of the modified version of the first test device in the second DUT structure based on the first and the second S-parameters.

20. The system of claim 19, further comprising program instructions to: determine open-corrected Y-parameters of the first and the second DUT structures and first and second through structures based on the first and the second Y-parameters; determine open-corrected impedance parameters (Z-parameters) of the first and the second through structures based on the open-corrected Y-parameters; and determine the first and the second electrical parameters based on the open-corrected Y-parameters and the open-corrected Z-parameters.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

(1) The present invention is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present invention.

(2) FIG. 1 is an exemplary environment for implementing the steps in accordance with aspects of the invention;

(3) FIGS. 2A-2C are exemplary schematics of a first set of structures used for radio frequency (RF) de-embedding in accordance with aspects of the invention;

(4) FIGS. 3A-3C are exemplary schematics of a second set of structures used for the RF de-embedding in accordance with aspects of the invention;

(5) FIG. 4 is an exemplary schematic of a vertical natural capacitor (VNCAP) that may be characterized by the RF de-embedding in accordance with aspects of the present invention;

(6) FIG. 5 is an exemplary schematic of a core portion of a “through” structure used for the RF de-embedding in accordance with aspects of the present invention;

(7) FIGS. 6A-6B are exemplary schematics of a cross-sectional view of structures used for the RF de-embedding in accordance with aspects of the present invention;

(8) FIGS. 7A-7B are exemplary schematics of equivalent circuits of open-corrected impedance parameter (“Z-parameters”) matrices in accordance with aspects of the present invention;

(9) FIG. 8 is an exemplary schematic of an equivalent circuit of a difference matrix of the open-corrected Z-parameter matrices in accordance with aspects of the present invention;

(10) FIGS. 9A-9B are other exemplary schematics of equivalent circuits of the open-corrected Z-parameter matrices in accordance with aspects of the present invention;

(11) FIG. 9C is an exemplary schematic of an equivalent circuit of a difference between impedances to ground in the through structures in accordance with aspects of the present invention;

(12) FIGS. 10A-10B are other exemplary schematics of equivalent circuits of the open-corrected Z-parameter matrices in accordance with aspects of the present invention; and

(13) FIGS. 11A-11C are exemplary flow diagrams of methods for the RF de-embedding in accordance with aspects of the present invention.

DETAILED DESCRIPTION

(14) The invention relates to electrical structures and methods of use and, more particularly, to electrical structures, methods, and computer program products for radio frequency (RF) de-embedding. Specifically, the invention provides for using two “through” structures, each of the structures including two terminals connected by a piece of metal, to obtain characterization parameters of an RF, two-terminal device. In the RF de-embedding method of the invention, resistance in these through structures is not completely subtracted from measured RF parameters of two “Device Under Test (DUT)” structures. Advantageously, the invention leads to a more accurate characterization of the RF device, including obtaining a more accurate Quality factor (“Q factor”) of the device, for example. The invention is particularly suitable to the RF characterization of back-end-of-the-line (BEOL) devices.

System Environment

(15) As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.

(16) Any combination of one or more computer readable medium(s) may be utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

(17) A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

(18) Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

(19) Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).

(20) Aspects of the present invention are described below with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

(21) These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

(22) The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

(23) FIG. 1 is an exemplary environment 10 for implementing the steps in accordance with aspects of the invention. To this extent, the environment 10 includes a server or other computing system 12 that can perform the processes described herein. In particular, the server 12 includes a computing device 14. The computing device 14 can be resident on a network infrastructure or computing device of a third party service provider (any of which is generally represented in FIG. 1).

(24) The computing device 14 also includes a processor 20, memory 22A, an I/O interface 24, and a bus 26. The memory 22A can include local memory employed during actual execution of program code, bulk storage, and cache memories which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution. In addition, the computing device includes random access memory (RAM), a read-only memory (ROM), and an operating system (O/S).

(25) The computing device 14 is in communication with the external I/O device/resource 28 and a storage system 22B. For example, the I/O device 28 can comprise any device that enables an individual to interact with the computing device 14 (e.g., user interface) or any device that enables the computing device 14 to communicate with one or more other computing devices using any type of communications link. The external I/O device/resource 28 may be for example, a handheld device, PDA, handset, keyboard etc.

(26) In general, the processor 20 executes computer program code (e.g., program control 44), which can be stored in the memory 22A and/or storage system 22B. Moreover, in accordance with aspects of the invention, the program control 44 controls an RF de-embedding module 105, e.g., the process described herein. The RF de-embedding module 105 can be implemented as one or more program code in the program control 44 stored in memory 22A as separate or combined modules. Additionally, the RF de-embedding module 105 may be implemented as separate dedicated processors or a single or several processors to provide the function of these tools. While executing the computer program code, the processor 20 can read and/or write data to/from memory 22A, storage system 22B, and/or I/O interface 24. The program code executes the processes of the invention, for example, RF de-embedding or determining characterization parameters of a two-terminal device. The bus 26 provides a communications link between each of the components in the computing device 14.

(27) The computing device 14 can comprise any general purpose computing article of manufacture capable of executing computer program code installed thereon (e.g., a personal computer, server, etc.). However, it is understood that the computing device 14 is only representative of various possible equivalent-computing devices that may perform the processes described herein. To this extent, in embodiments, the functionality provided by the computing device 14 can be implemented by a computing article of manufacture that includes any combination of general and/or specific purpose hardware and/or computer program code. In each embodiment, the program code and hardware can be created using standard programming and engineering techniques, respectively.

(28) Similarly, the computing infrastructure 12 is only illustrative of various types of computer infrastructures for implementing the invention. For example, in embodiments, the server 12 comprises two or more computing devices (e.g., a server cluster) that communicate over any type of communications link, such as a network, a shared memory, or the like, to perform the process described herein. Further, while performing the processes described herein, one or more computing devices on the server 12 can communicate with one or more other computing devices external to the server 12 using any type of communications link. The communications link can comprise any combination of wired and/or wireless links; any combination of one or more types of networks (e.g., the Internet, a wide area network, a local area network, a virtual private network, etc.); and/or utilize any combination of transmission techniques and protocols.

(29) The RF de-embedding module 105 determines the characterization parameters of a two-terminal device by probing a first set of structures 110 and a second set of structures 115 including the device. The RF de-embedding module 105 measures scattering parameters (“S-parameters”), or other network parameters, of the first and the second sets of structures 110, 115. In the following Figures, reference will be made to S-parameter; however, those of skill in the art should understand that other network parameters may be measured in place of S-parameters without materially altering the disclosed RF de-embedding methodology of the present invention. Based on these measured S-parameters, the RF de-embedding module 105 may further determine other characterization parameters of the device, such as admittance parameters, and impedance parameters.

(30) FIGS. 2A-2C are exemplary schematics of a first set of structures (e.g., the first set of structures 110 in FIG. 1) used for the RF de-embedding in accordance with aspects of the invention. More specifically, in FIG. 2A, the first set of structures includes a DUT structure 200 including a first port 205 and a second port 210. In embodiments, the first and the second ports 205, 210 may be an input port and an output port, respectively, the input port receiving a voltage and the output port sending a voltage. A core portion 225A of the DUT structure 200 is not connected to ground portions 215, 220 through a resistive path.

(31) In embodiments, the first and the second ports 205, 210 may be connected to a capacitor 225 (or connected to a BEOL resistor, or connected to an inductor) in series. In the following descriptions, reference will be made to a capacitor; however, those of skill in the art should understand that other two-terminal devices, such as a BEOL resistor, an inductor, and a transformer, may be substituted for a capacitor without materially altering the disclosed RF de-embedding procedure. For example, the capacitor 225 may be a vertical natural capacitor (VNCAP) or any other RF, two-terminal capacitor known in the art. In embodiments, the first and the second ports 205, 210 may be connected in series to any other RF, two-terminal device known in the art. The capacitor 225 has a length l.sub.1 and may have a certain width.

(32) In FIG. 2B, the first set of structures also includes a “through” structure 230 including a first port 235 and a second port 240. In embodiments, the first and the second ports 235, 240 may be an input port and an output port, respectively. The input port receives a voltage, and the output port sends a voltage. A core portion 255 of the through structure 230 is not connected to ground portions 245, 250 through a resistive path.

(33) In embodiments, the first and the second ports 235, 240 may be connected to each other by a piece of metal at the core portion 255 of the through structure 230. The core portion 255 is at one BEOL metal level and has a predetermined width and a predetermined pattern. The core portion 255 further has a length L.sub.1, which may be determined by a sum of the length l.sub.1 of the capacitor 225 and a difference in length Δl between the core portion 255 and the capacitor 225. Here, the variable X.sub.1 is a length between an end of the core portion 255 and a surface of the first port 235, while the variable X.sub.2 is a length between another end of the core portion 255 and a surface of the second port 240.

(34) In addition, in FIG. 2C, the first set of structures includes an “open” structure 260 including a first port 265, a second port 270, and ground portions 275, 280. In the open structure 260, there is not a resistive path among the first port 265, the second port 270, and the ground portions 275, 280. In other words, there is an open circuit among the first port 265, the second port 270, and the ground portions 275, 280.

(35) FIGS. 3A-3C are exemplary schematics of a second set of structures (e.g., the second set of structures 115 in FIG. 1) used for the RF de-embedding in accordance with aspects of the invention. More specifically, in FIG. 3A, the second set of structures includes a DUT structure 300 including a first port 305 and a second port 310. In embodiments, the first and the second ports 305, 310 may be an input port and an output port, respectively, the input port receiving a voltage and the output port sending a voltage. A core portion 325A of the DUT structure 300 is not connected to ground portions 315, 320 through a resistive path.

(36) In embodiments, the first and the second ports 305, 310 may be connected to a capacitor 325 in series. For example, the capacitor 325 may be a vertical natural capacitor (VNCAP) or any other RF, two-terminal capacitor known in the art. In embodiments, the first and the second ports 305, 310 may be connected in series to any other RF, two-terminal device known in the art. The capacitor 325 has a length l.sub.2 and may have a certain width. In other words, the capacitor 325 has a different length than the length l.sub.1 of the capacitor 225 of the first DUT structure 200, but may have a same or different width than the width of the capacitor 225.

(37) In FIG. 3B, the second set of structures also includes a “through” structure 330 including a first port 335 and a second port 340. In embodiments, the first and the second ports 335, 340 may be an input port and an output port, respectively. The input port receives a voltage, and the output port sends a voltage. A core portion 355 of the through structure 330 is not connected to ground portions 345, 350 through a resistive path.

(38) In embodiments, the first and the second ports 335, 340 may be connected to each other by a piece of metal at the core portion 355 of the through structure 330. The core portion 355 is at one BEOL metal level and has a predetermined width and a predetermined pattern. These predetermined values for the core portion 355 are the same as those for the core portion 255 of the first through structure 230. The core portion 355 further has a length L.sub.2, which may be determined by a sum of the length l.sub.2 of the capacitor 325 and a difference in length Δl between the core portion 355 and the capacitor 325. That is, the core portion 355 has a different length than the length L.sub.1 of the core portion 255 of the first through structure 230. Here, the variable X.sub.1 is a length between an end of the core portion 355 and a surface of the first port 335, while the variable X.sub.2 is a length between another end of the core portion 355 and a surface of the second port 340.

(39) In addition, in FIG. 3C, the second set of structures includes an “open” structure 360 including a first port 365, a second port 370, and ground portions 375, 380. In the open structure 360, there is not a resistive path among the first port 365, the second port 370, and the ground portions 375, 380. In other words, there is an open circuit among the first port 365, the second port 370, and the ground portions 375, 380.

(40) FIG. 4 is an exemplary schematic of a vertical natural capacitor (VNCAP) 400 that may be characterized by the RF de-embedding in accordance with aspects of the present invention. Specifically, the schematic is a top view of the VNCAP 400. The VNCAP 400 may be connected in series to ports of one of two DUT structures (e.g., the ports 205, 210 of the DUT structure 200, or the ports 305, 310 of the DUT structure 300, in FIGS. 2A and 3A). To characterize a quality factor Q of a given VNCAP layout, there can be different definitions of a characterized device range. The different definitions of the characterized device range lead to different Q values for the same device. For example, one definition of a characterized device range of the given VNCAP 400 has a core portion 415 only with a length l. Another definition of a characterized device range of the same VNCAP 400 has a length L 410, which includes the same core portion 415 plus two segments of wiring out lines. Due to an additional resistance in the two segments of wiring out lines, an effective impedance in the 2.sup.nd definition of the VNCAP size is larger than that in the 1.sup.st definition of the VNCAP range. Thus, the quality factor Q(L) associated with the 2.sup.nd definition of the device size is smaller than the quality factor Q(l) associated with the 1.sup.st definition of the device size, Q(L)<Q(l).

(41) FIG. 5 is an exemplary schematic of a core portion 500 of a through structure used for the RF de-embedding in accordance with aspects of the present invention. The core portion 500 may be connected in series to ports of one of two through structures (e.g., the ports 235, 240 of the through structure 230, or the ports 335, 340 of the DUT structure 330, in FIGS. 2B and 3B). In embodiments, the core portion 500 may have a width w (e.g., 1 micron) that is the same as widths of portions of the through structure connected to the core portion 500. The core portion 500 may also have a length 505 represented at reference l in FIG. 5 (e.g., 10 microns). The core portion 500 provides an accurate correction of resistance in the core portion 500 of the through structure.

(42) FIGS. 6A-6B are exemplary schematics of a cross-sectional view of structures 600, 630 used for RF de-embedding in accordance with aspects of the present invention. For instance, the structure 600 may include any one of the structures 200, 230, and 260 in FIGS. 2A-2C, while the structure 630 may include any one of the corresponding structures 300, 330, and 360 in FIGS. 3A-3C. In FIG. 6A, the structure 600 includes a first port 605 or signal pad, a second port 610 or signal pad, and a core portion 615 having a length L.sub.1. A length between a center of the first port 605 and a center of the second port 610 is (x.sub.1+L.sub.1+x.sub.2). The first and the second ports 605, 610 are in contact with tips of probes 620, 625, respectively. The probes 620, 625 are operable to transfer voltages between the first and the second ports 605, 610, and to a RF de-embedding module (e.g., the RF de-embedding module 105 in FIG. 1).

(43) In FIG. 6B, the structure 630 includes a first port 635 or signal pad, a second port 640 or signal pad, and a core portion 645 having a length L.sub.2 that is different than the length L.sub.1 of the core portion 615 of the structure 600. A length between a center of the first port 635 and a center of the second port 640 is (x.sub.1+L.sub.2+x.sub.2), which is also different than the length (x.sub.1+L.sub.1+x.sub.2) between the centers of the ports 605, 610 of the structure 600. The first and the second ports 635, 640 are in contact with tips of probes 650, 655, respectively. The probes 650, 655 are operable to transfer voltages between the first and the second ports 635, 640, and to a RF de-embedding module (e.g., the RF de-embedding module 105 in FIG. 1).

(44) In these structures 600, 630, an impedance of a non-core (e.g., x.sub.1+x.sub.2) portion of the structure 600 is about the same as an impedance of a non-core portion of the structure 630. Accordingly, for measurement efficiency, the probes 620, 625 of the structure 600 may be placed a same distance apart as the probes 650, 655 of the structure 630, for example, the distance [x.sub.1+1/2(L.sub.1+L.sub.2)+x.sub.2], even though the lengths L.sub.1 and L.sub.2 are different.

(45) Using the first and the second sets of structures in FIGS. 2-3, the invention provides for RF de-embedding of the capacitor 225, the capacitor 325, and/or any other RF, two-terminal device known in the art that are placed in the sets of structures. More specifically, for the capacitor 225, the RF de-embedding module 105 measures three separate 2×2 S-parameter matrices S.sub.dut1, S.sub.through1, and S.sub.open1 utilizing the DUT structure 200, the through structure 230, and the open structure 260, respectively. For example, the S-parameter matrix S.sub.dut1 may be given by:

(46) $\begin{array}{cc}{S}_{\mathrm{dut}1}=\left(\begin{array}{cc}{S}_{11}& S_{12}\\ S_{21}& S_{22}\end{array}\right),& \left(1\right)\end{array}$
where S.sub.11 is a voltage reflection coefficient of the input port 205, S.sub.12 is a reverse voltage gain, S.sub.21 is a forward voltage gain, and S.sub.22 is a voltage reflection coefficient of the output port 210.

(47) The RF de-embedding module 105 then determines three separate 2×2 admittance parameter (“Y-parameter”) matrices Y.sub.dut1, Y.sub.through1, and Y.sub.open1 that correspond to the matrices S.sub.dut1, S.sub.through1, and S.sub.open1, respectively. For the capacitor 325, the RF de-embedding module 105 measures three separate 2×2 S-parameter matrices S.sub.dut2, S.sub.through2, and S.sub.open2 utilizing the DUT structure 300, the through structure 330, and the open structure 360, respectively. The RF de-embedding module 105 then determines three separate 2×2 Y-parameter matrices Y.sub.dut2, Y.sub.through2, and Y.sub.open2 that correspond to the matrices S.sub.dut2, S.sub.through2, and S.sub.open2, respectively.

(48) Next, the RF de-embedding module 105 subtracts admittances of “parallel” components (e.g., the first and second ports) from the admittance of each of the DUT structures 200, 300 and the through structures 230, 330. This is accomplished by subtracting the admittance of the open structure 260 from the DUT structure 200 and the through structure 230, and subtracting the admittance of the open structure 360 from the DUT structure 300 and the through structure 330. As a result, the following open-corrected Y-parameter matrices Y.sup.do1, Y.sup.to1, Y.sup.do2, and Y.sup.to2 are determined based on the following equations:
Y.sup.do1=Y.sub.dut1−Y.sub.open1;   (2a)
Y.sup.to1=Y.sub.through1−Y.sub.open1;   (2b)
Y.sup.do2=Y.sub.dut2−Y.sub.open2; and   (2c)
Y.sup.to2=Y.sup.through2−Y.sub.open2.   (2d)

(49) Using the open-corrected Y-parameter matrices Y.sup.to1 and Y.sup.to2, the RF de-embedding module 105 determines open-corrected impedance parameter (“Z-parameters”) matrices Z.sup.to1 and Z.sup.to2 of the through structures 230, 330 based on the following equations:

(50) $\begin{array}{cc}{Z}^{\mathrm{to}1}\equiv {\left(Y^{\mathrm{to}1}\right)}^{-1}=\left(\begin{array}{cc}{Z}_{11}^{\mathrm{to}1}& Z_{12}^{\mathrm{to}1}\\ Z_{21}^{\mathrm{to}1}& Z_{22}^{\mathrm{to}1}\end{array}\right);\mathrm{and}& \left(3a\right)\\ Z^{\mathrm{to}2}\equiv {\left(Y^{\mathrm{to}2}\right)}^{-1}=\left(\begin{array}{cc}{Z}_{11}^{\mathrm{to}2}& Z_{12}^{\mathrm{to}2}\\ Z_{21}^{\mathrm{to}2}& Z_{22}^{\mathrm{to}2}\end{array}\right).& \left(3b\right)\end{array}$

(51) FIGS. 7A-7B are exemplary schematics of equivalent circuits 700, 725 of the open-corrected Z-parameter matrices in accordance with aspects of the present invention. Specifically, in FIG. 7A, the circuit 700 is the equivalent circuit of the open-corrected Z-parameter matrix Z.sup.to1 for the through structure 230, which may be denoted as follows:

(52) $\begin{array}{cc}{Z}^{\mathrm{to}1}\equiv {\left(Y^{\mathrm{to}1}\right)}^{-1}=\left(\begin{array}{cc}{Z}_{L1}+Z_{L3}& Z_{L3}\\ Z_{L3}& Z_{L2}+Z_{L3}\end{array}\right)& \left(4a\right)\end{array}$
where Z.sub.L1 is an impedance of the first port 235, Z.sub.L2 is the impedance of the second port 240, and Z.sub.L3 is an impedance to the ground portions 245, 250 in the through structure 230.

(53) The equivalent circuit 700 includes a resistor-inductor, series-connected pair 705 (e.g., the first port 235) having the impedance Z.sub.L1, and a resistor-inductor, series-connected pair 710 (e.g., the second port 240) having the impedance Z.sub.L2. The equivalent circuit 700 also includes a capacitor 715 (e.g., the capacitance to ground of an internal through structure device) having an impedance Z.sub.c3, and a resistor-inductor, series-connected pair 720 (e.g., a padset parasitic) having an impedance to ground Z.sub.p3. The impedance Z.sub.c3 is equal to an inverse of an admittance Y.sub.c3, of the capacitor 715. The impedance to ground Z.sub.L3 in the through structure 230 is equal to the sum of the impedance Z.sub.c3 of the capacitor 715 and the impedance to ground Z.sub.p3 of the resistor-inductor pair 720. An impedance from the first port 235 to the second port 240 of the through structure 230, with resistance and inductance at a low frequency, is (Z.sub.L1+Z.sub.L2)=(Z.sub.11.sup.to1+Z.sub.22.sup.to1−Z.sub.21.sup.to1−Z.sub.12.sup.to1).

(54) In FIG. 7B, the circuit 725 is the equivalent circuit of the open-corrected Z-parameter matrix Z.sup.to2 for the through structure 330, which may be denoted as follows:

(55) $\begin{array}{cc}{Z}^{\mathrm{to}2}\equiv {\left(Y^{\mathrm{to}2}\right)}^{-1}=\left(\begin{array}{cc}{Z}_{L1}+\delta z_1+Z_{L4}& Z_{L4}\\ Z_{L4}& Z_{L2}+\delta z_2+Z_{L4}\end{array}\right)& \left(4b\right)\end{array}$
where (Z.sub.L1+δ.sub.Z1) is an impedance of the first port 335, (Z.sub.L2+δ.sub.Z2) is the impedance of the second port 340, and Z.sub.L4 is an impedance to the ground portions 345, 350 in the through structure 330.

(56) The equivalent circuit 725 includes a resistor-inductor, series-connected pair 730 (e.g., the first port 335) having the impedance (Z.sub.L1+δ.sub.Z1), and a resistor-inductor, series-connected pair 735 (e.g., the second port 340) having the impedance (Z.sub.L2+δ.sub.Z2). The equivalent circuit 725 also includes a capacitor 740 (e.g., the capacitance to ground of an internal through structure device) having an impedance Z.sub.c4, and a resistor-inductor, series-connected pair 745 (e.g., a padset parasitic) having an impedance to ground Z.sub.p4. The impedance Z.sub.c4 is equal to an inverse of an admittance Y.sub.c4, of the capacitor 740. The admittance Y.sub.c4 of the capacitor 740 is equal to a sum of the admittance Y.sub.c3 of the capacitor 715 and a difference Δy of the two admittances Y.sub.c4 and Y.sub.c3. The impedance to ground Z.sub.L4 in the through structure 330 is equal to the sum of the impedance Z.sub.c4 of the capacitor 740 and the impedance to ground Z.sub.p4 of the resistor-inductor pair 745. An impedance from the first port 335 to the second port 340 of the through structure 330, with resistance and inductance at a low frequency, is (Z.sub.L1+δ.sub.Z.sub.1+Z.sub.L2+δ.sub.Z.sub.2)=(Z.sub.11.sup.to2+Z.sub.22.sup.to2−Z.sub.21.sup.to2−Z.sub.12.sup.to2).

(57) In order to further de-embed the open-corrected Y-parameter matrices Y.sup.do1 and Y.sup.do2 of the DUT structures 200, 300, the open-corrected Z-parameter matrices Z.sup.to1 and Z.sup.to2 for the through structure 230, 330 need to be subtracted from open-corrected Z-parameter matrices of the DUT structures 200, 300. This subtraction unambiguously removes padset parasitics from the measurement of the DUT structures 200, 300, since the open-corrected Z-parameter matrices of the DUT structures 200, 300 includes a series combination of impedances of the padset parasitics and of internal DUT structure devices. However, in order to avoid subtracting internal impedances (i.e., impedances of the core portions 255 and 355) of the through structures 230, 330, internal impedance matrices of the through structures 230, 330 (“impedance corrections”) must be determined and added back into the de-embedded, open-corrected Y-parameter matrices Y.sup.do1 and Y.sup.do2 of the DUT structures 200, 300.

(58) Accordingly, to determine the impedance corrections and using the open-corrected Z-parameter matrices Z.sup.to1 and Z.sup.to2 of the through structures 230, 330, the RF de-embedding module 105 determines a difference matrix Δz between these Z-parameter matrices Z.sup.to1 and Z.sup.to2 based on the following equation:

(59) $\begin{array}{cc}\Delta z\equiv \left(\begin{array}{cc}\Delta z_{11}& \Delta z_{12}\\ \Delta z_{21}& \Delta z_{22}\end{array}\right)=Z^{\mathrm{to}2}-Z^{\mathrm{to}1}.& \left(5\right)\end{array}$

(60) FIG. 8 is an exemplary schematic of equivalent circuit 800 of the difference matrix between the open-corrected Z-parameter matrices in accordance with aspects of the present invention. Specifically, the circuit 800 is the equivalent circuit of the difference matrix Δz between the open-corrected Z-parameter matrices Z.sup.to1 and Z.sup.to2, which is found from Eqs. (5), (4a), and (4b) to be:

(61) $\begin{array}{cc}\Delta z=Z^{\mathrm{to}2}-Z^{\mathrm{to}1}=\left(\begin{array}{cc}\delta z_1+Z_{L4}-Z_{L3}& Z_{L4}-Z_{L3}\\ Z_{L4}-Z_{L3}& \delta z_2+Z_{L4}-Z_{L3}\end{array}\right).& \left(6\right)\end{array}$

(62) The equivalent circuit 800 includes a resistor-inductor, series-connected pair 805 having a difference impedance δ.sub.Z1, a resistor-inductor, series-connected pair 810 having a difference impedance δ.sub.Z2, and a resistor-inductor, series-connected pair 815 having an impedance to ground (Z.sub.L4−Z.sub.L3). A difference between the impedances of the through structures 230, 330 is thus obtained from the difference matrix Δz and is equal to (δ.sub.Z1+δ.sub.Z2)=(Δ.sub.z11+Δ.sub.z22−Δ.sub.z21−Δ.sub.z12). An impedance difference per unit length δ.sub.Z is given by:

(63) $\begin{array}{cc}\delta z=\frac{\Delta z_{11}+\Delta z_{22}-\Delta z_{21}-\Delta z_{12}}{L_2-L_1}.& \left(7\right)\end{array}$

(64) The above impedance difference per unit length δ.sub.Z can be partitioned into two parts:

(65) $\begin{array}{cc}\delta z=\delta z_1+\delta z_r,\mathrm{where}& \left(8a\right)\\ \delta z_1=\frac{\Delta z_{11}-\Delta z_{21}}{L_2-L_1},\mathrm{and}& \left(8b\right)\\ \delta z_r=\frac{\Delta z_{22}-\Delta z_{12}}{L_2-L_1}.& \left(8c\right)\end{array}$

(66) After determining the difference matrix Δz, the RF de-embedding module 105 determines internal impedance matrices of the through structures 230, 330 (“impedance corrections”). To accomplish this, in embodiments, the RF de-embedding module 105 may determine the impedance to ground Z.sub.L4 in the through structure 330 based on the following equation:
Z.sub.L4=1/2(Z.sub.21.sup.to2+Z.sub.12.sup.to2).   (9a)

(67) The impedance to ground Z.sub.L3 in the through structure 230 may also be determined based on the following equation:
Z.sub.L3=1/2(Z.sub.21.sup.to1+Z.sub.12.sup.to1).   (9b)

(68) When both the through structure 230 and the open structure 260 are symmetric (or from the viewpoint of a T-network for a Z-parameter matrix), the impedance Z.sub.21.sup.to1 is equal to the impedance Z.sub.12.sup.to1, and thus, the impedance to ground Z.sub.L3 is equal to the impedances Z.sub.21.sup.to1 and Z.sub.12.sup.to1. Similarly, when both the through structure 330 and the open structure 360 are symmetric, the impedance Z.sub.21.sup.to2 is equal to the impedance Z.sub.12.sup.to2, and thus, the impedance to ground Z.sub.L4 is equal to the impedances Z.sub.21.sup.to2 and Z.sub.12.sup.to2.

(69) Using the impedances to ground Z.sub.L4 and Z.sub.L3 in the through structures 330, 230, respectively, the RF de-embedding module 105 may determine a difference Δy between admittances to ground in the through structures 330, 230. In a first embodiment, at low frequency in the through structure 230, the impedance to ground |Z.sub.p3| of the padset parasitic may be safely assumed to much smaller than the impedance to ground |Z.sub.c3| of the internal through structure device. Similarly, at low frequency in the through structure 330, the impedance to ground |Z.sub.p4| of the padset parasitic may be safely assumed to be much smaller than the impedance to ground |Z.sub.c4| of the internal through structure device. Accordingly, the impedances to ground |Z.sub.p3| and |Z.sub.p4| of the padset parasitics may be approximated to a zero value. After this approximation, an admittance to ground in the through structure 330 is proportional to capacitance at low frequency, or is 1/Z.sub.L4. An admittance to ground in the through structure 230 is proportional to capacitance at low frequency, or is 1/Z.sub.L3. The difference Δy between the admittances to ground in the through structures 330, 230 is determined based on the following equation:

(70) $\begin{array}{cc}\Delta y=\frac{1}{Z_{L4}}-\frac{1}{Z_{L3}}.& \left(10\right)\end{array}$

(71) FIGS. 9A-9B are other exemplary schematics of equivalent circuits 900, 920 of the open-corrected Z-parameter matrices in accordance with aspects of the present invention. Specifically, in FIG. 9A, the circuit 900 is the equivalent circuit of the open-corrected Z-parameter matrix Z.sup.to1 for the through structure 230. The equivalent circuit 900 includes a resistor-inductor, series-connected pair 905 (e.g., the first port 235) having the impedance Z.sub.L1, and a resistor-inductor, series-connected pair 910 (e.g., the second port 240) having the impedance Z.sub.L2. The equivalent circuit 900 also includes a capacitor 915 (e.g., the capacitance to ground of the internal through structure device) having the admittance to ground Y.sub.c3, which is approximately equal to 1/Z.sub.L3. The padset parasitic Z.sub.p3 of the through structure 230 is approximated to a zero value.

(72) In FIG. 9B, the circuit 920 is the equivalent circuit of the open-corrected Z-parameter matrix Z.sup.to2 for the through structure 330. The equivalent circuit 920 includes a resistor-inductor, series-connected pair 925 (e.g., the first port 335) having the impedance (Z.sub.L1+δ.sub.Z1), and a resistor-inductor, series-connected pair 930 (e.g., the second port 340) having the impedance (Z.sub.L2+δ.sub.Z2). The equivalent circuit 920 also includes a capacitor 935 (e.g., the capacitance to ground of the internal through structure device) having an admittance to ground (Y.sub.c3+Δy), which is approximately equal to 1/Z.sub.L4. The padset parasitic Z.sub.p4 of the through structure 330 is approximated to a zero value.

(73) FIG. 9C is an exemplary schematic of an equivalent circuit 940 of the difference between admittances to ground in the through structures 230, 330 in accordance with aspects of the present invention. The equivalent circuit 940 has a length 945 of (L.sub.2−L.sub.1) and includes a capacitor 950 having an admittance equal to the difference Δy between admittances to ground in the through structures 330, 230.

(74) In an alternative, second embodiment, at low frequency in the through structure 230, an inductance part of the impedance to ground Z.sub.p3 of the padset parasitic may be safely assumed to be much smaller than a resistance part of the impedance to ground Z.sub.p3 and the impedance to ground |Z.sub.c3| of the internal through structure device. Likewise, at low frequency in the through structure 330, an inductance part of the impedance to ground Z.sub.p4 of the padset parasitic may be safely assumed to be much smaller than a resistance part of the impedance to ground Z.sub.p4 and the impedance to ground |Z.sub.c4| of the internal through structure device. Thus, the inductance parts of the impedances to ground Z.sub.p3 and Z.sub.p4 of the padset parasitics may be approximated to zero values. Under this approximation, the difference Δy between the admittances to ground in the through structures 330, 230 is determined based on the following equation:

(75) 0$\begin{array}{cc}\Delta y=\frac{1}{i\mathrm{Im}{Z}_{L4}}-\frac{1}{i\mathrm{Im}{Z}_{L3}}.& \left(11\right)\end{array}$

(76) FIGS. 10A-10B are other exemplary schematics of equivalent circuits 1000, 1025 of the open-corrected Z-parameter matrices in accordance with aspects of the present invention. Specifically, in FIG. 10A, the circuit 1000 is the equivalent circuit of the open-corrected Z-parameter matrix Z.sup.to1 for the through structure 230. The equivalent circuit 1000 includes a resistor-inductor, series-connected pair 1005 (e.g., the first port 235) having the impedance Z.sub.L1, and a resistor-inductor, series-connected pair 1010 (e.g., the second port 240) having the impedance Z.sub.L2. The equivalent circuit 1000 also includes a capacitor 1015 (e.g., the capacitance to ground of the internal through structure device) having the admittance to ground Y.sub.c3, and a resistor 1020 (e.g., the padset parasitic) having the real part of the impedance to ground Z.sub.p3. The inductance part of the impedance to ground Z.sub.p3 is approximated to a zero value.

(77) In FIG. 10B, the circuit 1025 is the equivalent circuit of the open-corrected Z-parameter matrix Z.sup.to2 for the through structure 330. The equivalent circuit 1025 includes a resistor-inductor, series-connected pair 1030 (e.g., the first port 335) having the impedance (Z.sub.L1+δ.sub.Z1), and a resistor-inductor, series-connected pair 1035 (e.g., the second port 340) having the impedance (Z.sub.L2+δ.sub.Z2). The equivalent circuit 1025 also includes a capacitor 1040 (e.g., the capacitance to ground of the internal through structure device) having an admittance to ground (Y.sub.c3+Δy), and a resistor 1045 (e.g., the padset parasitic) having the real part of the impedance to ground Z.sub.p4. The inductance part of the impedance to ground Z.sub.p4 is approximated to a zero value.

(78) Assuming that the determined difference Δy in admittance is proportional to a difference in length (L.sub.2−L.sub.1) of the through structures 330, 230, then an admittance difference per unit length is Δy/(L.sub.2−L.sub.1). It is noted that:
L.sub.2−L.sub.1=l.sub.2−l.sub.1,   (12)
where L.sub.2 is the length of the capacitor 225, L.sub.1 is the length of the capacitor 125, l.sub.2 is the length of a core portion of the capacitor 225, and l.sub.1 is the length of a core portion of the capacitor 225.

(79) However, since L.sub.1 and L.sub.2 may be different than l.sub.1 and l.sub.2, respectively, to prevent typical over de-embedding, the RF de-embedding module 105 may subtract out an impedance L.sub.1δ.sub.Z and an admittance δy.sub.1 from the open-corrected Z-parameter matrix Z.sup.to1 of the through structure 230. The admittance δy.sub.1 is determined based on the following equation:

(80) $\begin{array}{cc}\delta y_1=\frac{L_1\Delta y}{L_2-L_1}.& \left(13a\right)\end{array}$

(81) The RF de-embedding module 105 may also subtract out an impedance L.sub.2δ.sub.Z and an admittance δy.sub.2 from the open-corrected Z-parameter matrix Z.sup.to2 of the through structure 330. The admittance δy.sub.2 is determined based on the following equation:

(82) $\begin{array}{cc}\delta y_2=\frac{L_2\Delta y}{L_2-L_1}.& \left(13b\right)\end{array}$

(83) Using these determined admittances δy.sub.1 and δy.sub.2, the open-corrected Z-parameter matrices Z.sup.to1 and Z.sup.to2, and the difference matrix Δz between the open-corrected Z-parameter matrices Z.sup.to1 and Z.sup.to2, the RF de-embedding module 105 may determine the internal impedance matrices of the through structures 230, 330 (“the impedance corrections”). The 2×2 internal impedance matrix ΔZ.sup.to1 of the through structure 230 may be determined based on the following equation:

(84) $\begin{array}{cc}{Z}^{\mathrm{to}1}=\left(\begin{array}{cc}\begin{array}{c}\frac{L_1}{L_2-L_1}\left(\Delta z_{11}-\Delta z_{21}\right)-\\ \frac{{\left(Z_{21}^{\mathrm{to}1}\right)}^2\delta y_1}{1-\left(Z_{21}^{\mathrm{to}1}\right)\delta y_1}\end{array}& -\frac{{\left(Z_{12}^{\mathrm{to}1}\right)}^2\delta y_1}{1-\left(Z_{12}^{\mathrm{to}1}\right)\delta y_1}\\ -\frac{{\left(Z_{21}^{\mathrm{to}1}\right)}^2\delta y_1}{1-\left(Z_{21}^{\mathrm{to}1}\right)\delta y_1}& \begin{array}{c}\frac{L_1}{L_2-L_1}\left(\Delta z_{22}-\Delta z_{12}\right)-\\ \frac{{\left(Z_{12}^{\mathrm{to}1}\right)}^2\delta y_1}{1-\left(Z_{12}^{\mathrm{to}1}\right)\delta y_1}\end{array}\end{array}\right)=\left(\begin{array}{cc}{L}_1\delta z_l-\frac{{\left(Z_{21}^{\mathrm{to}1}\right)}^2\delta y_1}{1-\left(Z_{21}^{\mathrm{to}1}\right)\delta y_1}& -\frac{{\left(Z_{12}^{\mathrm{to}1}\right)}^2\delta y_1}{1-\left(Z_{12}^{\mathrm{to}1}\right)\delta y_1}\\ -\frac{{\left(Z_{21}^{\mathrm{to}1}\right)}^2\delta y_1}{1-\left(Z_{21}^{\mathrm{to}1}\right)\delta y_1}& L_1\delta z_r-\frac{{\left(Z_{12}^{\mathrm{to}1}\right)}^2\delta y_1}{1-\left(Z_{12}^{\mathrm{to}1}\right)\delta y_1}\end{array}\right).& \left(14a\right)\end{array}$

(85) The 2×2 internal impedance matrix ΔZ.sup.to2 of the through structure 330 may be determined based on the following equation:

(86) $\begin{array}{cc}{Z}^{\mathrm{to}2}=\left(\begin{array}{cc}\begin{array}{c}\frac{L_2}{L_2-L_1}\left(\Delta z_{11}-\Delta z_{21}\right)-\\ \frac{{\left(Z_{21}^{\mathrm{to}2}\right)}^2\delta y_2}{1-\left(Z_{21}^{\mathrm{to}2}\right)\delta y_2}\end{array}& -\frac{{\left(Z_{12}^{\mathrm{to}2}\right)}^2\delta y_2}{1-\left(Z_{12}^{\mathrm{to}2}\right)\delta y_2}\\ -\frac{{\left(Z_{21}^{\mathrm{to}2}\right)}^2\delta y_2}{1-\left(Z_{21}^{\mathrm{to}2}\right)\delta y_2}& \begin{array}{c}\frac{L_2}{L_2-L_1}\left(\Delta z_{22}-\Delta z_{12}\right)-\\ \frac{{\left(Z_{12}^{\mathrm{to}2}\right)}^2\delta y_2}{1-\left(Z_{12}^{\mathrm{to}2}\right)\delta y_2}\end{array}\end{array}\right)=\left(\begin{array}{cc}{L}_2\delta z_l-\frac{{\left(Z_{21}^{\mathrm{to}2}\right)}^2\delta y_2}{1-\left(Z_{21}^{\mathrm{to}2}\right)\delta y_2}& -\frac{{\left(Z_{12}^{\mathrm{to}2}\right)}^2\delta y_2}{1-\left(Z_{12}^{\mathrm{to}2}\right)\delta y_2}\\ -\frac{{\left(Z_{21}^{\mathrm{to}2}\right)}^2\delta y_2}{1-\left(Z_{21}^{\mathrm{to}2}\right)\delta y_2}& L_2\delta z_r-\frac{{\left(Z_{12}^{\mathrm{to}2}\right)}^2\delta y_2}{1-\left(Z_{12}^{\mathrm{to}2}\right)\delta y_2}\end{array}\right).& \left(14b\right)\end{array}$

(87) In a third embodiment, the RF de-embedding module 105 may determine these impedance corrections via another process. Specifically, from the difference matrix Δz between these Z-parameter matrices Z.sup.to1 and Z.sup.to2 in equation (5), the RF de-embedding module 105 may determine a difference between the impedances to ground of the through structures 330, 230. The difference Δz.sub.g between the impedances to ground of the through structures 330, 230 may be determined based on the following equation:

(88) $\begin{array}{cc}\Delta z_g=\frac{1}{2}\left(\Delta z_{21}+\Delta z_{12}\right)=\frac{1}{2}(Z_{21}^{\mathrm{to}2}-Z_{21}^{\mathrm{to}1}+Z_{12}^{\mathrm{to}2}-Z_{12}^{\mathrm{to}1})=Z_{L4}-Z_{L3}\approx Z_{c4}-Z_{c3}=\frac{1}{Y_{c4}}-\frac{1}{Y_{c3}}.& \left(15\right)\end{array}$

(89) It is noted that the difference Δz.sub.g represents the difference between the impedances to ground of the two internal through structure devices Z.sub.c4 and Z.sub.c3 only, and the impedances to ground of the padset parasitics Z.sub.p4 and Z.sub.p3 are cancelled. The RF de-embedding module 105 may independently determine the impedances to ground of the two internal through structure devices Z.sub.c4 and Z.sub.c3 based on a relationship between their admittances Y.sub.c3 and Y.sub.c4. Particularly, assuming that a change in admittance between the internal through structure devices is proportional to a change in their length, a proportionality constant may be approximated as follows:

(90) $\begin{array}{cc}\frac{Y_{c3}}{Y_{c4}}\approx \frac{L_1}{L_2}.& \left(16a\right)\end{array}$

(91) Using this approximation, the admittance Y.sub.c4 may be denoted as a function of the admittance Y.sub.c3 as follows:

(92) $\begin{array}{cc}{Y}_{c4}=Y_{c3}\left(\frac{L_2}{L_1}\right).& \left(16b\right)\end{array}$

(93) Using this relation, the difference Δz.sub.g between the impedances to ground of the through structures 330, 230 may be denoted as follows:

(94) $\begin{array}{cc}\Delta z_g=\frac{1}{Y_{c4}}-\frac{1}{Y_{c3}}\approx \frac{1}{Y_{c3}\left(\frac{L_2}{L_1}\right)}-\frac{1}{Y_{c3}}=\frac{L_1-L_2}{Y_{c3}{L}_2}\approx \frac{L_1-L_2}{Y_{c4}{L}_1}.& \left(16c\right)\end{array}$

(95) Accordingly, the RF de-embedding module 105 may independently determine the impedances to ground of the two internal through structure devices Z.sub.c4 and Z.sub.c3 based on the following equations:

(96) $\begin{array}{cc}{Z}_{c3}=\frac{1}{Y_{c3}}\approx \frac{L_2\Delta z_g}{L_1-L_2};\mathrm{and}& \left(16d\right)\\ Z_{c4}=\frac{1}{Y_{c4}}\approx \frac{L_1\Delta z_g}{L_1-L_2}.& \left(16e\right)\end{array}$

(97) Utilizing the impedances to ground of the two internal through structure devices Z.sub.c4 and Z.sub.c3, and the difference matrix Δz between the open-corrected Z-parameter matrices Z.sup.to1 and Z.sup.to2, the RF de-embedding module 105 may determine the internal impedance matrices of the through structures 230, 330 (“the impedance corrections”). The 2×2 internal impedance matrix ΔZ.sup.to1 of the through structure 230 may be determined based on the following equation:

(98) 0$\begin{array}{cc}\Delta Z^{\mathrm{to}1}=\left(\begin{array}{cc}\frac{L_1}{L_2-L_1}\left(\Delta z_{11}-\Delta z_{21}\right)+Z_{c3}& Z_{c3}\\ Z_{c3}& \frac{L_1}{L_2-L_1}\left(\Delta z_{22}-\Delta z_{12}\right)+Z_{c3}\end{array}\right)=\left(\begin{array}{cc}{L}_1\delta z_l+Z_{c3}& Z_{c3}\\ Z_{c3}& L_1\delta z_r+Z_{c3}\end{array}\right).& \left(17a\right)\end{array}$

(99) The 2×2 internal impedance matrix ΔZ.sup.to2 of the through structure 330 may be determined by the following equation:

(100) $\begin{array}{cc}\Delta Z^{\mathrm{to}2}=\left(\begin{array}{cc}\frac{L_2}{L_2-L_1}\left(\Delta z_{11}-\Delta z_{21}\right)+Z_{c4}& Z_{c4}\\ Z_{c4}& \frac{L_2}{L_2-L_1}\left(\Delta z_{22}-\Delta z_{12}\right)+Z_{c4}\end{array}\right)=\left(\begin{array}{cc}{L}_2\delta z_l+Z_{c4}& Z_{c4}\\ Z_{c4}& L_2\delta z_r+Z_{c4}\end{array}\right).& \left(17b\right)\end{array}$

(101) As shown in equations (17a) and (17b), any inaccuracy in the determination of the impedances to ground of the two internal through structure devices Z.sub.c4 and Z.sub.c3 appears equally in all four terms of the internal impedance matrices ΔZ.sup.to1 and ΔZ.sup.to2. This implies that any error will appear equally in all four terms of the final de-embedded, open-corrected Y-parameter matrices of the DUT structures 200, 300. Specifically, this means that any inaccuracy in the determination of the impedances to ground of the two internal through structure devices Z.sub.c4 and Z.sub.c3 appears in the final de-embedded, open-corrected Y-parameter matrices of the DUT structures 200, 300 as an error in the impedance to ground. In two-port measurements, of passive devices in particular, this error is a parasitic that is often of secondary importance.

(102) Last, utilizing the open-corrected Y-parameter matrices Y.sup.do1 and Y.sup.do2, the open-corrected Z-parameter matrices Z.sup.to1 and Z.sup.to2, and the impedance corrections ΔZ.sup.to1 and ΔZ.sup.to2, the RF de-embedding module 105 determines Y-parameter matrices Y.sup.dev1 and Y.sup.dev2 of the capacitors 225, 325, respectively, with the following equations:
Y.sup.dev1=[(Y.sup.do1).sup.−1−Z.sup.to1+ΔZ.sup.to1].sup.−1; and   (18a)
Y.sup.dev2=[(Y.sup.do2).sup.−1−Z.sup.to2+ΔZ.sup.to2].sup.−1.   (18b)

(103) For the first and second embodiments where the admittance δy.sub.1 and δy.sub.2 are determined, the Y-parameter matrices Y.sup.dev1 and Y.sup.dev2 of the capacitors 225, 325, respectively, may be denoted as follows:

(104) $\begin{array}{cc}{Y}^{\mathrm{dev}1}={\left[{\left(Y^{\mathrm{do}1}\right)}^{-1}-{\tilde{Z}}^{\mathrm{to}1}\right]}^{-1};\mathrm{and}& \left(19a\right)\\ Y^{\mathrm{dev}2}={\left[{\left(Y^{\mathrm{do}2}\right)}^{-1}-{\tilde{Z}}^{\mathrm{to}2}\right]}^{-1},\mathrm{where}& \left(19b\right)\\ {\tilde{Z}}^{\mathrm{to}1}=Z^{\mathrm{to}1}-{\mathrm{\Delta Z}}^{\mathrm{to}1}=(\begin{array}{cc}\begin{array}{c}{Z}_{11}^{\mathrm{to}1}-\frac{L_1}{L_2-L_1}\left(\Delta z_{11}-\Delta z_{21}\right)+\\ \frac{{\left(Z_{21}^{\mathrm{to}1}\right)}^2\delta y_1}{1-\left(Z_{21}^{\mathrm{to}1}\right)\delta y_1}\end{array}& \frac{1}{{\left(Z_{12}^{\mathrm{to}1}\right)}^{-1}-\delta y_1}\\ \frac{1}{{\left(Z_{21}^{\mathrm{to}1}\right)}^{-1}-\delta y_1}& \begin{array}{c}{Z}_{22}^{\mathrm{to}1}-\frac{L_1}{L_2-L_1}\left(\Delta z_{22}-\Delta z_{12}\right)+\\ \frac{{\left(Z_{12}^{\mathrm{to}1}\right)}^2\delta y_1}{1-\left(Z_{12}^{\mathrm{to}1}\right)\delta y_1}\end{array}\end{array})=\left(\begin{array}{cc}{Z}_{11}^{\mathrm{to}1}-L_1\delta z_l+\frac{{\left(Z_{21}^{\mathrm{to}1}\right)}^2\delta y_1}{1-\left(Z_{21}^{\mathrm{to}1}\right)\delta y_1}& \frac{1}{{\left(Z_{12}^{\mathrm{to}1}\right)}^{-1}-\delta y_1}\\ \frac{1}{{\left(Z_{21}^{\mathrm{to}1}\right)}^{-1}-\delta y_1}& Z_{22}^{\mathrm{to}1}-L_1\delta z_r+\frac{{\left(Z_{12}^{\mathrm{to}1}\right)}^2\delta y_1}{1-\left(Z_{12}^{\mathrm{to}1}\right)\delta y_1}\end{array}\right),\mathrm{and}& \left(19c\right)\\ {\tilde{Z}}^{\mathrm{to}2}=Z^{\mathrm{to}2}-{\mathrm{\Delta Z}}^{\mathrm{to}2}=(\begin{array}{cc}\begin{array}{c}{Z}_{11}^{\mathrm{to}2}-\frac{L_2}{L_2-L_1}\left(\Delta z_{11}-\Delta z_{21}\right)+\\ \frac{{\left(Z_{21}^{\mathrm{to}2}\right)}^2\delta y_2}{1-\left(Z_{21}^{\mathrm{to}2}\right)\delta y_2}\end{array}& \frac{1}{{\left(Z_{12}^{\mathrm{to}2}\right)}^{-1}-\delta y_2}\\ \frac{1}{{\left(Z_{21}^{\mathrm{to}2}\right)}^{-1}-\delta y_2}& \begin{array}{c}{Z}_{22}^{\mathrm{to}2}-\frac{L_2}{L_2-L_1}\left(\Delta z_{22}-\Delta z_{12}\right)+\\ \frac{{\left(Z_{12}^{\mathrm{to}2}\right)}^2\delta y_2}{1-\left(Z_{21}^{\mathrm{to}2}\right)\delta y_2}\end{array}\end{array})=\left(\begin{array}{cc}{Z}_{11}^{\mathrm{to}2}-L_2\delta z_l+\frac{{\left(Z_{21}^{\mathrm{to}2}\right)}^2\delta y_2}{1-\left(Z_{21}^{\mathrm{to}2}\right)\delta y_2}& \frac{1}{{\left(Z_{12}^{\mathrm{to}2}\right)}^{-1}-\delta y_2}\\ \frac{1}{{\left(Z_{21}^{\mathrm{to}2}\right)}^{-1}-\delta y_2}& Z_{22}^{\mathrm{to}2}-L_2\delta z_r-\frac{{\left(Z_{21}^{\mathrm{to}2}\right)}^2\delta y_2}{1-\left(Z_{21}^{\mathrm{to}2}\right)\delta y_2}\end{array}\right).& \left(19d\right)\end{array}$

(105) Advantageously, the invention leads to a more accurate characterization of an RF device, such as the capacitors 225 and 325. Specifically, in the example of the capacitors 225 and 325, the invention leads to more accurate Y-parameter matrices Y.sup.dev1 and Y.sup.dev2 of the capacitors 225, 325. This is because the internal impedance matrices ΔZ.sup.to1 and ΔZ.sup.to2 of the through structures 230, 330 are determined and added back into the Y-parameter matrices Y.sup.dev1 and Y.sup.dev2 instead of being subtracted from these parameters.

Flow Diagrams

(106) FIGS. 11A-11C show exemplary flows for performing aspects of the present invention. The steps of FIGS. 11A-11C may be implemented in the environment of FIG. 1, for example.

(107) The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

(108) Furthermore, the invention can take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system. The software and/or computer program product can be implemented in the environment of FIG. 1. For the purposes of this description, a computer-usable or computer readable medium can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device) or a propagation medium. Examples of a computer-readable storage medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk and an optical disk. Current examples of optical disks include compact disk-read only memory (CD-ROM), compact disc-read/write (CD-R/W) and DVD.

(109) FIG. 11A is an exemplary flow diagram of a process 1100 for RF de-embedding of a device. At step 1105, the process starts. At step 1110, an RF de-embedding module (e.g., the RF de-embedding module 105 in FIG. 1) measures three separate 2×2 S-parameter matrices S.sub.dut1, S.sub.through1, and S.sub.open1 of a first set of structures (e.g., the DUT structure 200, the through structure 230, and the open structure 260 in FIGS. 2A-2C). At step 1115, the RF de-embedding module measures three separate 2×2 S-parameter matrices S.sub.dut2, S.sub.through2, and S.sub.open2 of a second set of structures (e.g., the DUT structure 300, the through structure 330, and the open structure 360 in FIGS. 3A-3C).

(110) At step 1120, the RF de-embedding module determines three separate 2×2 Y-parameter matrices Y.sub.dut1, Y.sub.through1, and Y.sub.open1 of the first set of structures that correspond to the matrices S.sub.dut1, S.sub.through1, and S.sub.open1, respectively. At step 1125, the RF de-embedding module determines three separate 2×2 Y-parameter matrices Y.sub.dut2, Y.sub.through2, and Y.sub.open2 of the second set of structures that correspond to the matrices S.sub.dut2, S.sub.through2, and S.sub.open2, respectively. At step 1130, the RF de-embedding module determines open-corrected Y-parameter matrices Y.sup.do1 and Y.sup.to1 of a first DUT structure (e.g., the DUT structure 200) and a first through structure (e.g., the through structure 230) based on the Y-parameters matrices Y.sub.dut1, Y.sub.through1, and Y.sub.open1. At step 1135, the RF de-embedding module determines open-corrected Y-parameters matrices Y.sup.do2 and Y.sup.to2 of a second DUT structure (e.g., the DUT structure 300) and a second through structure (e.g., the through structure 330) based on the Y-parameters matrices Y.sub.dut2, Y.sub.through2, and Y.sub.open2.

(111) At step 1140, the RF de-embedding module determines an open-corrected Z-parameter matrix Z.sup.to1 of the first through structure based on the open-corrected Y-parameter matrix Y.sup.to1. At step 1145, the RF de-embedding module determines an open-corrected Z-parameter matrix Z.sup.to2 of the second through structure based on the open-corrected Y-parameter matrix Y.sup.to2. At step 1150, the RF de-embedding module determines a difference matrix Δz between these Z-parameter matrices Z.sup.to1 and Z.sup.to2. At step 1155, in embodiments, the RF de-embedding module determines impedance corrections ΔZ.sup.to1 and ΔZ.sup.to2 of the through structures based on the open-corrected Z-parameter matrices Z.sup.to1 and Z.sup.to2, and the difference matrix Δz between the open-corrected Z-parameter matrices Z.sup.to1 and Z.sup.to2.

(112) At step 1160, the RF de-embedding module determines a Y-parameter matrix T.sup.dev1 of a device in the first set of structures based on the open-corrected Y-parameter matrix Y.sup.do1, the open-corrected Z-parameter matrix Z.sup.to1, and the impedance correction ΔZ.sup.to1. At step 1165, the RF de-embedding module determines a Y-parameter matrix Y.sup.dev2 of a device in the second set of structures based on the open-corrected Y-parameter matrix Y.sup.do2, the open-corrected Z-parameter matrix Z.sup.to2, and the impedance correction ΔZ.sup.to2. At step 1170, the process ends.

(113) FIG. 11B is an exemplary flow diagram of a process for the determining of the impedance corrections ΔZ.sup.to1 and ΔZ.sup.to2 of the through structures (e.g., the step 1155 in FIG. 11A). At step 1175, the process starts. At step 1180, the RF de-embedding module determines impedance to ground Z.sub.L4 and Z.sub.L3 in the through structures based on the open-corrected Z-parameters Z.sup.to1 and Z.sup.to2. At step 1185, in embodiments, the RF de-embedding module determines a difference Δy between admittances to ground in the through structures based on the impedance to ground Z.sub.L4 and Z.sub.L3.

(114) At step 1190, the RF de-embedding module determines admittances δy.sub.1 and δy.sub.2 based on the difference Δy between admittances to ground and lengths L.sub.1 and L.sub.2 of the through structures. At step 1195, the RF de-embedding module determines the impedance corrections ΔZ.sup.to1 and ΔZ.sup.to2 of the through structures based on the open-corrected Z-parameter matrices Z.sup.to1 and Z.sup.to2, the difference matrix Δz between the open-corrected Z-parameter matrices Z.sup.to1 and Z.sup.to2, and the admittances δy.sub.1 and δy.sub.2. At step 1200, the process ends.

(115) FIG. 11C is an exemplary flow diagram of another process for the determining of the impedance corrections ΔZ.sup.to1 and ΔZ.sup.to2 of the through structures (e.g., the step 1155 in FIG. 11A). At step 1205, the process starts. At step 1210, the RF de-embedding module determines a difference Δz.sub.g between impedances to ground of the through structures based on the open-corrected Z-parameters Z.sup.to1 and Z.sup.to2. At step 1215, the RF de-embedding module determines impedances to ground of internal through structure devices Z.sub.c4 and Z.sub.c3 in the through structures based on the difference Δz.sub.g between impedances to ground and the lengths L.sub.1 and L.sub.2. At step 1220, the RF de-embedding module determines the impedance corrections ΔZ.sup.to1 and ΔZ.sup.to2 of the through structures based on the open-corrected Z-parameter matrices Z.sup.to1 and Z.sup.to2, the difference matrix Δz between the open-corrected Z-parameter matrices Z.sup.to1 and Z.sup.to2, and the impedances to ground of internal through structure devices Z.sub.c4 and Z.sub.c3. At step 1225, the process ends.

(116) The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

(117) The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims, if applicable, are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principals of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated. Accordingly, while the invention has been described in terms of embodiments, those of skill in the art will recognize that the invention can be practiced with modifications and in the spirit and scope of the appended claims.