1S1R memory integrated structure with larger selector surface area which can effectively suppress leakage current in the cross array without increasing the overall size of the integrated structure and method for fabricating the same

Abstract

The present disclosure provides a 1S1R memory integrated structure and a method for fabricating the same, wherein the 1S1R memory integrated structure includes: a word line metal, a resistive material layer, a selector lower electrode, a selector material layer, a selector upper electrode, an interconnection wire, and a bit line metal; wherein the selector material layer is in a shape of a groove, and the selector upper electrode is formed in the groove. According to the 1S1R memory integrated structure and its fabricating method in the present disclosure, by the change of the integrated position of the selector, the device area of the selector is much larger than the device area of the memory, which significantly reduces the requirement for the on-state current density of the selector.

Claims

1. A 1S1R memory cell, comprising: a word line metal, a resistive material layer, a first selector electrode, a selector material layer, a second selector electrode, an interconnection wire, and a bit line metal; wherein the selector material layer is in a shape of a groove, and the second selector electrode is formed in the groove, wherein an area of the selector material layer is larger than an area of the resistive material layer, and wherein the word line, the bit line, the interconnection wire, the resistive material layer, and the selector material layer are formed by a process of electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or sputtering; a material of the word line, the bit line and the interconnection wire comprises W or Cu; a thickness of the resistive material layer is between 5 nm and 60 nm, and a material of the resistive material layer comprises one or a combination of ZrO.sub.2, HfO.sub.2, TiO.sub.2, SiO.sub.2, Ta.sub.2O.sub.5, and Y.sub.2O.sub.3; and a thickness of the selector material layer is between 5 nm and 60 nm, and a material of the selector material layer comprises a metal oxide or a mixed ion-electron conducting (MIEC) material; the metal oxide comprises one or a combination of ZrO.sub.2, HfO.sub.2, TiO.sub.2, SiO.sub.2, Ta.sub.2O.sub.5, Y.sub.2O.sub.3, NbOx, and VO.sub.2.

2. The 1S1R memory cell of claim 1, further comprising a first memory electrode and a second memory electrode, wherein the word line metal is also used as the first memory electrode of the 1S1R memory cell, and the first selector electrode is also used as the second memory electrode of the 1S1R memory cell and an interconnection wire.

3. The 1S1R memory cell of claim 1, wherein the resistive material layer is on the word line metal or on the second selector electrode.

4. A method for fabricating a 1S1R memory cell, comprising: forming sequentially, from bottom to top, a word line metal, a resistive material layer and a first selector electrode; forming an insulating layer on the first selector electrode, etching the insulating layer to form a groove structure; forming a groove-shaped selector material layer in the groove structure; forming a second selector electrode in the groove of the selector material layer; and forming sequentially an interconnection wire and a bit line metal on the second selector electrode, wherein the 1S1R memory cell further comprises a first memory electrode and a second memory electrode, the word line metal is also used as the first memory electrode of the 1S1R memory cell, and the first selector electrode is also used as the second memory electrode of the 1S1R memory cell and an interconnection wire; an area of the formed selector material layer is greater than an area of the resistive material layer, and wherein the word line, the bit line, the interconnection wire, the resistive material layer, and the selector material layer are formed by a process of electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or sputtering; a material of the word line, the bit line and the interconnection wire comprises W or Cu; a thickness of the resistive material layer is between 5 nm and 60 nm, and a material of the resistive material layer comprises one or a combination of ZrO.sub.2, HfO.sub.2, TiO.sub.2, SiO.sub.2, Ta.sub.2O.sub.5, and Y.sub.2O.sub.3; a thickness of the selector material layer is between 5 nm and 60 nm, and a material of the selector material layer comprises a metal oxide or a mixed ion-electron conducting (MIEC) material; the metal oxide comprises one or a combination of ZrO.sub.2, HfO.sub.2, TiO.sub.2, SiO.sub.2, Ta.sub.2O.sub.5, Y.sub.2O.sub.3, NbOx, and VO.sub.2; and a material of the insulating layer comprises SiO.sub.2.

5. The method for fabricating the 1S1R memory cell of claim 4, wherein in the etching of the insulating layer, the insulating layer is etched to an upper surface of the interconnection wire, and thus a bottom surface of the groove structure is flush with the upper surface of the interconnection wire.

6. A method for fabricating a 1S1R memory cell, comprising: forming sequentially, from bottom to top, a word line metal and a first selector electrode; forming an insulating layer on the first selector electrode, etching the insulating layer to form a groove structure; forming a groove-shaped selector material layer in the groove structure; forming a second selector electrode in the groove of the selector material layer; and forming sequentially a resistive material layer, an interconnection wire and a bit line metal on the second selector electrode, wherein the 1S1R memory cell further comprises a first memory electrode and a second memory electrode, the word line metal is also used as the first memory electrode of the 1S1R memory cell, and the first selector electrode is also used as the second memory electrode of the 1S1R memory cell and an interconnection wire; an area of the formed selector material layer is greater than an area of the resistive material layer, and wherein the word line, the bit line, the interconnection wire, the resistive material layer, and the selector material layer are formed by a process of electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or sputtering; a material of the word line, the bit line and the interconnection wire comprises W or Cu; a thickness of the resistive material layer is between 5 nm and 60 nm, and a material of the resistive material layer comprises one or a combination of ZrO.sub.2, HfO.sub.2, TiO.sub.2, SiO.sub.2, Ta.sub.2O.sub.5, and Y.sub.2O.sub.3; a thickness of the selector material layer is between 5 nm and 60 nm, and a material of the selector material layer comprises a metal oxide or a mixed ion-electron conducting (MIEC) material; the metal oxide comprises one or a combination of ZrO.sub.2, HfO.sub.2, TiO.sub.2, SiO.sub.2, Ta.sub.2O.sub.5, Y.sub.2O.sub.3, NbOx, and VO.sub.2; and a material of the insulating layer comprises SiO.sub.2.

7. The method for fabricating the 1S1R memory cell of claim 6, wherein in the etching of the insulating layer, the insulating layer is etched to an upper surface of the interconnection wire, and thus a bottom surface of the groove structure is flush with the upper surface of the interconnection wire.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The drawings are intended to provide a further understanding of the present disclosure, and form part of the specification. In addition, the drawings together with the specific embodiments below are used to interpret the present disclosure, but do not constitute a restriction on the present disclosure. In the drawings:

(2) FIG. 1 is a schematic diagram of a conventional 1S1R memory integrated structure.

(3) FIG. 2 is a schematic diagram of a 1S1R memory integrated structure according to an embodiment of the present disclosure.

(4) FIGS. 3-7 are schematic diagrams showing a fabricating process of the 1S1R memory integrated structure according to an embodiment of the present disclosure.

(5) FIG. 8 is a schematic diagram of a 1S1R memory integrated structure according to still another embodiment of the present disclosure.

COMPONENT DESCRIPTION

(6) 101-interconnection wire (selector upper electrode), M0-selector lower electrode; 201-selector material layer, 301-interconnection wire, 401-resistive material layer; 102-interconnection wire, 202-selector material layer, 302-interconnection wire (selector lower electrode, memory upper electrode), 402-resistive material layer, 502-insulating layer, 602-deep groove, M1-word line metal (memory lower electrode), M2-selector upper electrode, M3-bit line metal; 103-interconnection wire, 203-selector material layer, 303-interconnection wire (selector lower electrode, memory upper electrode), 403-resistive material layer.

DETAILED DESCRIPTION

(7) To make the objectives, technical solutions, and advantages of the present disclosure clearer, the present disclosure will be further described in detail below in conjunction with the specific embodiments and with reference to the accompanying drawings.

(8) The present disclosure provides a 1S1R memory integrated structure, including: a word line metal, a resistive material layer, a selector lower electrode, a selector material layer, a selector upper electrode, an interconnection wire, and a bit line metal; wherein the selector material layer is in a shape of a groove, and the selector upper electrode is formed in the groove.

(9) In addition, the present disclosure also provides a method for fabricating a 1S1R memory integrated structure, including:

(10) forming, from bottom to top, a word line metal, a resistive material layer and a selector lower electrode;

(11) forming an insulating layer on the selector lower electrode, etching the insulating layer to form a groove structure;

(12) forming a groove-shaped selector material layer in the groove structure;

(13) forming a selector upper electrode in the groove of the selector material layer; and

(14) forming sequentially an interconnection wire and a bit line metal on the selector upper electrode.

(15) In addition, the present disclosure also provides another method for fabricating 1S1R memory integrated structure, including:

(16) forming, from bottom to top, a word line metal and a selector lower electrode;

(17) forming an insulating layer on the selector lower electrode, etching the insulating layer to form a groove structure;

(18) forming a groove-shaped selector material layer in the groove structure;

(19) forming a selector upper electrode in the groove of the selector material layer; and

(20) forming sequentially a resistive material layer, an interconnection wire and a bit line metal on the selector upper electrode.

(21) Specifically, the word line, the bit line, the interconnection wire, the resistive material layer, and the selector material layer may be formed by a process of electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or sputtering.

(22) In the 1S1R memory integrated structure, the word line metal is also a memory lower electrode, and the selector lower electrode is also a memory upper electrode and an interconnection wire. The resistive material layer may be on the word line metal or on the selector upper electrode. The area of the selector material layer is larger than the area of the resistive material layer.

(23) In an embodiment, as shown in FIG. 2, the 1S1R memory integrated structure includes, from bottom to top, a memory word line metal M1 (which is also a memory lower electrode), a resistive material layer 402, a selector lower electrode 302 (which also serves as a resistive memory upper electrode and an interconnection wire), a selector material layer 202, a selector upper electrode M2, an interconnection wire 102 and a bit line metal M3.

(24) As shown in FIG. 2, the selector material layer 202 is in a shape of a groove, and the selector upper electrode M2 is filled in the groove of the selector material layer 202, and the top surface of the selector upper electrode M2 is flush with the top surfaces of both sides of the groove of the selector material layer 202.

(25) The bottom surface of the selector material layer has a larger dimension than the bottom surface of each of the metal electrodes and the interconnection wire. By the change of the integrated position of the selector, the device area of the selector is much larger than the device area of the memory, which significantly reduces the requirement for the on-state current density of the selector.

(26) Specifically, the metal electrodes M1, M2, the bit line metal M3, and the interconnection wires 302 and 102 may be made of a metal element such as W, Cu, and the like, and may be fabricated by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition or sputtering.

(27) The resistive material layer 402 is formed on the lower electrode M1 and may be fabricated by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition or sputtering. The material of the resistive material layer comprises one or a combination of completely proportioned metal oxides such as ZrO.sub.2, HfO.sub.2, TiO.sub.2, SiO.sub.2, Ta.sub.2O.sub.5, Y.sub.2O.sub.3, and the like, and the thickness is between 5 nm and 60 nm, preferably, the thickness is 36 nm.

(28) The selector material layer 202 is formed on the selector lower electrode 302 and is made of metal oxide or mixed ion-electron conducting (MIEC) material. Specifically, the selector material layer 202 may be formed by one or a combination of metal oxides such as ZrO.sub.2, HfO.sub.2, TiO.sub.2, SiO.sub.2, Ta.sub.2O.sub.5, Y.sub.2O.sub.3, NbO.sub.x, VO.sub.2, or may be formed by other compound materials, such as mixed ion-electron conducting (MIEC) materials. The selector material layer may be fabricated by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition or sputtering, and the thickness is between 5 nm and 60 nm, preferably, the thickness is 38 nm.

(29) Referring to FIG. 2, the outer walls of the word line metal M1, the resistive material layer 402, the selector lower electrode 302, the selector material layer 202, the selector upper electrode M2, the interconnection wire 102, and the bit line metal M3 are covered with an insulating layer 602, and the material of the insulating layer may be SiO.sub.2. The insulating layer may also be fabricated by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition or sputtering.

(30) In another embodiment, as shown in FIGS. 2-7, the method for fabricating the 1S1R memory integrated structure includes the following steps.

(31) Step 1: the lower electrode M1, the resistive material layer 402, and the interconnection wire 302 are formed using a standard CMOS process, as shown in FIG. 3.

(32) Specifically, the lower electrode M1, the resistive material layer 402 and the interconnection wire 302 may be fabricated by one way of electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, and sputtering. The material of the resistive material layer 402 may be one of completely proportioned metal oxides such as ZrO.sub.2, HfO.sub.2, TiO.sub.2, SiO.sub.2, Ta.sub.2O.sub.5, Y.sub.2O.sub.3, and the like, and the thickness of the material is between 5 nm and 60 nm.

(33) Step 2: an insulating layer 502 is grown on the interconnection wire 302, as shown in FIG. 4.

(34) The material of the insulating layer may be SiO.sub.2. The insulating layer 502 is grown by one of electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, and sputtering.

(35) Step 3: the insulating layer is etched to form a deep groove 602 on the insulating layer, as shown in FIG. 5.

(36) Specifically, in the step of etching the insulating layer, the insulating layer is etched to an upper surface of the interconnection wire, and a bottom surface of the deep groove 602 thus formed is flush with the upper surface of the interconnection wire.

(37) Step 4: the selector material layer 202 is fabricated by one of electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, and sputtering. Then the structure shown in FIG. 6 is obtained by a smoothing process.

(38) Specifically, the selector material layer may be formed by one of metal oxides such as ZrO.sub.2, HfO.sub.2, TiO.sub.2, SiO.sub.2, Ta.sub.2O.sub.5, Y.sub.2O.sub.3, NbO.sub.x, VO.sub.2, or may be formed by other compound materials, such as mixed ion-electron conducting (MIEC) materials.

(39) Step 5: the upper electrode M2 is grown on the selector material layer 202, and then the structure shown in FIG. 7 is obtained by a smoothing process.

(40) Step 6: the interconnection wire 102 and the bit line metal M3 are implemented by a standard CMOS process, and the 1S1R memory integrated structure as shown in FIG. 2 is obtained.

(41) In the method of this embodiment, the metal electrodes M1, M2, the bit line metal M3, and the interconnection wires 303 and 103 may be made of a metal element such as W, Cu, and the like, and may be fabricated by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition or sputtering.

(42) In another embodiment, as shown in FIG. 8, the 1S1R memory integrated structure sequentially includes, from bottom to top, a memory word line metal and lower electrode M1, a selector lower electrode 303 (which also serves as a memory upper electrode and an interconnection wire), a selector material layer 203, a selector upper electrode M2, a resistive material layer 403, an interconnection wire 103 and a bit line metal M3.

(43) Different from the 1S1R memory integrated structure in the previous embodiment, the resistive material layer is formed on the selector upper electrode in the present embodiment, whereas the resistive material layer is formed on the word line metal in the previous embodiment. The other components of the 1S1R memory integrated structure of the present embodiment are the same as those of the previous embodiment, and the corresponding fabricating methods are similar to the foregoing fabricating methods, and are not described herein again.

(44) Heretofore, the embodiments of the present disclosure have been described in detail in conjunction with the accompanying drawings. Based on the above description, those skilled in the art should have a clear understanding of the 1S1R memory integrated structure and its fabricating method of the present disclosure.

(45) It should be noted that the implementations that are not shown or described in the drawings or the text of the specification are all known to those of ordinary skill in the art and are not described in detail. In addition, the above definitions of the various elements are not limited to the specific structures and shapes mentioned in the embodiments, and those skilled in the art may simply change or replace them. An example of parameters including specific values may be provided herein, however, these parameters need not be exactly equal to the corresponding values, but may approximate the corresponding values within acceptable error tolerances or design constraints. The directional terms mentioned in the embodiments, such as “upper”, “lower”, “front”, “back”, “left”, “right”, and the like, are merely referring to the directions of the drawings, and are not intended to limit the scope of protection of the present disclosure. The above embodiments may be used in combination with each other or with other embodiments based on design and reliability considerations, that is, the technical features in different embodiments may be freely combined to form more embodiments.

(46) The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments are obvious to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, this disclosure will not be limited to these embodiments shown herein, but shall conform to the broadest range consistent with the principles and novel features disclosed herein.

(47) It should be noted that the implementations that are not shown or described in the drawings or the text of the specification are all known to those of ordinary skill in the art and are not described in detail. In addition, the above definitions of the various elements and methods are not limited to the specific structures, shapes or manners mentioned in the embodiments, and those skilled in the art can simply modify or replace them.

(48) The specific embodiments described above further elaborate on the purpose, technical solution and beneficial effect of this disclosure. It should be understood that the foregoing are only specific embodiments of the this disclosure and are not used to limit this disclosure, and that any modifications, equivalent substitutions, improvements, and the like, made within the spirit and principles of this disclosure shall be included in the scope of protection of this disclosure.