Integrated grating coupler

Abstract

A grating coupler having first and second ends for coupling a light beam to a waveguide of a chip includes a substrate configured to receive the light beam from the first end and transmit the light beam through the second end, the substrate having a first refractive index n1, a grating structure having curved grating lines arranged on the substrate, the grating structure having a second refractive index n1, wherein the curved grating lines have line width w and height d and are arranged by a pitch Λ, wherein the second refractive index n2 is less than first refractive index n1, and a cladding layer configured to cover the grating structure, wherein the cladding layer has a third refractive index n3.

Claims

1. An integrated grating coupler comprising: a grating coupler formed on a first chip, the grating coupler having first and second ends for coupling a light beam to a waveguide of a second chip, wherein the grating coupler comprises: a substrate configured to receive the light beam from the first end and transmit the light beam through the second end, the substrate having a first refractive index n1; a grating structure having grating lines arranged on the substrate, the grating structure having a second refractive index n2, wherein the grating lines have line width w and height d and are arranged by a pitch Λ, wherein the second refractive index n2 is greater than first refractive index n1, wherein the grating structure is configured to maintain a diffraction angle of the light beam from the second end in a range between 33 degree and 90 degree; and a cladding layer configured to cover the grating structure, wherein the cladding layer has a third refractive index n3, wherein the third refractive index n3 is less than the second refractive index n2; and a gain region connected to the first end of the grating coupler either directly or through a waveguide, wherein the laser structure comprises: a substrate identical to a substrate of the grating coupler; an active layer having a first thickness d1, the active layer being arranged on the substrate, wherein the active layer is connected to the grating structure of the grating coupler; and an upper cladding layer arranged on the active layer, wherein the upper cladding layer having a second thickness d2 is connected to the cladding layer of the grating coupler.

2. The integrated grating coupler of claim 1, wherein the active layer consists of a multiple quantum well structure.

3. The integrated grating coupler of claim 1, wherein the grating structure further includes a guide layer to form a grating geometry connecting the grating lines on the guide layer, wherein the guide layer having a thickness d is arranged on the substrate.

4. The integrated grating coupler of claim 3, wherein the grating structure further includes sub-gratings having line width w2 and the height d and a second pitch Λ2, wherein the pitch Λ is greater than the second pitch Λ2, wherein the sub-grating lines are arranged on at least one side of each of the grating lines.

5. The integrated grating coupler of claim 1, further comprising an end anti-reflection film arranged on the second end.

6. The integrated grating coupler of claim 1, wherein the gain region includes a wavelength selective reflector combined with the active layer.

7. The integrated grating coupler of claim 1, wherein the gain region further comprises first and second electrodes, wherein the first electrode is electrically connected to the laser-cladding layer, wherein the second electrode is electrically connected to a surface of the first chip or a surface of the second chip.

8. The integrated grating coupler of claim 1, wherein the second chip includes a Si3N4 waveguide.

9. The integrated grating coupler of claim 1, wherein the grating structure includes a waveguide layer to form a grating geometry connecting the grating lines on the waveguide layer, wherein the waveguide layer having a thickness d is arranged on the substrate.

10. The integrated grating coupler of claim 1, wherein the pitch Λ is changed from the first end to the second end to focus the light beam on the waveguide of the chip according to a function of distances.

11. The integrated grating coupler of claim 1, wherein a ratio w/Λ between the line width w and the pitch Λ over is arranged to be approximately 0.5 for reducing a second order diffraction of the light beam from the grating structure.

12. The integrated grating coupler of claim 1, wherein the grating coupler includes an end anti-reflection film arranged on the second end.

13. The integrated grating coupler of claim 12, wherein the end anti-reflection film consists of at least two layers with different materials.

14. The integrated grating coupler of claim 1, wherein the grating coupler includes a dielectric film arranged on the cladding layer.

15. The integrated grating coupler of claim 1, wherein the third refractive index n3 of the cladding layer is approximately the same as the first refractive index n1 of the substrate.

16. The integrated grating coupler of claim 1, further comprising a second cladding layer arranged between the grating structure and the cladding layer, wherein the second cladding layer has a fourth refractive index n4, wherein the fourth refractive index n4 is less than the third refractive index n3.

17. The integrated grating coupler of claim 1, wherein the grating lines are elliptic grating lines arranged to focus the light beam to the waveguide of the chip.

18. The integrated grating coupler of claim 1, further comprising a second waveguide layer arranged on the substrate, wherein the grating lines of the grating structure are separately arranged above the second waveguide layer, wherein the grating lines of the grating structure are burred in the cladding layer.

19. The integrated grating coupler of claim 1, wherein the grating lines of the grating structure are separately arranged between the substrate and the cladding layer.

20. The integrated grating coupler of claim 1, wherein the substrate is an InP substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The presently disclosed embodiments will be further explained with reference to the attached drawings. The drawings shown are not necessarily to scale, with emphasis instead generally being placed upon illustrating the principles of the presently disclosed embodiments.

(2) FIG. 1 shows a cross-sectional view of the integrated grating coupler system according to the invention;

(3) FIG. 2A show the definition of two angles θ and θ.sub.a;

(4) FIG. 2B shows the calculated relationship between the waveguide effective refractive index and the diffracted light angles;

(5) FIG. 3A shows the simulated coupling efficiency between the two optical chips as a function of wavelength;

(6) FIG. 3B shows the simulated coupling efficiency with different silicon grating length (positions);

(7) FIG. 4A shows this invention containing sub-gratings;

(8) FIG. 4B shows the conventional gratings without sub-gratings;

(9) FIG. 4C shows the simulated coupling efficiency with and without sub-gratings;

(10) FIG. 4D shows a grating shape wherein both edges are slanted;

(11) FIG. 4E shows a grating shape wherein a slanted edge is on one side;

(12) FIG. 4F shows a grating with sub-gratings on one side;

(13) FIG. 4G shows a grating with sub-gratings with varied width and/or spacing;

(14) FIG. 5A shows a cross-sectional view of a grating etched directly onto the waveguide layer, with an optional dielectric film on the cladding layer;

(15) FIG. 5B shows a cross-sectional view of a grating above the waveguide layer;

(16) FIG. 5C shows a cross-sectional view of a grating written directly on the waveguide layer and a guide (separate confinement) layer covering the grating;

(17) FIG. 5D shows a cross-sectional view of a grating made of separated segments of a waveguide layer;

(18) FIG. 5E shows a cross-sectional view of a grating made of separated segments of a waveguide layer embedded in a separate confinement layer;

(19) FIG. 6 shows a cross-sectional view of a grating with multiple layers of anti-reflection dielectric films on the facet;

(20) FIG. 7 shows the simulated facet reflectivity as a function of incident angle, wherein no coating, one layer coating (Si.sub.3N.sub.4), and two layer coating (Si.sub.3N.sub.4 and SiO.sub.2 films) are applied;

(21) FIG. 8A show the cross-section view of the grating coupler system, wherein the grating lines are curved;

(22) FIG. 8B shows the top view of the grating coupler system of FIG. 8A, wherein the grating lines are curved. θ.sub.1 and θ.sub.2 are the angles for the concentric grating lines for the first and second chips, respectively;

(23) FIG. 9A show the cross-section view of the grating coupler system, where linear gratings are connected to the waveguides through tapered waveguides;

(24) FIG. 9B shows the top view of the grating coupler system of FIG. 9A;

(25) FIG. 10A shows a cross-sectional view of a grating coupler system, wherein a gain section, or a laser section (DFB or DBR laser) is attached to the first end;

(26) FIG. 10B shows a top view of a grating coupler system of FIG. 10;

(27) FIG. 11A shows a cross-sectional view of a grating coupler system configured as a tunable laser with an optical chip with a grating coupler integrated with an active section and wavelength selective reflector, attached on a second optical chip with a grating coupler and a wavelength selective reflector; and

(28) FIG. 11B shows a top view of a grating coupler system of FIG. 11A.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(29) The following description provides exemplary embodiments only, and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the following description of the exemplary embodiments will provide those skilled in the art with an enabling description for implementing one or more exemplary embodiments. Contemplated are various changes that may be made in the function and arrangement of elements without departing from the spirit and scope of the subject matter disclosed as set forth in the appended claims.

(30) Specific details are given in the following description to provide a thorough understanding of the embodiments. However, understood by one of ordinary skill in the art can be that the embodiments may be practiced without these specific details. For example, systems, processes, and other elements in the subject matter disclosed may be shown as components in block diagram form in order not to obscure the embodiments in unnecessary detail. In other instances, well-known processes, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring the embodiments. Further, like reference numbers and designations in the various drawings indicated like elements.

(31) Furthermore, embodiments of the subject matter disclosed may be implemented, by use of at least in part, or combinations of parts of the structures described below.

Overview of Embodiments of the Present Disclosure

(32) Optical coupling between two optical chips constitute the most important part of hybrid PICs. The easiness of alignment and high coupling efficiency are very important factors. Grating couplers offer these capabilities.

(33) There are multiple factors in achieving high coupling efficiency for this configuration.

(34) FIG. 1 shows a cross-sectional view of the integrated grating coupler system 100 according to the invention. The first optical chip (first chip) 105 is made on an InP substrated 110, containing an InGaAsP waveguide layer 130, InP cladding layer 120, and a first grating 140. The second optical chip (second chip) 145 comprises of a silicon substrate 150, a buried SiO.sub.2 layer (also called a BOX layer) 160, a silicon (Si) waveguide layer (also called silicon-on-insulator, or SOI) 170, and a SiO.sub.2 cladding layer 180, and the second grating 190 etched onto the silicon waveguide layer. The diffracted light in the first optical chip 105 propagates through the InP substrate 110 and the first optical chip facet 195, and is coupled into the grating 190 on the second optical chip 145.

(35) Here, the grating pitch Λ is the distance between the rising edges of the grating, w is the line width of the main tooth, and d is the thickness of the grating. In the first optical chip, grating diffracts light towards the substrate as a shallow angle, which is further diffracted at the chip fact to a steeper angle. The light is focused on the grating in the second chip and is guided to its waveguide. The operating wavelength of 1530-1570 nm, the typical grating pitch Λ is 5-15 μm, and the typical grating line width w is 10-60% of the grating pitch, depending on whether sub-gratings are included, or how the sub-gratings are designed. The typical grating thickness d is 0.2-1 μm.

(36) FIG. 2A show the definition of θ and θ.sub.a, wherein θ is the angle between the InGaAsP waveguide layer 210 and the diffracted light 220, and θ.sub.a is the angle between the facet normal 230 and the diffracted light 240 passing through the facet 250.

(37) FIG. 2B shows the relationship between the waveguide effective refractive index and the diffracted light angle θ and θ.sub.a, before and after facet diffraction, respectively.

(38) The relationship between the diffraction angle, refractive indices, and the grating pitch can be expressed as,

(39) $k_0{n}_{\mathrm{eff}}-n_s\cos \theta =m\frac{2\pi }{\Lambda }$
where Λ is the pitch of the grating, k.sub.0=2π/λ is the wave vector in vacuum, λ is the wavelength in vacuum, n.sub.eff is the effective refractive index of the waveguide, n.sub.s is the refractive index of the substrate, θ is the angle between the propagation direction within the waveguide and the diffraction angle as defined in FIG. 2A, and m is the order of diffraction. From practical point of view, first-order grating usually offers the highest coupling efficiency, so m=1 is used in this invention.

(40) The angle between the diffracted light into the air from the facet and the original waveguide propagation angle (facet normal) θ.sub.a as defined in FIG. 2B can be expressed as,
n.sub.s sin θ=sin θ.sub.a

(41) The diffraction angle from the grating in the first optical chip has to be in a certain range, typically 10° and 20° within the optical chip. If it is below 10°, the diffraction light from the chip facet is also shallow (less than ˜33°), and coupling to a second optical chip makes less efficient. On the other hand, if the emission angle is more than 20°, most of the light is reflected at the chip facet, making the coupling very inefficient. Therefore, it is important to keep the diffraction angle between 10 and 20 degrees. Assuming n.sub.s=3.169 for a typical InP at the wavelength of 1550 nm, n.sub.eff=3.244, and Λ=8.5 μm, we obtain θ=15.0° and θ.sub.a=55.1°.

(42) FIG. 2B shows a plot of diffracted angles before and after the facet from the original propagation direction (i.e., facet normal), with two grating pitches, i.e., Λ=8.5 μm and Λ=10.5 μm are used. Depending on the pitch of the grating, there is an optimal waveguide effective refractive index. In other words, the grating pitch typically needs to be between 5 μm and 15 μm.

(43) FIG. 3A shows the simulated coupling coefficient as a function of wavelength. The structural parameters are optimized such that the coupling coefficient for the wavelength range of 1530-1565 nm is maximized. The simulated coupling coefficient is 58.0% (−2.4 dB) at the peak, and >49% for the wavelength range of 1530-1565 nm.

(44) The optimized structure and the parameters are as follows. The InP side structure consists of 80 μm-thick InP substrate, 0.5 μm-thick InGaAsP (bandgap: 1.30 μm), 0.3 μm-deep etched grating, 0.47 μm-thick InP upper cladding layer, and 20 nm-thick SiO.sub.2 passivation layer. The length of the InP grating section is 200 μm. In order to achieve shallow diffraction angle (15.0° within InP and 55.1° in the air) the initial pitch of the main grating in the left hand size is 8.5 μm. Further, in order to achieve focusing effect, the grating pitch is varied as a function of distance (linear pitch reduction: 0.1 μm per period). The grating has main teeth (width is 28% of the pitch) and 3 periods of sub-gratings with 210 nm width and 220 nm spacing on each side of the main teeth. Sub-gratings are gratings whose period is smaller than the main grating. The grating is also apodized in that the width of the etched part is linearly shrunk for each period. The facet has a pair of SiO.sub.2 and Si.sub.3N.sub.4 coating. In the silicon side, we used two pairs (Si/SiO.sub.2) of distributed Bragg reflectors (DBR) under the silicon waveguide. The 0.22 μm-thick silicon waveguide is sandwiched between a 2.1 μm-thick SiO.sub.2 lower cladding layer and a 1.04 μm-thick SiO.sub.2 upper cladding layer. The silicon grating depth is 87.5 nm. The length of the silicon grating section, starting from the end of the InP chip, is 32 μm. The silicon grating is apodized but does not have chirp.

(45) FIG. 3B shows the simulated coupling efficiency when the silicon grating section length (i.e., the endpoint measured from the edge of the InP chip facet). When the wavelength is at 1560 nm, the coupling efficiency changed within ±5% when the length changed by ±1.5 μm (29-32 μm). This is in contrast to typical chip-to-chip direct coupling, where submicron alignment accuracy is required.

(46) Grating diffracts light in multiple direction corresponding to the Fourier component of the diffraction grating. For example, third and fifth order diffraction, which do not contribute to the coupling efficiency, are related to the third and fifth order component of the grating. Therefore, it is important to reduce those components by effectively smoothing the grating. Sub-gratings, whose line width w.sub.2 and pitch Λ.sub.2 are much smaller than w and Λ, respectively, can be added on at least one side of the main (primary) grating (FIG. 4A). The typical w.sub.eff/Λ is 0.4-0.6. the typical sub-grating line width w.sub.2 is 0.02-0.3 μm, and typical sub-grating pitch Λ.sub.2 is 0.04-0.6 μm,

(47) Also, the second Fourier component needs to be minimized. The duty cycle (w/Λ), needs to be close to 0.5 in the case of a primary grating without sub-gratings (FIG. 4B). In the case of FIG. 4A, the effective duty cycle, w.sub.eff/Λ, where w.sub.eff is the effective line width of the grating, i.e., adding w of the main grating and cumulative w.sub.2 from all the subgratings.

(48) FIG. 4C shows the simulated coupling efficiency with and without sub-gratings, wherein the duty cycle is optimized in each case. It is clearly shown that sub-gratings show much higher coupling efficiency due to reduced diffraction in unnecessary directions.

(49) The grating geometry does not necessarily have to be rectangular. Third and fifth-order diffraction can also be suppressed by incorporating gratings with slanted edges, such as shown in FIG. 4D.

(50) Suppressing the upward diffraction also increases downward diffraction which more efficiently couples into the grating on the second chip. This can be achieved by slanting one of the edge of the gratings as shown in FIG. 4E, incorporating sub-gratings on one side of the grating (FIG. 4F), or asymmetric sub-grating on each side of the grating (FIG. 4G).

(51) FIG. 5A shows an example of the grating coupler of the first optical chip 540, wherein the grating 515 is etched into the InGaAsP waveguide layer 515 in the second refractive index, and is surrounded by an InP substrate 500 and an InP cladding layer 505 both of the first refractive index. This first optical chip can optionally have a SiO.sub.2 or Si.sub.3N.sub.4 dielectric layer 520 on top of an InP cladding layer 505. The grating 515 typically diffracts light in both upward and downward directions with similar intensity. Because of the shallow emission angle (10°-20°) in the first optical chip 540, the upward diffracted light 535 is very efficiently reflected either at the cladding layer—dieletric layer interface 525, or at the dielectric—air interface 530, and it is important not to disturb the surface. Therefore, flat interfaces 525 and 530 are desirable and thickness of the cladding layer 505 and the dielectric layer 520 needs to be chosen such that the reflected beam is combined with the originally downward diffracted light with the same or very similar phase. Metal surface absorbs light and is not desirable.

(52) A grating does not have to be directly etched into the waveguide layer. FIG. 5B shows an example wherein another InGaAsP layer of the third refractive index 545, above the waveguide layer 510 forms a grating. In this case, the grating height is determined by the thickness of the grating layer and not the etching depth, thus improving the process robustness.

(53) FIG. 5C shows an example wherein an InGaAsP separate confinement layer 550 of the third refractive index covers the grating etched into the waveguide layer. The refractive index difference between the separate confinement layer 550 and the InGaAsP waveguide layer can be smaller than the case depicted in FIG. 5A, thus improving the process robustness due to less sensitivity to the etch depth.

(54) FIG. 5D shows an example wherein the InP substrate 500 and the InP cladding layer 505 of the first refractive index surrounds the InGaAsP waveguide layer 510 of the second refractive index, which is fully etched into grating segments 555. Since this creates unguided light between the grating segments 555, and mismatch to the guided mode within the grating segment 555 is large, thus creating a very strong grating and is adequate for short length grating region.

(55) FIG. 5E shows a case wherein an InP substrate 500 and an InP cladding layer 505 of the first refractive index surrounds an InGaAsP separate confinement layer 550 of the third refractive index, wherein an InGaAsP waveguide layer 510 with the second refractive index is fully etched and is buried. In this case, the optical confinement is mainly determined by the separate confinement layer and the grating strength is determined by the thickness of the waveguide layer, so the emission angle and coupling efficiency is robust to etching process variation.

(56) FIG. 6 shows the schematic of a first optical chip 600, comprising of a chip facet 610, the first dielectric film 620, and the second dielectric film 630. The optical beam impinging on the chip facet 610 is not normal to the surface, but is 10° to 20° described above. Therefore, dielectric films 610 and 620 have to be optimized for the incident angle, such as two layers or more.

(57) FIG. 7 shows the calculated transmittance of TE mode input as a function of incident angle, wherein there is one layer (Si.sub.3N.sub.4) coating, two layer (Si.sub.3N.sub.4 and SiO.sub.2), or no coating. The thicknesses of Si.sub.3N.sub.4 (first dielectric film) and SiO.sub.2 (second dielectric film) are optimized for 15° incident angle. One layer coating is effective in suppressing reflectivity at a certain angle, while two layer coating is effective in lowering reflectivity in a broad angle range. It is shown that reflectivity increases significantly above 16° incident angle. The exact behavior depends on the coating design, however, it is best to keep the incident angle below ˜20°.

(58) The emitted beam diverges in the horizontal direction along the propagation despite of relatively long gratings, typically 50 μm or longer. It is therefore important to use chirped grating, i.e., gradually changing the pitch Λ of the grating along the propagation direction, thereby focusing the beam onto a narrow region of the grating on the second chip.

(59) In order to make the emitted beam closer to the beam shape (such as Gaussian beam) more suitable for coupling into the second grating, the grating strength can be altered along the propagation direction, also called apodized grating.

(60) The emitted beam also diverges in the lateral direction, that is, in the horizontal direction normal to the propagation direction.

(61) One way to narrow the lateral beam divergence is to use curved gratings, such as elliptic grating. FIGS. 8A and 8B show a cross-sectional view and a top of the grating coupler system 800, respectively, wherein the first optical chip 810 and second optical chip 830 have elliptical gratings 820 and 840, respectively. In one example, an InP waveguide 815 with around 1 μm width is connected to the elliptic grating 820 with at least 10° in full width. A silicon waveguide 835 with 0.5 μm width is also connected to an elliptic silicon grating 840.

(62) The most common way is to define elliptic curves is to follow the equation
qλ.sub.0=n.sub.eff√{square root over (y.sup.2+z.sup.2)}−zn.sub.t cos θ.sub.c.

(63) Here, z is the coordinate in the propagating direction, y is that in the lateral direction, q is an integer number for each grating line, θ is the angle between the outgoing/incoming light and the chip surface, n.sub.t is the refractive index of the environment, λ.sub.0 is the vacuum wavelength, and n.sub.eff is the effective index felt by the wave in the waveguide with the grating. In the center (y=0), the grating lines are determined by the previously described methods whose cross-sections are described in FIGS. 4 and 5.

(64) Alternatively, we can use tilted grating so that the reflected light will not couple back into the original waveguide.

(65) The above equation is derived to generate a circular beam. In this grating coupler system 800, due to the diffraction at the facet, a circular beam becomes an elliptical beam. Therefore, further modification to the grating lines 820 may be desirable to form a near circular beam observed at the grating 840 at the second optical chip.

(66) Another way of narrowing the lateral beam divergence is to use tapered waveguide. FIGS. 9A and 9B show a cross-sectional view and a top of the grating coupler system 900, respectively, wherein the first optical chip 910 and second optical chip 930 have elliptical gratings 920 and 940, respectively. In one example, an InP waveguide 915 with ˜1 μm width is tapered to the width to 5-20 μm, and then it is connected to a linear InP grating 920, whose cross-section is defined in FIGS. 4 and 5. The length of the taper section can be 5-100 μm. The grating on the second chip 930 can be a linear width grating 940. Alternatively, it can be an elliptical grating 840 such as shown in FIG. 8B.

(67) It is also important to increase the coupling efficiency for the grating in the second chip, typically based on silicon substrate, and silicon waveguide is sandwiched between two SiO.sub.2 layers. There are many ways to increase it.

(68) Bragg reflector (a pair of layers with different refractive indices) between the silicon substrate and the bottom of the SiO.sub.2 layer. Subgrating on at least one side of the main grating teeth. Silicon amorphous layer above the upper SiO.sub.2 cladding layer. Metallic layer between the silicon substrate and the bottom of the SiO.sub.2 layer.

(69) Alternatively, a Si.sub.3N.sub.4 waveguide, sandwiched between two SiO.sub.2 layers, can also be used for guiding the incoming light. Also, a SiO.sub.2 substrate can be used for the second optical chip

(70) In one embodiment of the invention, the grating coupler system 1000 can comprise of a first optical chip with a waveguide 1020 and a grating 1050 connected to a gain region 1035 comprising of an active layer 1030 such as a multi quantum well (MQW) structure (FIGS. 10A and 10B). MQW structure is a very efficient gain medium. The light generated or amplified in the gain region 1035 through a current injection provided by the electrode 1040 can be guided to the grating coupler 1050 to be coupled to the second optical chip 1060. The gain region can also be part of a DFB or a DBR laser, wherein the laser light is generated. In this case, a substrate of DFB or a DBR laser may be identical to the substrate of the grating coupler system 1000.

(71) FIGS. 11A and 11B show a cross-sectional view and a top of a tunable laser based on an integrated grating coupler system 1100, respectively, wherein the first optical chip 1110 and second optical chip 1150 form the laser cavity. In this case, a wavelength selective reflector 1115, whose refractive index is controlled by temperature or injected carrier through the first electrode 1120, an active section 1125 comprising of an MQW structure with current injected through the second electrode 1130, a grating coupler 1135, and a third electrode 140 are on a first optical chip 1110, formed on a substrate made of materials such as InP, GaAs, or GaN. A second optical chip 1150 comprises of a silicon substrate, BOX layer 1155, silicon and/or silicon nitride waveguide 1160, a grating coupler 1165, and a wavelength selective reflector 1170 whose refractive index can be controlled by temperature or injected carrier through a second pair electrodes 1175 and 1185. A phase controller can be on either chip. In FIG. 11B, a ring resonator is depicted as an example of a wavelength selective mirror, however, it can also be a sampled grating distributed Bragg reflector. These wavelength selectable mirrors have multiple reflection peaks, wherein the peak wavelengths can be tuned by the injected current, applied reverse bias voltage, or temperature controlled by a heater.

(72) According to aspects of integrated grating coupler system described above, with respect to the integrated grating coupler system, a ratio w/Λ between the line width w and the pitch Λ over can be arranged to be approximately 0.5 for reducing a second order diffraction of the light beam from the grating structure.

(73) Further, a dielectric film may be arranged on the cladding layer, and the substrate of the first chip may be an InP substrate. Also in some cases, the substrate of the second chip can be a Si substrate, the second chip may include a Si waveguide, and the first wavelength selectable reflector may include a sampled grating Bragg reflector.

(74) Although the present disclosure has been described with reference to certain preferred embodiments, it is to be understood that various other adaptations and modifications can be made within the spirit and scope of the present disclosure. Therefore, it is the aspect of the append claims to cover all such variations and modifications as come within the true spirit and scope of the present disclosure.