Organic Thin Film Transistor and Method for Producing Same
20210391549 · 2021-12-16
Inventors
Cpc classification
H10K10/482
ELECTRICITY
H10K10/464
ELECTRICITY
International classification
Abstract
An organic thin film transistor (OTFT), in particular thin-film field-effect transistor (OFET), that includes a substrate, a source electrode, a drain electrode, a gate electrode arranged in a top gate arrangement, and an organic semiconductor functional layer. The source electrode, the drain electrode, and the gate electrode are arranged in a coplanar layer structure. The organic thin-film transistor has an intermediate layer for the capacitive decoupling of the gate electrode from the source electrode and/or from the drain electrode.
Claims
1. An organic thin film transistor comprising: a substrate, a source electrode, a drain electrode, a gate electrode arranged in a top gate arrangement, and an organic semiconductor functional layer, wherein the source electrode, the drain electrode, and the gate electrode are arranged in a coplanar layer structure, and wherein the organic thin film transistor comprises an intermediate layer for capacitive decoupling of the gate electrode from the source electrode and/or from the drain electrode.
2. The organic thin film transistor according to claim 1, wherein the organic semiconductor functional layer is arranged between the gate electrode and the substrate.
3. The organic thin film transistor according to claim 1, wherein the intermediate layer is arranged below or above the gate electrode.
4. The organic thin film transistor according to claim 1, wherein the intermediate layer, perpendicular to a main plane of extent of the substrate, at least partly overlaps both the drain electrode and the source electrode in a direction perpendicular to a main plane of extension of the substrate, wherein the intermediate layer has an interruption in a region of the gate electrode.
5. (canceled)
6. (canceled)
7. The organic thin film transistor according to claim 1, wherein the intermediate layer has a polymer-based spacer layer.
8. (canceled)
9. A display comprising a multiplicity of pixels, wherein at least one pixel comprises the organic thin film transistor according to claim 1.
10. (canceled)
11. A method for producing the organic thin film transistor according to claim 1, wherein: in a first production step, an organic semiconductor material is deposited on a substrate, for forming the organic semiconductor functional layer, in a second production step, a first metal layer is arranged on the organic semiconductor material, in a third production step, the first metal layer is structured for forming at least one first electrode, in a fourth production step, a second metal layer is deposited, in a fifth production step, the second metal layer is structured for forming at least one second electrode, wherein in an additional step carried out between the first and the second production steps or between the third and the fourth production steps, a gate insulation layer is produced, wherein in an intermediate step an intermediate layer is applied to the at least one first electrode or to the at least second electrode for the capacitive decoupling.
12. The method according to claim 11, wherein between the first step and the second step, an organic functional layer is arranged on the semiconductor functional layer, completely covering the semiconductor functional layer, wherein the functional layer is partially removed between the third step and the fourth step.
13. The method according to claim 12, wherein after the functional layer has been partially removed, defects are annealed by means of a thermal treatment, wherein the thermal treatment is carried out between the partial removal of the functional layer and the fourth step.
14. The method according to claim 11, wherein the intermediate step is carried out between the second and fourth production steps and in particular between the third and fourth production steps.
15. The method according to claim 11, wherein the intermediate step is carried out before or after the additional step and preferably comprises applying a polymer-based spacer layer.
16. The method according to claim 15, wherein the intermediate step comprises applying photoresist in the third production step and the photoresist remains contained in the layer structure as an intermediate layer for capacitive decoupling in a region of the at least one first electrode.
17. The method according to claim 11, wherein in the additional step a wet-chemical anodization of the first metal layer is carried out for forming the gate insulation layer, in the form of an aluminum oxide layer.
18. (canceled)
19. The method according to claim 11, wherein the intermediate step comprises applying photoresist in the third production step and the photoresist remains contained in the layer structure as an intermediate layer for capacitive decoupling in the region of the source and drain electrodes.
20. The method according to claim 11, wherein in the second production step, a double layer composed of aluminum and gold is arranged on the organic semiconductor material as a first metal layer, wherein in the third production step the gold layer of the double layer is photolithographically patterned, and wherein in the additional step the aluminum layer of the double layer is anodized for forming the gate insulation layer.
21. (canceled)
22. (canceled)
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0036]
[0037]
[0038]
[0039]
[0040]
[0041]
DETAILED DESCRIPTION
[0042] In the various figures, identical parts are always provided with the same reference signs and, therefore, are generally also referred to or mentioned only once in each case.
[0043]
[0044] The organic thin film transistor (OTFT) 1 comprises a substrate 2, on which is arranged an organic semiconductor material for forming an organic semiconductor functional layer 4. Optionally, an auxiliary layer 3 for planarizing the substrate 2 is provided between the organic semiconductor functional layer 4 and the substrate 2. In this case, the substrate 2, the auxiliary layer 3 and the layer composed of organic semiconductor material 4 extend parallel to a main plane of extent 10.
[0045] A source electrode 5 and a drain electrode 6 composed of metal are formed in a manner spatially separated from one another on the organic semiconductor material 4. In the main plane of extent 10 a gate insulation layer 7 is formed between the source electrode 5 and the drain electrode 6 in order to electrically insulate the organic semiconductor functional layer 4 from a gate electrode 8.
[0046] In the region of the source electrode 5 the organic thin film transistor 1 comprises an intermediate layer 9, which serves to obtain a capacitive decoupling between the source electrode 5 and the gate electrode 8. For this purpose, the intermediate layer 9 completely covers the source electrode 5 along a direction perpendicular to the main plane of extent 10. In other words: the intermediate layer 9 and the source electrode 5 completely overlap one another. Analogously, an intermediate layer 9 is also arranged in the region of the drain electrode 6, said intermediate layer completely overlapping the drain electrode 6 and serving to obtain a capacitive decoupling between the drain electrode 6 and the gate electrode 8. The gate insulation layer 7 extends laterally in each case across the intermediate layer 9. Furthermore, the gate electrode 8 is arranged on the gate insulation layer 7, said gate electrode likewise both extending over the active region of the transistor and projecting laterally slightly over the source and drain electrodes 5, 6. This overlap inevitably gives rise to unwanted parasitic capacitances between the source electrode 5 and the gate electrode 8 and/or between the drain electrode 6 and the gate electrode 8.
[0047] The intermediate layer 9 comprises a preferably polymer-based spacer layer (alternatively, oxides, nitrides or small molecule layers would also be conceivable as spacer layer), which can be for example a non-removed photoresist from a preceding photolithographic patterning method for patterning the source and drain electrodes 5, 6. The intermediate layer 9 functions as a spacer and for this purpose preferably has a thickness of between 500 nm and 5 μm. In comparison with the typical thickness of the gate insulation layer 7 of between 50 nm and 500 nm, the intermediate layer 9 is therefore comparatively thick, such that the parasitic capacitances between the source electrode 5 and the gate electrode 8 and/or between the drain electrode 6 and the gate electrode 8 advantageously become very small in comparison with the capacitance of the active gate region. Consequently, the unity-gain cut-off frequency f.sub.T can be increased and the “voltage kickback” (VKB) effect can be reduced, as a result of which the organic thin film transistor 1 according to the invention becomes faster and more energy-efficient and can find application for example in high-definition active matrix displays.
[0048] A further advantage of the organic thin film transistor 1 according to the invention is that the electrodes can be formed by means of a conventional photolithographic patterning with subsequent wet-chemical anodization, without the organic semiconductor material incurring damage in the process. The production of the organic thin film transistor 1 according to the invention can thus be effected in the manner of self-patterned electrodes, as a result of which low parasitic capacitances and cost-effective production are made possible.
[0049] The organic thin film transistor 1 shown in
[0050] In a second production step, subsequently a first metal layer, for example composed of gold, is applied to the organic functional layer 4, for example by means of physical vapor deposition (PVD), or vapor deposition. In the third production step, said first metal layer is patterned by means of conventional photolithographic patterning, as a result of which the source electrode 5 and the drain electrode 6 are formed. For this purpose, the metal layer is firstly coated with a photoresist as masking layer, subsequently exposed and then etched wet-chemically (aqueous solution) in such a way that the underlying semiconductor does not incur any damage. For noble metals such as gold or silver, for example, this etching step can be carried out by means of KI/I2 solution or aqua regia. For copper, metal chloride salt solutions composed of e.g. NaCl, CuCl2, MgCl2 or the like are suitable. Said salt solutions preferably contain hydrogen chloride (HCl). Base metals such as Al, for example, can be etched using basic solutions such as NaOH or tetramethylammonium hydroxides. The concentrations of the respective substances in an aqueous solution determine the etching rate. In order that the lithographic structures are transferred with structural fidelity, it is recommended to use diluted etching solutions: e.g. KI/I2 diluted with H2O (ratio 1:10), or aqua regia diluted with H2O (ratio 1:10). In a succeeding additional step, the gate insulation layer 7 is formed by applying a thin insulating polymer layer, which is applied by printing or spin coating, for example. Alternatively, insulation layers composed of aluminum, titanium or hafnium oxide, for instance, are also conceivable.
[0051] In order to form the intermediate layer 9, either the photoresist in the region of the source and drain electrodes 5, 6 is not removed after the third production step, such that the photoresist subsequently functions as intermediate layer 9 for capacitive decoupling. The intermediate step thus comprises that partial step of the third production step in which the photoresist is applied. Alternatively, an intermediate step for applying a polymeric spacer layer is carried out after the third production step, said layer constituting the intermediate layer 9. The intermediate step is carried out either before or after the additional step.
[0052] Afterward, in a fourth production step a second metal layer is applied, which is photolithographically patterned in order to form the gate electrode 8 in a fifth production step.
[0053] It is optionally conceivable for the organic semiconductor material additionally to be doped in the region of the source and drain electrodes 5, 6, in particular by means of molecular dopants, such as F4-TCNQ, F6-TCNNQ, C60F36, W2(hpp)4, or inorganic dopants, such as WoO3, MoO3.
[0054]
[0055] The second embodiment substantially corresponds to the first embodiment explained with reference to
[0056] This second embodiment is produced analogously to the first embodiment, with the additional step being carried out before the second production step in order to produce the gate insulation layer 7 below the gate electrode 8 to be produced subsequently. Furthermore, the patterning of the first metal layer is carried out in the third production step in order to form the gate electrode 8. The patterning of the second metal layer in the fifth method step then serves for forming the drain and source electrodes (5, 6). For the patterning of the gate electrode (8), and also of source and drain, recourse is had to wet-chemical etching processes as described in the first embodiment. The process of wet-chemical oxidation is used for the production of the gate insulation layer 7. In this case, the gate electrode 8 consists of a wet-chemically oxidizable metal, or of a layer sequence of an oxidizable metal and a noble metal (e.g. aluminum and gold, cf. third embodiment).
[0057]
[0058] The third embodiment substantially corresponds to the first embodiment explained with reference to
[0059] In the third production step, photolithographic patterning of the gold layer is then carried out in order to form the source and drain electrodes 5, 6. The photoresist in the region of the source and drain electrodes 5, 6 is not removed and thus functions as an intermediate layer 9 in the form of the polymer-based spacer layer. In the succeeding fourth production step, by means of wet-chemical anodization of the aluminum layer uncovered in the third production step, the gate insulation layer 7 is formed in the form of an aluminum oxide layer (Al.sub.2O.sub.3). The thickness of the gate insulation layer 7 is again controlled by means of the electrical voltage applied during the anodization. A schematic detailed diagram of the wet-chemical anodization of the aluminum layer is illustrated in
[0060] Afterwards, in a fifth production step a metal layer is applied, which is photolithographically patterned in order to form the gate electrode 8 in a sixth production step.
[0061] The use of the double layer composed of aluminum and gold has advantages in particular for n-doped semiconductors since the drain and source electrodes 5, 6 are formed from aluminum.
[0062] Optionally, it is conceivable for the organic semiconductor material additionally to be doped in the region of the source and drain electrodes 5, 6, in particular by means of molecular dopants, such as F4-TCNQ, F6-TCNNQ, C60F36, W2(hpp)4, or inorganic dopants, such as WoO3, MoO3.
[0063]
[0064] In principle, in the past it has been assumed that organic semiconductor material is damaged during patterning by means of lithographic methods.
[0065] Therefore, the organic thin film transistor 1 illustrated in
[0066] In order to check whether the organic semiconductor material is actually damaged by the lithographic patterning of the metal layers, in the case of the test structure the charge carrier mobility in the region of the gate electrode 8 was then compared with the charge carrier mobility in the region of the further gate electrode 12. The measurement results are illustrated as measurement series 11 in
[0067] The result is that the charge carrier mobility was not impaired by the lithographic patterning. It has thus been discovered that some metals can be patterned directly on the organic semiconductor by means of wet etching, without the organic semiconductor material therefore being impaired.
[0068]
LIST OF REFERENCE SIGNS
[0069] 1 Organic thin film transistor [0070] 2 Substrate [0071] 3 Auxiliary layer for planarization [0072] 4 Organic semiconductor functional layer [0073] 5 Source electrode [0074] 6 Drain electrode [0075] 7 Gate insulation layer [0076] 8 Gate electrode [0077] 9 Intermediate layer [0078] 10 Main plane of extent [0079] 11 Measurement series [0080] 12 Further gate electrode [0081] 13 Further gate insulation layer [0082] 14 Functional layer