Use of Surface Patterning for Fabricating a Single Die Direct Capture Dental X-ray Imaging Sensor

Abstract

A device and process in which a single continuous depositional layer of a polycrystalline photoactive material is deposited on an integrated charge storage, amplification, and readout circuit with an irregular surface wherein the polycrystalline photoactive material is comprised of a II-VI semiconductor compound or alloys of II-VI compounds.

Claims

1. A device comprised of an integrated charge storage, amplification, and readout circuit serving as a depositional substrate with an irregular surface; and a polycrystalline photoactive material deposited as a single continuous depositional layer on top of the irregular surface; wherein the polycrystalline photoactive material is comprised of a II-VI semiconductor compound or alloys of II-VI compounds and the irregular surface is comprised of variations in elevation; wherein the polycrystalline photoactive material has a thickness sufficient to provide quantum efficiency and spatial resolution based upon photo-electrical properties of the polycrystalline photoactive material.

2. The device of claim 1 wherein the integrated charge storage, amplification, and readout circuit is a thin film array.

3. The device of claim 1 wherein the integrated charge storage, amplification, and readout circuit is silicon-based.

4. The device of claim 1 wherein the II-VI semiconductor compound is selected from the group consisting of CdTe, Hg.sub.xCd.sub.(1-x)Te, and Zn.sub.xCd.sub.(1-x)Te.

5. The device of claim 4 wherein the II-VI semiconductor compound is CdTe.

6. The device of claim 5 wherein the thickness is greater than 10 microns.

7. The device of claim 5 wherein the thickness is 100 to 300 microns.

8. A process, comprising depositing a single continuous depositional layer of a polycrystalline photoactive material on an integrated charge storage, amplification, and readout circuit exhibiting an irregular surface; wherein the polycrystalline photoactive material is comprised of a II-VI semiconductor compound or alloys of II-VI compounds, the irregular surface is comprised of variations in elevation and single continuous depositional layer has a thickness sufficient to provide quantum efficiency and spatial resolution based upon photo-electrical properties of the polycrystalline photoactive material.

9. The process of claim 8 wherein the II-VI semiconductor compound is CdTe and the thickness is greater than 10 microns.

10. The process of claim 9 wherein the thickness is 100 to 300 microns.

11. A sensor useful for detecting X-ray photons comprised of: a silicon-based single die, charge storage, amplification, and readout pixel array integrated circuit serving as a depositional substrate with a surface exhibiting an irregular surface of a prescribed size; and a polycrystalline photoactive material deposited as a single continuous depositional layer on top of the integrated charge storage, amplification, and readout circuit; wherein the irregular surface is comprised of a non-planar surface with two or more elevations at a minimum difference of at least approximately 0.1 micron and a maximum difference of approximately 100 microns while the prescribed size has a distance of at least approximately 1 micron; and wherein the polycrystalline photoactive material is selected from the group consisting of CdTe, Hg.sub.xCd.sub.(1-x)Te, and Zn.sub.xCd.sub.(1-x)Te; and wherein the single continuous depositional layer has a total surface area which exceeds 500 square millimeters; and wherein the single continuous depositional layer has a thickness sufficient to provide quantum efficiency and spatial resolution based upon photo-electrical properties of the polycrystalline photoactive material

12. The sensor of claim 11 wherein the II-VI semiconductor compound is CdTe and the thickness is greater than 10 microns.

13. The sensor of claim 12 wherein the thickness is 100 to 300 microns.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIGS. 1 and 1A are a whole wafer and close-up schematic view, respectively, which illustrate a sample textured depositional surface used in accordance with the present invention.

[0017] FIG. 2 is a micrograph (100x) of CdTe film surface on a wafer at one corner of the repeating pattern illustrated in FIG. 1. FIG. 3 is a macroscopic view showing enhancement of adhesion of CdTe (gray areas) in square regions of patterning (3 mm×3 mm) similar to that shown in FIG. 1 and delamination or peeling of CdTe over un-patterned regions (shiny areas).

[0018] FIG. 4 illustrates an example of a CMOS circuit substrate for deposition (circuit components and layer thicknesses not drawn to scale). Insulation between pixels creates a repeating surface pattern consisting of alternating elevations and materials similar to that shown in FIG. 1.

[0019] FIG. 5 is a scanning electron micrograph (SEM) of a wafer cut in cross-section through specially prepared troughs exhibiting undercut walls (0.25 microns as shown) down into the silicon substrate.

[0020] FIG. 6 illustrates a completed X-ray imager with photoactive material directly deposed on the patterned surface of example CMOS circuit (circuit components and layer thicknesses not drawn to scale).

DETAILED DESCRIPTION OF THE INVENTION

[0021] The present invention challenges the current wisdom that circuit substrates be smooth and defect free. This stems from a number of requirements including epitaxial growth, limitations in masking technology, circuit continuity, chip bonding, etc. The present invention provides a means of creating a sufficiently thick layer of photoactive material, preferably polycrystalline cadmium telluride (CdTe) directly on the surface of an integrated circuit, preferably a silicon based integrated circuit (e.g. CMOS, CCD, TFT). The photoactive material is in direct electrical contact with the pixel circuitry below. The current invention employs an alternate circuit substrate surface structure that facilitates the deposition of a high Z photoactive material onto the surface of the integrated circuit in a single chip architecture at relatively low substrate temperatures, i.e. below 350 degrees C., to avoid any possible degradation of the readout electronics. This avoids the more complex process of fabricating the different layers separately and then bonding them together, thus reducing fabrication costs and complexity, and increasing durability by having fewer bonded components.

[0022] The current invention intentionally creates an irregular (‘bumpy’) surface of an integrated circuit, preferably silicon based, as the depositional substrate of a high Z photoactive material, preferably polycrystalline II-VI semiconductor compounds and their alloys such as CdTe, Hg.sub.xCd.sub.(1-x)Te, Zn.sub.xCd.sub.(1-x)Te, and A.sub.xB.sub.(1-x)C generically. The irregularities consist of variations in elevation. The boundary of different elevations serves as attractive seeding locations for crystal formation and anchoring, therefore improving adhesion, due to increased points of contact which enhances Van der Waals or other attractive forces. The optimal spacing of the boundary interfaces need to be determined experimentally based on the materials used and the depositional conditions. The current invention is therefore an alternative to the use of a separate intermediate layer between the integrated circuit and the photoactive material to enhance adhesion.

[0023] A set of experiments were conducted to test the general theory on silicon wafers whose surfaces were specially prepared to present variations in surface height with a regular spacing. A standard silicon wafer with a 1-micron thick layer of SiO.sub.2 created on the surface was used. Note, that in this experiment the irregular surface was heterogenous in composition, yet the concept of enhanced attraction still pertains. Square pits were etched through the SiO.sub.2 layer down to bare silicon to a depth of 1 micron or slightly greater. The pits were arranged in a rectangular grid and created a “waffle” like appearance, a small sub-section, a sample of which is illustrated in FIG. 1A. In this sample the entire “waffle” structure was 2 cm by 2 cm with 20 micron spacing between the square pits, there being a repeating pattern of insulating walls (in this sample 5 microns wide and 1 micron high) surrounding square pits (in this sample 15 microns by 15 microns and 1 micron deep) with conductive floors. The surface of the bottoms of the “waffle” pits consisted of pure silicon but the walls between the waffle pits consisted of SiO.sub.2. Samples of grids with different pit sizes and spacings were created.

[0024] CdTe films were then deposited upon these surfaces according the following protocol. First the wafers were cleaned by standard semi-conductor cleaning techniques ending in a BOE etch. Immediately after BOE etch the samples were placed into a thermal evaporation chamber. The background chamber was between 10.sup.−5 and 10.sup.−6 Torr. Argon gas was then introduced into the chamber to approximately 4×10.sup.−1Torr and a plasma discharge was initiated for final cleaning. Subsequently background pressure was again reduced to a range between 10.sup.−5 and 10.sup.−6 Torr. Immediately after cleaning CdTe deposition was performed at a prescribed substrate temperature and deposition rate. A series of runs were performed in which films were deposited at substrate temperatures of 100, 150, and 200 degrees C. and at deposition rates of approximately 2, 5, 10 and 15 minutes per micron. The CdTe source was sublimated by a variable output radiant heat source. Deposition rates were monitored by an IR interferometer. Films as thick at 70-80 microns were produced and this was accomplished at substrate temperatures considerably below the 350 degrees C. temperature considered safe for silicon-based circuitry.

[0025] In another set of experiments, it was discovered that pit spacings of approximately 100 microns or less exhibited enhanced adhesion (no pealing) and crack resistance, with no further advantage at less than 20 microns spacing. FIG. 2 shows examples of cracks originating in a non “waffle” region of the wafer propagating to the first of the waffle pits only and going no deeper into the pattern. In this case a crack originating in the un-patterned region proceeds into the first pit on the edge of the pattern and continues at the outer edge but proceeds no deeper into the patterned region. This behavior was a general result indicating that the pattern increased adhesion but also terminated cracks. Significant pealing was observed in the un-patterned areas. Months after deposition the films remained stable over the patterned regions for both sets of experiments.

[0026] These experiments suggest a modification of X-ray sensor integrated circuit design that will take advantage of this phenomenology. This is illustrated in FIG. 3 showing in cross section the circuitry for two adjacent pixels. By standard fabrication techniques pixel circuitry can be created within the surface of a silicon wafer that includes all the components of a typical visible light imager except the photodetector component. Instead, a conductive path is created from the charge storage component to the surface of the wafer creating a conductive region within the surface of each pixel. To protect underlying circuitry and prevent electrical shorts between adjacent conductive regions insulating walls are created between the conductive regions. This can be easily created by depositing a continuous layer of insulating material such as SiO.sub.2 over the entire wafer surface and then etching isolated pits down to the conductive regions resulting in a pattern as shown in FIG. 1.

[0027] Further, the etching of the SiO.sub.2 can be modified with techniques to purposefully create undercuts in the walls of the “waffle” pits to create mechanical retention, significantly increasing adhesion beyond that created by van der Waals forces alone. FIG. 5 shows a SEM of a specially prepared wafer sample in which undercut walls have been created. Such undercuts create mechanical retention for the photoactive material deposited on this surface. This specific sample was created using a combination anisotropic and isotropic dry etching techniques on a silicon wafer with a surface coating of SiO.sub.2. In this example, an anisotropic etching technique was first used to etch preferentially vertically down to the silicon layer. Then, an isotropic etching technique, that was selective for pure silicon, was used to etch laterally as well as downward. The lateral component of this second etching created an undercut into the pure silicon and under the etch resistant SiO.sub.2. In general, undercuts can be created by exploiting differences in etching rates of the different structural layers of a wafer and by exploiting combinations of anisotropic versus isotropic etching techniques.

[0028] Note that in the specially prepared sample shown, troughs rather than pits were used. This was to ensure that the wafer could be reliably sectioned at right angles through a wall to show the undercuts in a SEM of the cross section. Similar undercuts would be created for pits as well.

[0029] The structure shown in FIG. 4 then serves as the substrate upon which to directly deposit the photoelectrically material in electrical contact with each conduction region in the array with the completed structure looking something like FIG. 6. In a preferred embodiment this material will be polycrystalline CdTe or one of its alloys (such as CdTe, Hg.sub.xCd.sub.(1-x)Te, Zn.sub.xCd.sub.(1-x)Te). This layer is grown to the appropriate thickness depending upon photoelectrical properties of the material. For CdTe, for example, 100 to 300 microns provides sufficient quantum efficiency and spatial resolution. This layer is directly deposited on normal silicon charge storage, amplification, and readout electronics by a number of means including, but not exclusive to, thermal evaporation, argon beam sputtering, e-beam evaporation, and chemical deposition. In the preferred embodiment the resulting photodetectors are functioning as photodiodes whose resistance decreases proportionally under X-ray illumination. CdTe has the advantage of high resistance and hence low current leakage (dark current) when not under illumination and relatively higher resistance in the lateral (or tangential) direction due to its columnar polycrystalline structure, helping to reduce pixel cross talk.

[0030] Finally, a thin conductive contact (such as gold or other metallization) to the photodetector devices is created on the top surface of the photoactive layer. By applying an appropriate voltage bias to the conductive contact, the resulting electric field preferentially drives charges to the conduction regions below, before the charge pairs can be destroyed by recombination, and thus helps to reduce pixel cross talk. Note that the X-ray photons will easily pass through the thin conductive contact and produce electron-hole pairs within the photoactive material below. Accordingly, the conductive contact has a thickness sufficient to support an electric field to drive charges to the charge conduction region for each pixel, but not so thick as to prevent (sufficient) X-rays from passing through it.

[0031] In accordance with the present invention, it has been found that it is possible to grow CdTe under low substrate temperature conditions (less than 350 degrees Celsius substrate temperature) benign to CMOS electronics. In addition, the polycrystalline structure provides strain relief, which allows for growth on materials of very different lattice spacing, such as CdTe on silicon, and growth on top of irregular surfaces, such as the surface of a silicon substrate upon which electronic circuitry has been created.

[0032] Laboratory measurements have demonstrated that polycrystalline CdTe grown under such conditions retains much of the photoelectrical properties of the single crystalline form, demonstrating that crystal boundaries and other defects do not significantly degrade the electrical properties compared to the pure single crystalline form. For example, the impedance of samples of polycrystalline grown in labs was greater than 10.sup.6 ohms-cm, similar to that single crystal CdTe. In addition, testing was performed for pixel uniformity using three simplified thin film CdTe (2-5 microns) pixels under a flat field illumination at 60 kV (typical dental X-ray energy levels). After only calibrating for differences in gain and no other mitigation for readout noise, a ratio of mean intensity to standard deviation (i.e., SNR) of greater than 30:1 was obtained, which is comparable to that of traditional indirect capture devices.

[0033] It has also been demonstrated in the laboratory that X-ray photon capture efficiency for an array of pixels consisting of polycrystalline-based photoresistors grown on highly doped n-type silicon is comparable to that of conventional indirect-capture X-ray imaging chips. For example, in an initial experiment on 1 mm thick slices of polycrystalline CdTe under X-ray irradiation at 60 kV and a bias of 20 V, photon capture efficiencies were obtained of approximately 33% that of those for pure CdTe. The extremely high resistance of CdTe (greater than 10.sup.6 ohms-cm) means the current leakage under a voltage bias is low compared to photonic induced conduction. Also, because the interface of the photodetector with the conduction region forms a heterojunction, one can take advantage of the diode behavior to further reduce dark current. However, the present invention does not depend upon diode behavior because the dark current is highly predictable. And in radiographic applications, it is common practice to record both a ‘light’ and ‘dark’ image and then subtract the dark from the light image. Laboratory measurements of light to dark current ratios in excess of 6:1 have been achieved, a value comparable to conventional indirect-capture X-ray imaging chips.

[0034] The specific embodiment of the current invention exploits properties of polycrystalline CdTe that are found in II-VI compounds and their alloys, and that are not well appreciated by researchers in the field. Thus, the present invention is not restricted to CdTe, II-VI compounds and their alloys but also includes any other photoactive materials of similar properties; these properties include: 1) electrically benign behavior at crystal grain boundaries (i.e. no sites for charge recombination), 2) can be deposited on irregular surfaces and do not require epitaxy and, 3) such deposited films tend to be columnar in structure, biasing charge migration in the vertical direction. The current invention is a simple single die approach that involves the direct deposition of an X-ray sensitive material on conventional electronics which does not require a separate intermediate layer whose purpose is to enhance adhesion and does not require pure, single-crystal epitaxial growth.

[0035] The present invention includes, but is not limited to, the following specifically preferred devices:

1. A device comprised of an integrated charge storage, amplification, and readout circuit serving as a depositional substrate with a surface exhibiting an irregular surface; and a polycrystalline photoactive material deposited as a single continuous depositional layer on top of the integrated charge storage, amplification, and readout circuit; wherein the polycrystalline photoactive material is comprised of a II-VI semiconductor compound or alloys of II-VI compounds.

[0036] 2. Device 1 wherein the integrated charge storage, amplification, and readout circuit is a thin film array.

[0037] 3. Device 1 the integrated charge storage, amplification, and readout circuit is silicon based.

[0038] 4. Device 1 wherein the II-VI semiconductor compound is selected from the group consisting of CdTe, Hg.sub.xCd.sub.(1-x)Te, and Zn.sub.xCd.sub.(1-x)Te.

[0039] 5. Device 4 wherein the II-VI semiconductor compound is CdTe.

[0040] 6. Device 1 wherein the periodic pattern is comprised of a non-planar surface with two or more alternating elevations at a minimum of difference of at least approximately 0.1 microns.

[0041] 7. Device 1 wherein the periodic pattern is comprised of a non-planar surface with two or more alternating elevations at a maximum of difference of approximately 100 microns.

[0042] 8. Device 1 wherein the prescribed size has a distance of repetition of at least approximately 1 micron.

[0043] 9. Device 1 wherein the prescribed size has a distance of repetition of at most 100 microns.

[0044] 10. Device 1 wherein the single continuous depositional layer has a total surface area which exceeds 100 square millimeters.

[0045] 11. Device 1 wherein the single continuous depositional layer has a total surface area which exceeds 500 square millimeters.

[0046] 12. Device 1 wherein the periodic pattern is detectable by diffraction effects, such as a diffraction pattern.

[0047] 13. Device 1 wherein propagation of cracks within the polycrystalline photoactive material is disrupted by the periodic pattern.

[0048] 14. Device 1 wherein delamination of the polycrystalline photoactive material from the surface of the depositional substrate is inhibited by the periodic pattern.

[0049] The present invention includes, but is not limited to, the following specifically preferred processes:

[0050] 1. A process, comprising: depositing a single continuous depositional layer of a polycrystalline photoactive material on an integrated charge storage, amplification, and readout circuit with an irregular surface;

[0051] wherein the polycrystalline photoactive material is comprised of a II-VI semiconductor compound or alloys of II-VI compounds.

[0052] 2. Process 1 wherein the prescribed size has a distance of repetition of at most 100 microns.

[0053] 3. Process 1 wherein the single continuous depositional layer has a total surface area which exceeds 100 square millimeters.

[0054] 4. Process 1 wherein the single continuous depositional layer has a total surface area which exceeds 500 square millimeters.

[0055] 5. Process 1 wherein the single continuous depositional layer is deposited on the integrated charge storage, amplification, and readout circuit at a temperature which is not destructive to the integrated charge storage, amplification, and readout circuit.

[0056] 6. Process 1 wherein the single continuous depositional layer is deposited on the integrated charge storage, amplification, and readout circuit at a temperature which does not exceed approximately 350 degrees Celsius.

[0057] 7. Process 1 wherein the single continuous depositional layer is deposited on the integrated charge storage, amplification, and readout circuit at a temperature which does not exceed approximately 200 degrees Celsius.

[0058] 8. Process 1 wherein the single continuous depositional layer is deposited on the integrated charge storage, amplification, and readout circuit at a depositional rate which exceeds approximately 6 microns per hour.

[0059] 9. Process 1 wherein the single continuous depositional layer is deposited on the integrated charge storage, amplification, and readout circuit at a depositional rate which exceeds approximately 1 micron per hour.

[0060] 10. Process 1 wherein the single continuous depositional layer of the polycrystalline photoactive material is deposited on an integrated charge storage, amplification, and readout circuit without techniques using interim substrates such as bump bonding.

[0061] 11. Process 1 wherein the single continuous depositional layer of the polycrystalline photoactive material is deposited on an integrated charge storage, amplification, and readout circuit without the use of a separate intermediate layer whose purpose is to enhance adhesion.

[0062] 12. Process 1 wherein the single continuous depositional layer of the polycrystalline photoactive material is deposited on an integrated charge storage, amplification, and readout circuit without the use of a compliant layer.

[0063] The present invention includes, but is not limited to, a specifically preferred sensor useful for detecting X-ray photons comprised of a silicon-based single die, charge storage, amplification, and readout pixel array integrated circuit serving as a depositional substrate with a surface exhibiting a periodic pattern of a prescribed size; and a polycrystalline photoactive material deposited as a single continuous depositional layer on top of the integrated charge storage, amplification, and readout circuit; wherein the periodic pattern is comprised of a non-planar surface with two or more alternating elevations at a minimum difference of at least approximately 0.1 micron and a maximum difference of approximately 100 microns while the prescribed size has a distance of repetition of at least approximately 1 micron but at most 100 microns; wherein the polycrystalline photoactive material is selected from the group consisting of CdTe, Hg.sub.xCd.sub.(1-x)Te, and Zn.sub.xCd.sub.(1-x)Te; and wherein the single continuous depositional layer has a total surface area which exceeds 500 square millimeters.

[0064] Specifically preferred embodiments of the current invention exploit properties of polycrystalline CdTe that are found in II-VI compounds and their alloys, and that are not well appreciated by researchers in the field. Thus, the present invention is not restricted to CdTe, II-VI compounds and their alloys but also includes any other photoactive materials of similar properties; these properties include: 1) electrically benign behavior at crystal grain boundaries (i.e. no sites for charge recombination), 2) can be deposited on irregular surfaces and do not require epitaxy and, 3) such deposited films tend to be columnar in structure, biasing charge migration in the vertical direction. It is specifically contemplated, although not yet tested in the laboratory, that the current invention can also use a layer which is a member of the class of compounds known as perovskites. This is the family of methyl ammonium lead halides, compounds with the perovskite structure and are also semiconductors. These include, methyl ammonium lead iodide, methyl ammonium lead bromide and methyl ammonium lead chloride, and use of such layers, rather than polycrystalline CdTe compounds, are specifically included as being within the scope of the present invention. The current invention is a simple single die approach that involves the direct deposition of an X-ray sensitive material on conventional electronics, and does not require pure, single-crystal epitaxial growth. Experiments confirm the feasibility of the present invention.

[0065] Accordingly, it will be apparent to those skilled in the art that still further changes and modifications in the actual concepts described herein can readily be made without departing from the spirit and scope of the disclosed inventions.