Display using analog and digital subframes

Abstract

A display comprises a matrix comprising a plurality of N rows divided into a plurality of M columns of cells, each cell including a light emitting device; a scan driver providing a plurality of N scan line signals to respective rows of said matrix, each for selecting a respective row of the matrix to be programmed with pixel values; and a data driver providing a plurality of M variable level data signals to respective columns of the matrix, each for programming a respective pixel within a selected row of the matrix with a pixel value. A pulse driver provides a plurality of N driving signals to respective rows of the matrix, each driving signal comprising successive sequences of pulses enabling the cells to emit light according to their programmed pixel values during respective sub-frames of successive frames to be displayed. The data driver is arranged to provide variable level data signals to respective pixels within a selected row of the matrix during a limited number of sub-frames of a frame, the variable data levels corresponding to a programmed value of a plurality of bits of a pixel value for a frame. The data driver is further arranged to provide data signals to respective pixels within a selected row of the matrix during a remaining number of sub-frames of a frame, the data signals each corresponding to a programmed value of a single bit of a pixel value for a frame.

Claims

1. A display, comprising: a matrix comprising a plurality of rows divided into a plurality of columns of cells, each cell including a light emitting device; a scan driver providing a plurality of scan line signals to respective rows of the matrix, each for selecting a respective row of the matrix to be programmed with pixel values; a data driver providing a plurality of variable level data signals to respective columns of the matrix, each for programming a respective pixel within a selected row of the matrix with a pixel value; and a pulse driver providing a plurality of driving signals to respective rows of the matrix, each driving signal comprising a sequence of driving pulses enabling the cells to emit light according to their programmed pixel values during respective sub-frames of successive frames to be displayed, wherein each driving pulse of the sequence of driving pulses comprises a stepped pulse with multiple intermediate voltage levels, the stepped pulse including increasing voltage levels from a first intermediate voltage level followed by decreasing voltage levels to the first intermediate voltage level or decreasing voltage levels from a second intermediate voltage level followed by increasing voltage levels to the second intermediate voltage level; wherein the data driver is configured to provide the variable level data signals to respective pixels within a selected row of the matrix during a limited number of sub-frames of a frame, variable data levels of the variable level data signals each being defined by a programmed gray-level value of a plurality of bits of a pixel value for the frame, and wherein the data driver is configured to provide data signals to the respective pixels within the selected row of the matrix during a remaining number of sub-frames of the frame, data levels of the data signals each being defined by a programmed value of a single bit of the pixel value for the frame, and wherein each stepped pulse of the sequence of driving pulses corresponds with the limited number of sub-frames of the frame or a sub-frame of the remaining number of sub-frames of the frame.

2. The display according to claim 1, wherein each pixel is programmed according to a grayscale value and wherein the frame includes a number of sub-frames that is less than a number of gray-scale bits of the frame.

3. The display according to claim 1, wherein the limited number of sub-frames comprises a single sub-frame.

4. The display according to claim 1, wherein the limited number of sub-frames correspond with the least significant bits (LSB) of the pixel value for the frame.

5. The display according to claim 1, wherein the limited number of sub-frames correspond with either 2 or 3 least significant bits (LSB) of the pixel value for the frame.

6. The display according to claim 1, wherein a sub-frame corresponding to a most-significant bit (MSB) of the pixel value for the frame has a longest sub-frame duration and a sub-frame corresponding to a least-significant bits of the pixel value for the frame has a shortest sub-frame duration.

7. The display of claim 1, wherein the limited number of sub-frames are variable according to a maximum resolution of the variable level data signals provided by the data driver.

8. The display of claim 1, wherein each cell comprises a first transistor connected to each of a scan driver signal line and a data driver signal line, the first transistor being connected to a second transistor, the second transistor being connected in series with a light emitting device, and a charge storage device connected between the first and second transistors, the scan driver signal line periodically actuating the first transistor to enable the data driver signal line to set a charge on the charge storage device for a subsequent sub-frame.

9. The display of claim 8, wherein a source for each second transistor of a row is connected in common to a pulse driving signal for the row.

10. The display of claim 8, wherein each light emitting device is connected between the pulse driving signal for the row and a source for the second transistor.

11. The display of claim 8, wherein each light emitting device is connected between the pulse driving signal for the row and a drain for the second transistor and wherein the source for each second transistor is connected to a common supply line.

12. The display of claim 11, wherein an amplitude of the driving pulses is less than the voltage of the common supply line.

13. The display of claim 1, wherein the light emitting devices comprise an inorganic light emitting diode (LED).

14. The display of claim 1, wherein a duration of the limited number of sub-frames is no greater than a shortest duration of a sub-frame from the remaining number of sub-frames.

15. The display of claim 1, wherein a duration of the limited number of sub-frames is approximately equal to a shortest duration of a sub-frame from the remaining number of sub-frames.

16. A display, comprising: a matrix comprising a plurality of rows divided into a plurality of columns of cells, each cell including a light emitting device; a scan driver configured to provide a plurality of scan line signals to respective rows of the matrix, each for selecting a respective row of the matrix to be programmed with pixel values; a data driver configured to provide a plurality of variable level data signals to respective columns of the matrix, each for programming a respective pixel within a selected row of the matrix with a pixel value; and a pulse driver configured to provide a plurality of driving signals to respective rows of the matrix, each driving signal comprising a sequence of driving pulses enabling the cells to emit light according to their programmed pixel values during respective sub-frames of successive frames to be displayed; wherein each driving pulse of the sequence of driving pulses comprises a stepped pulse with multiple intermediate voltage levels, the stepped pulse including increasing voltage levels from a first intermediate voltage level followed by decreasing voltage levels to the first intermediate voltage level or decreasing voltage levels from a second intermediate voltage level followed by increasing voltage levels to the second intermediate voltage level; wherein the data driver is configured to provide the variable level data signals to respective pixels within a selected row of the matrix during a limited number of sub-frames of a frame, variable data levels of the variable level data signals each being defined by a programmed gray-level value of a plurality of bits of a pixel value for the frame, and wherein the data driver is configured to provide data signals to the respective pixels within the selected row of the matrix during a remaining number of sub-frames of the frame, data levels of the data signals each being defined by a programmed value of a single bit of the pixel value for the frame; and wherein each stepped pulse of the sequence of driving pulses corresponds with the limited number of sub-frames of the frame or a sub-frame of the remaining number of sub-frames of the frame.

17. The display according to claim 16, wherein each cell comprises a first transistor connected to each of a scan driver signal line and a data driver signal line, the first transistor being connected to a second transistor, the second transistor being connected in series with a light emitting device, and a charge storage device connected between the first and second transistors, the scan driver signal line periodically actuating the first transistor to enable the data driver signal line to set a charge on the charge storage device for a subsequent sub-frame.

18. A display, comprising: a plurality of cells, each cell including a light emitting device; a data driver configured to provide variable level data signals to a matrix during a first sub-frame of a frame and provide data signals to the matrix during a second sub-frame of the frame, variable data levels of the variable level data signals of the first sub-frame each being defined by a programmed gray-level value of a plurality of bits of a pixel value for the frame, data levels of the data signals of the second sub-frame each being defined by a programmed value of a single bit of the pixel value for the frame; and a pulse driver configured to provide driving signals including a sequence of driving pulses to the matrix to enable the cells to emit light according to the variable level data signals during the first sub-frame and emit light according to the data signals during the second sub-frame, wherein each driving pulse of the sequence of driving pulses comprises a stepped pulse with multiple intermediate voltage levels, the stepped pulse including increasing voltage levels from a first intermediate voltage level followed by decreasing voltage levels to the first intermediate voltage level or decreasing voltage levels from a second intermediate voltage level followed by increasing voltage levels to the second intermediate voltage level.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Various embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which:

(2) FIG. 1 illustrates a conventional PWM driving scheme for a display;

(3) FIG. 2 illustrates a first mixed mode pulse driving scheme for a display according to an embodiment of the present invention;

(4) FIG. 3 illustrates a second mixed mode pulse driving scheme for a display according to an embodiment of the present invention;

(5) FIG. 4 shows an active drive matrix for a display according to one embodiment of the present invention;

(6) FIG. 5 shows an active drive matrix for a display according to another embodiment of the present invention;

(7) FIG. 6 shows an active drive matrix for a display according to a still further embodiment of the present invention;

(8) FIGS. 7(a) and 7(b) illustrate the driving pulses for the matrices of FIGS. 4, 5 and FIG. 6 respectively; and

(9) FIGS. 8(a) and 8(b) illustrate stepped versions of the driving pulses for the matrices of FIGS. 4, 5 and FIG. 6 respectively.

DESCRIPTION OF THE EMBODIMENTS

(10) Referring now to FIGS. 4, 5 and 6, there are shown exemplary active drive matrices for a display according to embodiments of the present invention. Each matrix comprises N rows of cells divided into M columns. Each cell corresponds to either: a pixel for a monochrome display; or one of a red, green or blue sub-pixel within a color display. As explained, for color displays either: differently colored sub-pixels can be interleaved along rows of the matrix; or respective rows of the matrix can comprise only sub-pixels of a given colour.

(11) A plurality of peripheral driving blocks comprise:

(12) Scan driver—which produces the pulses enabling respective rows of the matrix to be programmed for a subsequent sub-frame;

(13) DATA driver—which delivers both variable level outputs to program individuals cells of a row enabled by the scan driver; and

(14) PWM Driver—which produces the PWM pulses used to bias programmed cells enabling the cells to emit light or not according to their programming. (Note that the term “PWM” is used in the present description to relate to pulsed signals for activating cells within a row—such pulses may be employed as part of a conventional PWM addressing scheme or a color sequential scheme.)

(15) Two synchronization blocks are employed: one located between the scan driver and DATA driver in order to ensure that the required data signals are delivered after a scan pulse is applied to a row; and a second between the DATA and PWM drivers to ensure that PWM pulses are applied when data loading is completed.

(16) Each row within the matrix is addressed with a respective scan line S1 . . . Sn which goes high or is asserted when a respective row of the display is to be addressed (or programmed) by the DATA driver for the subsequent sub-frame. During a given frame for each row, the PWM driver provides a sequence of driving pulses using respective PWM signals P1 . . . Pn. Each signal P can be a time shifted version of the adjacent PWM signal synchronized with the scan line signals S1 . . . Sn and DATA driver signals D1 . . . Dm.

(17) In embodiments of the present invention, the DATA driver provides programming signals D1 . . . Dm for each pixel of the display—these signals are updated for each sub-frame from scan line to scan line.

(18) Referring briefly to FIGS. 7(a) and 7(b), in a 2-transistor, 1-capacitor (2T1C) pixel design, such as employed in the matrices of FIGS. 4, 5, 6, each pixel comprises a light emitting device, for example, an iLED such as disclosed in WO2013/121051, connected in series with a thin-film transistor T2. FIG. 7(a) illustrates the pixel design for the matrix of FIG. 4 where the iLED is connected between the transistor drain and ground (Vss); whereas in the pixel design of FIG. 5, the iLED is connected directly between the PWM signal line and the transistor source.

(19) In each case, the scan line for the row and the data line for the cell are connected to a thin-film transistor T1. When a given row is selected by asserting the associated scan line signal, T1 is switched on and the data line signal is used either to charge or discharge a charge storage capacitor Cst shunt-connected between T1 and the gate of the transistor T2 to program a required charge for the subsequent sub-frame. In some embodiments, such as FIG. 7(a), a PWM signal can be applied at the source side of T2 and according to the charge on Cst, the iLED will emit light or not for the sub-frame.

(20) Conventionally, the values for each data signal D1 . . . Dm are digital in that they are either high or low, (“0” or “1”, asserted or not) switching on a pixel for a subsequent sub-frame when the scan line signal S and the PWM signal P for a pixel are asserted and the value for D is high and switching off the pixel, if during the same period, the value for D is low.

(21) In some embodiments of the present invention, a digital driving method is combined with an analog approach not alone to potentially reduce the time required for a frame, but also to reduce the maximum switching frequency required to program pixels for a frame. In this case, values for D1 . . . Dm can be set not only high or low, but also to intermediate values.

(22) Referring now to FIG. 2, in one embodiment of a mixed mode driving scheme, 6-bits of an 8-bit grayscale scheme are driven digitally whereas the remaining 2-bits are driven with an analog signal. In the embodiment, the 6 MSBs are driven digitally in a generally conventional fashion, whereas the two LSBs are combined in a single sub-frame—in this case the 1.sup.st sub-frame. The time duration of the 1.sup.st sub-frame can be anywhere between the duration of the sub-frame for the least significant digital sub-frame, in this case, the 2.sup.nd sub-frame, but need not be any shorter than the length of the equivalent sub-frame that would have been required for a digital only driving scheme with a similar frame length. Where for example, the 1.sup.st analog sub-frame replaces two digital sub-frames, providing the analog sub-frame over the same duration as the 2.sup.nd sub-frame for the 3.sup.rd LSB reduces the maximum switching frequency requirement for a frame by 4. On the other hand, reducing the duration by reducing the number of cycles for the first sub-frame towards 1 potentially shortens the overall duration of the frame slightly.

(23) In the example of FIG. 2, a frame is divided into 256 cycles with the MSB PWM pulse being asserted for 128 cycles down to the PWM pulse for 2.sup.nd sub-frame for the 3.sup.rd LSB being asserted for 4 cycles. Between each set of PWM pulse cycles, the data driver programs the capacitor for each cell according to whether or not the cell is to be switched on or off for the sub-frame.

(24) In the example of FIG. 2, the 1.sup.st sub-frame corresponding to the 2 LSB extends over 4 cycles. In this example, an analog value for the cell data signal asserted prior to the analog sub-frame will correspond to one of the gray-levels 0, 1, 2, and 3, and will depend to an extent on the length of the sub-frame. However, for an analog sub-frame with the same duration as the 2.sup.nd sub-frame, and for a matrix such as shown in FIG. 4 where Vdd=5V, the voltages corresponding to gray-level 0, 1, 2, 3 can be 0V, 3.25V, 4.52V, 4.78V respectively. These voltages can either be provided by DACs incorporated with the DATA driver or through providing fixed reference voltage lines and multiplexors for selecting those lines as required within the DATA driver.

(25) These levels provide a sufficient level of charge to Cst to partially or fully switch on both T2 and the iLED during the analog 1.sup.st sub-frame (or to switch off T2 for gray level 0) and so provide the finer adjustment of the brightness of the iLED during the frame as a whole.

(26) Using the approach of FIG. 2, one data-loading cycle is saved and one emission sub-frame or up to 3 emission cycles can be saved according to the frequency switching limitations for the matrix.

(27) Other combinations of analog and data sub-frames are also possible. FIG. 3 shows another combination comprising 5 MSB digital sub-frames plus 3 LSB analog sub-frames to achieve 8-bit grayscale. In this case, two data-loading cycles are saved and either two emission sub-frames or up to 7 emission cycles can be saved. This of course requires finer data control of the charge on the capacitor Cst and for example requires 3-bit DACs for each port of the DATA driver, rather than 2-bit DACs as in the example of FIG. 2. However, the approach potentially reduces frequency switching requirements even further than the approach of FIG. 2.

(28) In either case, it will be seen that the matrix only operates in analog mode for a small proportion of its operating cycle, i.e. 4 or 8 emission cycles of 256 cycles and so this provides satisfactory device durability.

(29) It will be appreciated that using the architecture of FIG. 4, 5 or 6, the number of analog sub-frames and number of digital sub-frames can be variable (up to the resolution of the DACs or available reference voltages employed within the DATA driver) for a given display and can be adjusted for different applications.

(30) Referring back to FIGS. 7(a) and 7(b), the high supply voltage (Vdd) is the highest voltage of the entire panel while Vss, at ground level, is the lowest one. When PWM pulses are applied to a common high supply line for a row of iLEDs as in the matrices of FIG. 4, their amplitude swing, from Vdd to Vss, is the largest possible. This has a direct impact on the power consumption of the display since more capacitances have to be loaded more often.

(31) In other embodiments, such as FIG. 7(b), the PWM signal is instead applied directly to the cathode of the iLED and when asserted, the iLED will emit light or not for the sub-frame according to the charge on Cst. FIG. 6 shows an active matrix incorporating the pixel design of FIG. 7(b) and where each cell comprises a red, green or blue sub-pixel of a color display.

(32) The advantage of this approach is that the voltage swing for the PWM pulse can now be reduced compared to the pulses used in the matrix of FIG. 4 resulting in lower power consumption. With a supply voltage Vdd-Vss of between about 10-12V, the voltage needed to turn OFF the iLED device is about 4-5V. So rather than driving the PWM signal between Vdd and Vss, using the pixel design of FIG. 7(b) and the matrix of FIG. 6, when the PWM pulse is high (Vdd>˜5V>Vss), the ILED is OFF and when it is “0”=Vss, the iLED emits light according to the charge on capacitor Cst. This pixel design not alone results in less power consumption but also reduced propagation delay vis-à-vis a matrix using the pixel design of FIG. 4, because the PWM signal is applied directly to the iLED cathode.

(33) To further reduce the power consumption, instead of a digital two-level voltage swing for the PWM signals, a stepped multi-voltage level PWM pulse can be applied as shown in FIG. 8. FIG. 8(a) shows such a stepping pulse applied at the high power supply line as in the matrices of FIGS. 4 and 5; whereas FIG. 8(b) illustrates a stepping pulse employed with the pixel design of FIG. 7(b) and with the matrix of FIG. 6.

(34) The main advantage of the voltage stepping pulse is lower power consumption (theoretically it can reach −33%) because the extent of the PWM pulse swing is reduced. Furthermore, the transition of the iLED from the ON to the OFF state will be smoother, so reducing visual artefacts. The number of the intermedia voltage levels (Vint1 . . . Vint3) and their time duration is determined based on the display's specifications and the required performance as well as the mixed mode pulse waveform. Again, these intermediate voltages can either be provided by DACs incorporated with the PWM driver or through providing fixed reference voltage lines and multiplexors for selecting those lines as required within the PWM driver.

(35) The above embodiments have been described with successively longer sub-frames within any given frame. However, it will be appreciated that sub-frames need not be ordered as such and can be mixed to avoid visual aliasing artefacts.

(36) It will also been seen that embodiments of the invention can comprise more than 1 analog sub-frame.