Compact high-voltage nanosecond pulsed-power generator

Abstract

A pulsed-power circuit includes first, second, third and fourth compression stages. The first and second stages each include at least one pre-charged capacitor and at least one inductor in series, and at least one switch operative to pump a DSRD (drift-step-recovery diode). The pre-charged capacitor of the second stage is pre-charged in negative direction with respect to the pre-charged capacitor of the first stage. The third and fourth stages each include at least one DSRD. The switches of the first and second stage are operative to drive (pump and then pulse) the DSRDs of the third and fourth stages.

Claims

1. A pulsed-power device comprising: a pulsed-power circuit comprising first, second, third and fourth compression stages, the first and second compression stages each comprising at least one pre-charged capacitor and at least one inductor in series, and at least one switch operative to pump a DSRD (drift-step-recovery diode), wherein the pre-charged capacitor of the second compression stage is pre-charged in negative direction with respect to the pre-charged capacitor of the first compression stage; and the third and fourth compression stages each comprise at least one DSRD, and wherein said switches of the first and second compression stages are operative to drive (pump and then pulse) the DSRDs of the third and fourth compression stages, wherein said at least one switch of the second compression stage comprises two switches in parallel.

2. The pulsed-power device according to claim 1, wherein said DSRDs are operated in a cascaded compression mode.

3. The pulsed-power device according to claim 2, wherein a bias voltage is used to balance pumping charges of said DSRDs.

4. A pulsed-power device comprising: a pulsed-power circuit comprising first, second, third and fourth compression stages, the first and second compression stages each comprising at least one pre-charged capacitor and at least one inductor in series, and at least one switch operative to pump a DSRD (drift-step-recovery diode), wherein the pre-charged capacitor of the second compression stage is pre-charged in negative direction with respect to the pre-charged capacitor of the first compression stage; and the third and fourth compression stages each comprise at least one DSRD, and wherein said switches of the first and second compression stages are operative to drive (pump and then pulse) the DSRDs of the third and fourth compression stages, wherein said at least one switch of each of the first and second compression stages comprises an IGBT (insulated-gate bipolar transistor), wherein said DSRDs are operated in a cascaded compression mode, and wherein a bias voltage is used to balance pumping charges of said DSRDs.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention will be understood and appreciated more fully from the following detailed description, taken in conjunction with the drawings in which:

(2) FIG. 1 is a simplified schematic of a pulsed-power circuit for a compact high-voltage nanosecond pulsed-power generator (e.g., 10 kV, 1.85 ns rise-time), in accordance with a non-limiting embodiment of the invention.

(3) FIG. 2 is a graphical illustration of load peak voltage versus time for the circuitry of FIG. 1, wherein in graph (a), HV.sub.1=850 V, HV.sub.2=−320 V. and in graph (b), HV.sub.1=800 V, HV.sub.2=−200 V and wherein V.sub.B=−4.0 V (solid line) and V.sub.B=0 V (dashed line).

(4) FIG. 3 is a simplified graphical illustration of load peak voltage versus HV.sub.1 for various values of HV.sub.2.

(5) FIG. 4 is a simplified illustration of a prior art circuit using a DSRD.

DETAILED DESCRIPTION OF EMBODIMENTS

(6) Reference is now made to FIG. 1, which illustrates a pulsed-power circuit for a compact high-voltage nanosecond pulsed-power generator, in accordance with a non-limiting embodiment of the present invention.

(7) The compact pulsed-power circuit may be made of COTS solid-state switching components. The circuit may have four compression stages. The first stage consists of a pre-charged capacitor and an inductor in series, where a switch, such as an IGBT (insulated-gate bipolar transistor) is used for the DSRD pumping. The second stage is similar to the first one, with the exception of its capacitor being pre-charged in the negative direction. The pre-charge in the negative direction allows an enhanced performance for the DSRD pulsing, without any need for a magnetic switch of the prior art. Accordingly, in contrast with the prior art, in the present invention, capacitor C.sub.2 is pre-charged in the negative direction with respect to the pre-charging of capacitor C.sub.1. This allows an enhanced performance in pulsing of the DSRD, resulting in a high DC to peak pulse compression ratio, in a compact generator.

(8) Further compression can be achieved if two DSRDs are operated in a cascaded operation mode. Accordingly, in one embodiment, there are third and fourth stages that include DSRDs operated in a cascaded compression mode, where a small bias voltage allows the balancing of their pumping charges. The switches of the first and second stages drive (pump and then pulse) the DSRDs of the third and fourth stages.

(9) It is noted that cascaded operation is described in A. S. Kesar, L. M. Merensky, M. Ogranovich, A. F. Kardo-Sysoev, and D. Shmilovitz, “6-kv, 130-ps rise-time pulsed-power circuit featuring cascaded compression by fast recovery and avalanche diodes,” Electronics Letters, vol. 49, no. 24, pp. 1539-1540, 2013 (herein “Kesar et al.”). In Kesar et al., both DSRDs in the cascade have their anode on a high voltage bias (high means that the voltage bias is of the order of the high-voltage supply). In contrast, in the present invention, the first DSRD is grounded and the second DSRD has a small voltage bias (for example, only a few volts, which is small with respect to the initial charging of capacitors C.sub.1 and C.sub.2). This small bias is sufficient for a balanced-charge operation.

(10) The circuit size, not including its power supplies, was 100×50×30 mm. Its output to a 50Ω load was above 10 kV (2 MW) with a rise-time of 1.85 ns. The invention is not limited to this size and output.

(11) The pulsed-power generator is an order of magnitude more compact with respect to commercial products, as shown in Table 1.

(12) TABLE-US-00001 TABLE 1 Comparison of commercial products to the pulsed-power generator of the invention Company FID The present Technology Megaimpulse invention Product FPM 10-N NPG 15-2000 HV output 10 kV to 15 kV to 10 kV to 50 Ohm 75 Ohm 50 Ohm Rise-time 1-5 ns 4 ns Approx. 2 ns Dimensions [mm] 200 × 120 × 60 248 × 90 × 250 100 × 50 × 30 Specific power 1.39 0.72 14 [W/mm{circumflex over ( )}3]

(13) Referring again to the circuit of FIG. 1, positive, +HV.sub.1, and negative, −HV.sub.2, high-voltage supplies may be used for charging the circuit capacitors. The circuit may include four compression stages, as mentioned above. In the non-limiting illustrated circuit, the first stage consists of an IGBT (S.sub.1=IRG7PH50UPbF by International Rectifier), two capacitors (C.sub.1a=C.sub.1b=20 nF) pre-charged to HV1+|HV2|, and two inductors (L.sub.1a=L.sub.1b=200 nH). The second stage consists of two IGBTs (S.sub.2a=S.sub.2b=IRG7PH50UPbF), two capacitors (C.sub.2a=C.sub.2b=20 nF) pre-charged to −HV.sub.2, and two inductors (L.sub.2a=L.sub.2b=150 nH). As shown in FIG. 1, the safe parallel operation of S.sub.2a and S.sub.2b is due to the splitting of their capacitors and inductors, namely, S.sub.2a operates with C.sub.1a, L.sub.1a, C.sub.2a, and L.sub.2a, and S.sub.2b operates with the capacitors and inductors with the subscript “b”. The design of two branches in parallel is due to the estimated current in the second compression stage being more than twice the current in the first stage.

(14) The third and fourth stages consist of DSRDs, where the current is compressed via an inductor (L.sub.3=70 nH). The second DSRD is biased by a capacitor (C.sub.3=2 μF) pre-charged to a small bias voltage, V.sub.B, which allows the balancing of their pumping charges. The DSRDs were built using 1-kV cell rectifier diodes (CN25M by EIC). These diodes were found to have a snappy reverse recovery when operated in DSRD mode. DSRD.sub.1 consists of ten stacks in parallel, each stack containing four diodes in series. DSRD.sub.2 consists of seven stacks in parallel, each stack containing seven diodes in series.

(15) In order to pump the DSRDs, S.sub.1 is turned on. This IGBT is driven at time t.sub.1 by its driver (MIC4452 by Micrel). In order to pulse the DSRDs, IGBTs S.sub.2a and S.sub.2b are turned on simultaneously at t.sub.2=t.sub.1+ΔT. These IGBTs are driven via an isolating transformer (not shown in FIG. 1). The transformer consists of two primary coils and two secondary coils, each consisting of five turns on a toroid ferrite core (outer diameter 20 mm, inner diameter 9.5 mm, height 10 mm, relative permeability ≈1500). MIC4452 drivers were connected to the primary coils and each secondary coil was connected to the gate and emitter of its respective IGBT. The output pulse was measured on the load (R.sub.L=50Ω).

(16) The circuit shown in FIG. 1 was operated with a delay time between the first and second IGBTs of ΔT=150 ns. The high-voltage supplies were HV.sub.1=850 V, and HV.sub.2=−320 V. The bias voltage of DSRD2 was V.sub.B=−4.4 V. The result is shown in FIG. 2(a). The load peak voltage was 10.3 kV, and its rise-time (10-90%) was 1.85 ns.

(17) The effect of the bias voltage, V.sub.B on the output is shown in FIG. 2(b). In this graph HV.sub.1 was 800 V, and HV.sub.2 was −200 V. The load voltage versus time when V.sub.B was −4.0 V and 0 V is shown by the solid and dashed lines, respectively. As shown, when V.sub.B was optimized, the load peak voltage was 9.4 kV. When V.sub.B was zero, two peaks are seen, where the higher one was 7.2 kV.

(18) The load peak voltage versus the positive high-voltage, HV.sub.1, is shown in FIG. 3, for various values of the negative high-voltage, HV.sub.2, of −320 V (circle marks), −200 V (square marks), −100 V (diamond marks), and 0 V (triangle marks). As seen in this graph, the negative high-voltage (which charges C.sub.2a and C.sub.2b) results in enhanced performance. When HV.sub.2 was zero, the peak load voltage in the case of HV.sub.1=900 V was 6.1 kV. When HV.sub.2 was −320 V and HV.sub.1 was 500 V, e.g. the total energy in the capacitors was lower than in the previous case, a higher load peak voltage of 8.7 kV was obtained, the load peak power having doubled. Since the IGBTs were rated to 1200 V, the maximum allowed voltage on charging C1a and C1b was HV1+|HV2|≤1200 V.

(19) Accordingly, the embodiment of FIG. 1 is a highly compact, 100×50×30 mm, circuit with an output of 10.3-kV, 1.85-ns rise-time that uses COTS components. Its output power per circuit volume is 14 W/mm.sup.3, which is a factor of ten greater than prior art circuits which use a magnetic switch. It is noted that a more compact circuit size is possible with a custom-designed DSRD.

(20) The capacitors of the second compression stages, C.sub.2a and C.sub.2b were pre-charged to a negative high-voltage. This feature enhances the peak voltage at the load, FIG. 3, and eliminates the need for a magnetic switch. Since the current in the second compression stage is estimated at more than twice the current in the first stage, two IGBTs were used in parallel. An additional design feature is the introduction of a small bias voltage (compared to the HV supplies), at the anode of DSRD.sub.2. Only a few volts were required for balancing the cascaded operation of the DSRDs, FIG. 2(b).

(21) The invention may be utilized to produce higher peak load voltages by increasing the number of the IGBTs. For example, three more IGBTs in a similar configuration can be connected to point “A” in FIG. 1 in order to drive the DSRDs at a higher current. In this case, the DSRDs should be changed in order to support a higher peak power.