Silicon carbide epitaxial substrate, method of manufacturing thereof, silicon carbide semiconductor device, and method of manufacturing thereof

Abstract

A silicon carbide epitaxial substrate including a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, and a high-density foreign element region. The first semiconductor layer is provided at a front surface of the silicon carbide semiconductor substrate and has an impurity concentration lower than that of the silicon carbide semiconductor substrate. The high-density foreign element region is provided in the silicon carbide semiconductor substrate at a predetermined depth from the front surface thereof. The high-density foreign element region contains an element other than carbon and silicon, at a density higher than that of the silicon carbide semiconductor substrate.

Claims

1. A silicon carbide epitaxial substrate comprising: a silicon carbide semiconductor substrate of a first conductivity type; a first semiconductor layer of the first conductivity type, provided at a front surface of the silicon carbide semiconductor substrate and having an impurity concentration lower than that of the silicon carbide semiconductor substrate; a high-density foreign element region provided in the silicon carbide semiconductor substrate at a predetermined depth from the front surface thereof, the high-density foreign element region containing an element other than carbon and silicon, at a density higher than that of the silicon carbide semiconductor substrate.

2. The silicon carbide epitaxial substrate according to claim 1, wherein a thickness of the high-density foreign element region is 0.1 μm to 1.0 μm.

3. The silicon carbide epitaxial substrate according to claim 1 or 2, wherein the density of the element in the high-density foreign element region is 1×10.sup.14/cm.sup.3 to 1×10.sup.18/cm.sup.3.

4. The silicon carbide epitaxial substrate according to claim 1, wherein the element is hydrogen, magnesium, calcium, scandium, titanium, vanadium, chromium, manganese, or iron.

5. The silicon carbide epitaxial substrate according to claim 1, further comprising a buffer layer that becomes a minority-carrier short-lifetime layer and is provided between the silicon carbide semiconductor substrate and the first semiconductor layer.

6. A silicon carbide semiconductor device comprising: a silicon carbide semiconductor substrate of a first conductivity type, having a front surface and a back surface; a high-density foreign element region provided in the silicon carbide semiconductor substrate at a predetermined depth from the front surface thereof, the high-density foreign element region containing an element other than carbon and silicon, at a density higher than that of the silicon carbide semiconductor substrate; a first semiconductor layer of the first conductivity type, provided at the front surface of the silicon carbide semiconductor substrate and having an impurity concentration lower than that of the silicon carbide semiconductor substrate, the first semiconductor layer having a first surface and a second surface that are opposite to each other, the first surface facing the silicon carbide semiconductor substrate; a second semiconductor layer of a second conductivity type, provided at the second surface of the first semiconductor layer; a first electrode provided at a surface of the second semiconductor layer; and a second electrode provided at the back surface of the silicon carbide semiconductor substrate.

7. A method of manufacturing a silicon carbide epitaxial substrate, the method comprising: providing a silicon carbide semiconductor substrate of a first conductivity type; ion implanting, to a depth of at least 0.1 μm at a front surface of the silicon carbide semiconductor substrate an element other than carbon and silicon; and forming a first semiconductor layer of the first conductivity type, at the front surface of the silicon carbide semiconductor substrate by epitaxial growth, the first semiconductor layer having an impurity concentration lower than that of the silicon carbide semiconductor substrate.

8. The method according to claim 7, wherein the element is hydrogen, magnesium, calcium, scandium, titanium, vanadium, chromium, manganese, or iron.

9. A method of manufacturing a silicon carbide semiconductor device, the method comprising: providing a silicon carbide semiconductor substrate of a first conductivity type, the silicon carbide semiconductor substrate having a front surface and a back surface; irradiating the front surface of the silicon carbide semiconductor substrate with an element other than carbon and silicon to a depth of at least 0.1 μm; forming a first semiconductor layer of the first conductivity type, at the front surface of the silicon carbide semiconductor substrate by epitaxial growth, the first semiconductor layer having an impurity concentration lower than that of the silicon carbide semiconductor substrate, the first semiconductor layer having a first surface and a second surface that are opposite to each other, the first surface facing the silicon carbide semiconductor substrate; forming a second semiconductor layer of the first conductivity type, at the second surface of the first semiconductor layer, the second semiconductor layer having a first surface and a second surface that are opposite to each other, the first surface of the second semiconductor layer facing the silicon carbide semiconductor substrate; forming a third semiconductor layer of a second conductivity type, at the second surface of the second semiconductor layer, the third semiconductor layer having a first surface and a second surface that are opposite to each other, the first surface of the third semiconductor layer facing the silicon carbide semiconductor substrate; forming a first electrode at the second surface of the third semiconductor layer; and forming a second electrode at the back surface of the silicon carbide semiconductor substrate.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a cross-sectional view depicting a structure of a silicon carbide epitaxial substrate according to an embodiment.

(2) FIG. 2 is a cross-sectional view schematically depicting a state of the silicon carbide epitaxial substrate according to the embodiment during manufacture (part 1).

(3) FIG. 3 is a cross-sectional view schematically depicting a state of the silicon carbide epitaxial substrate according to the embodiment during manufacture (part 2).

(4) FIG. 4A is a diagram depicting penetrating BPD conversion in a conventional silicon carbide epitaxial substrate.

(5) FIG. 4B is a diagram depicting penetrating BPD conversion in the conventional silicon carbide epitaxial substrate.

(6) FIG. 4C is a diagram depicting penetrating BPD conversion in the conventional silicon carbide epitaxial substrate.

(7) FIG. 4D is a diagram depicting penetrating BPD conversion in the conventional silicon carbide epitaxial substrate.

(8) FIG. 5 is a graph depicting a temperature profile of an epitaxial growth furnace for normal temperature rise.

(9) FIG. 6 is a graph depicting, for the epitaxial growth furnace, a temperature profile having an annealing time.

(10) FIG. 7 is a graph depicting a relationship between annealing time and penetrating BPD count.

(11) FIG. 8 is a top view of a silicon carbide semiconductor substrate, depicting areas of increased penetrating BPDs.

(12) FIG. 9A is a diagram depicting TED conversion in the silicon carbide epitaxial substrate according to the embodiment.

(13) FIG. 9B is a diagram depicting TED conversion in the silicon carbide epitaxial substrate according to the embodiment.

(14) FIG. 9C is a diagram depicting TED conversion in the silicon carbide epitaxial substrate according to the embodiment.

(15) FIG. 9D is a diagram depicting TED conversion in the silicon carbide epitaxial substrate according to the embodiment.

(16) FIG. 10 is a cross-sectional view depicting a structure of a silicon carbide semiconductor device according to the embodiment.

(17) FIG. 11 is a cross-sectional view (part 1) schematically depicting the silicon carbide semiconductor device according to the embodiment during manufacture.

(18) FIG. 12 is a cross-sectional view (part 2) schematically depicting the silicon carbide semiconductor device according to the embodiment during manufacture.

(19) FIG. 13 is a cross-sectional view depicting a structure of a trench-type silicon carbide MOSFET.

(20) FIG. 14 is a cross-sectional view depicting a structure of the conventional silicon carbide epitaxial substrate.

(21) FIG. 15 is a cross-sectional view depicting the structure of a conventional silicon carbide substrate.

MODE OF CARRYING OUT THE INVENTION

(22) Preferred embodiments of a silicon carbide epitaxial substrate, a method of manufacturing a silicon carbide epitaxial substrate, a silicon carbide semiconductor device, and a method of manufacturing a silicon carbide semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present description and accompanying drawings, layers and regions prefixed with n or p mean that majority carriers are electrons or holes, respectively. Additionally, + or − appended to n or p means that the impurity concentration is higher or lower, respectively, than layers and regions without + or −. Cases where n or p symbols include the same + or − indicate that concentrations are close and the concentrations are not necessarily equal. In the description of the embodiments below and the accompanying drawings, main portions that are identical will be given the same reference numerals and will not be repeatedly described.

Embodiment

(23) Among a silicon carbide epitaxial substrate, a method of manufacturing a silicon carbide epitaxial substrate, a silicon carbide semiconductor device, and a method of manufacturing a silicon carbide semiconductor device according to the present invention, first, the silicon carbide epitaxial substrate will be described. FIG. 1 is a cross-sectional view depicting a structure of a silicon carbide epitaxial substrate according to an embodiment.

(24) As depicted in FIG. 1, a silicon carbide epitaxial substrate 100 includes an n.sup.+-type silicon carbide substrate 1 and an n-type silicon carbide epitaxial layer 2. The n-type silicon carbide epitaxial layer 2 is provided at a front surface of the n.sup.+-type silicon carbide substrate 1 and is a semiconductor layer that is formed by epitaxial growth and has an impurity concentration lower than that of the n.sup.+-type silicon carbide substrate 1.

(25) In the n.sup.+-type silicon carbide substrate 1, a high-density foreign element region 24 is provided at a predetermined depth from the front surface of the n.sup.+-type silicon carbide substrate 1. The high-density foreign element region 24 is a region in which a density of a foreign element 23 is higher than that in the n.sup.+-type silicon carbide substrate 1. The high-density foreign element region 24, for example, has a film thickness h that is preferably 0.1 μm to 1 μm.

(26) Because the foreign element 23 in the high-density foreign element region 24 hinders movement of basal plane dislocations 20, the silicon carbide epitaxial substrate 100 of the embodiment increases the proportion of the basal plane dislocations 20 in the n.sup.+-type silicon carbide substrate 1 converted into threading edge dislocations 21, reduces the proportion thereof converted into penetrating basal plane dislocations, and improves BPD conversion efficiency. The BPD conversion efficiency is the proportion of the basal plane dislocations 20 that are converted into the threading edge dislocations 21 and as the BPD conversion efficiency increases, the basal plane dislocations 20 converted into the threading edge dislocations 21 increases; as a result, the number thereof converted into penetrating basal plane dislocations decreases, triangular-shaped stacking faults also decrease, and increases in the forward ON voltage can be reduced.

(27) As the density of the foreign element 23 increases, the effect of hindering the movement of the basal plane dislocations 20 increases, however, when introduced excessively, defects of the n-type silicon carbide epitaxial layer 2 deposited thereon increase and therefore, the density is preferably 1×10.sup.14/cm.sup.3 to 1×10.sup.18/cm.sup.3.

(28) The silicon carbide epitaxial substrate according to the embodiment is manufactured as follows. FIGS. 2 and 3 are cross-sectional views schematically depicting states of the silicon carbide epitaxial substrate according to the embodiment during manufacture. First, the n.sup.+-type silicon carbide substrate 1 is prepared. In the n.sup.+-type silicon carbide substrate 1, defects called the basal plane dislocations 20 are contained at a density on an order of 10.sup.2 to 10.sup.3/cm.sup.2. The state up to here is depicted in FIG. 2.

(29) Next, a foreign element 25 is ion implanted from the front surface of the n.sup.+-type silicon carbide substrate 1, whereby the foreign element 23 in SiC crystals is introduced and the high-density foreign element region 24 is formed. For example, hydrogen, magnesium, calcium, scandium, titanium, vanadium, chromium, manganese, iron, etc. can be used for the foreign element 25. Preferably, the size of the foreign element 25 greatly differs from that of silicon atoms and that of carbon atoms constituting the silicon carbide. Further, preferably, ion implantation of the foreign element 25 is performed so that the foreign element is implanted to a depth of at least 0.1 μm from the front surface of the n.sup.+-type silicon carbide substrate 1 so as not to be removed by etching before epitaxial growth of the n-type silicon carbide epitaxial layer 2. The state up to here is depicted in FIG. 3.

(30) Next, on the n.sup.+-type silicon carbide substrate 1, a silicon carbide epitaxial layer that becomes the n-type silicon carbide epitaxial layer 2 is deposited while nitrogen (N), which is an n-type impurity, is doped. A surface on which the n-type silicon carbide epitaxial layer 2 is deposited may be a Si-face, a C-face, or a face other than these, however in the embodiment, a Si-face is used. As described above, the silicon carbide epitaxial substrate 100 of the embodiment depicted in FIG. 1 is manufactured.

(31) Next, a model of BPD penetration proposed by the inventors will be described in detail. FIGS. 4A, 4B, 4C, and 4D are diagrams depicting penetrating BPD conversion in the conventional silicon carbide epitaxial substrate. FIGS. 4A, 4B, 4C, and 4D are cross-sectional views of the silicon carbide epitaxial substrate 200. As depicted in FIG. 4A, near a surface of the n.sup.+-type silicon carbide substrate 101, the BPD 120 formed by a narrow stacking fault (hatched portion in FIG. 4A) between two partial dislocations (Si(g)) and (C(g)) is present. Next, as depicted in FIG. 4B, when thermal stress is applied before the epitaxial growth of the n-type silicon carbide epitaxial layer 2, of the partial dislocations in the BPD 120, a Si-core partial dislocation Si(g) moves in a direction of arrow A and the stacking fault expands. Next, as depicted in FIG. 4C, when the front surface is hydrogen etched while the thermal stress is applied, the surface is removed by the hydrogen etching, however, at the same time, therebelow, the stacking fault expands in the direction of arrow A. Next, as depicted in FIG. 4D, an n-type silicon carbide epitaxial layer (not depicted) is epitaxially grown. In FIG. 4D, dotted line C indicates an interface between the n.sup.+-type silicon carbide substrate 101 and the n-type silicon carbide epitaxial layer. As depicted in FIG. 4D, while the stacking fault slightly contracts due to a start of the epitaxial growth, the stacking fault does not completely contract and becomes the penetrating BPD 122. On the other hand, when the stacking fault sufficiently contracts, during the epitaxial growth, cross-slip of the partial dislocations and conversion into a TED occurs.

(32) To verify the model, the inventors investigated the extent to which BPDs penetrate due to thermal stress. Thermal stress was given by temperature distribution of an epitaxial growth furnace. The inventors applied the thermal stress and compared penetrating BPD counts by providing an annealing time that kept the temperature constant during temperature rise of the epitaxial growth. FIG. 5 is a graph depicting a temperature profile of the epitaxial growth furnace for normal temperature rise and FIG. 6 is a graph depicting a temperature profile of the epitaxial growth furnace having the annealing time. In FIGS. 5 and 6, vertical axes indicate time in units of minutes. Further, vertical axes indicate temperature in units of degrees C.

(33) FIG. 5 is a temperature profile when the n-type silicon carbide epitaxial layer 2 is epitaxially grown. As depicted in FIG. 5, the n.sup.+-type silicon carbide substrate 1 is inserted into the epitaxial growth furnace, the temperature is raised to 1600 degrees C., and after the hydrogen (H.sub.2) etching is performed, the n-type silicon carbide epitaxial layer 2 is epitaxially grown and thereafter, the temperature is lowered.

(34) FIG. 6 is a temperature profile having the annealing time before the epitaxial growth. As depicted in FIG. 6, the n.sup.+-type silicon carbide substrate 1 is inserted into the epitaxial growth furnace, the temperature is raised to 900 degrees C., and annealing is performed for 60 minutes. Thereafter, similarly as with FIG. 5, the n.sup.+-type silicon carbide substrate 1 is inserted into the epitaxial growth furnace, the temperature is raised to 1600 degrees C., and after the hydrogen (H.sub.2) etching is performed, the n-type silicon carbide epitaxial layer 2 is epitaxially grown and thereafter, the temperature is lowered.

(35) FIG. 7 is a graph depicting a relationship between annealing time obtained by experiment and penetrating BPD count. In FIG. 7, a horizontal axis indicates annealing time in units of minutes. Further, a vertical axis indicates counts of penetrating BPDs per semiconductor wafer in units of pieces. FIG. 7 depicts the penetrating BPD count in a case in which the time and the temperature of the annealing time is changed before epitaxial growth. As depicted in FIG. 7, as the annealing time increases, i.e., the longer thermal stress due to the annealing is applied, the count of the penetrating BPDs per semiconductor wafer increases.

(36) The inventors further investigated areas of increased penetrating BPDs at the wafer surface. FIG. 8 is a top view of silicon carbide semiconductor substrate, depicting areas of increased penetrating BPDs. FIG. 8 depicts areas where, as compared to a silicon carbide semiconductor substrate for which annealing during temperature rise was not performed, the penetrating BPDs increased by two or more penetrating BPDs within a rectangular shape having a mathematical area of 1×1.4 mm.sup.2 in a silicon carbide semiconductor substrate in a case in which annealing during temperature rise was performed at 1250 degrees C. for 30 minutes. In FIG. 8, as compared to the case in which annealing is not performed during temperature rise, the areas where the penetrating BPDs increase by two or more penetrating BPDs are concentrated at parts surrounded by circles.

(37) The inventors compared distribution (not depicted) of thermal stress calculated by the temperature distribution at the wafer surface and FIG. 8, and learned that the areas where the penetrating BPDs increased are areas having strong shear stress (thermal stress). From results of the experiment above, the inventors verified for the proposed model, that the longer thermal stress due to annealing is applied, the count of penetrating BPDs per semiconductor wafer increases.

(38) Subsequently, the inventors proposed the following penetrating BPD reduction scheme, based on the model. In other words, for example, even when thermal stress is added, partial dislocations do not move, whereby expansion of stacking faults is suppressed and the penetrating BPD count is reduced. Movement of the partial dislocations is hindered and therefore, ion implantation of hydrogen, magnesium, calcium, scandium, titanium, vanadium, chromium, manganese, iron, etc. is performed and the high-density foreign element region 24 is formed in the n.sup.+-type silicon carbide substrate 1. As is well known in metal engineering, dislocation glide motion is suppressed by a solid solution strengthening mechanism due to the foreign element. The greater that the size differs from that of the target element, the foreign element can more firmly suppress the motion.

(39) FIGS. 9A, 9B, 9C, and 9D are diagrams depicting TED conversion in the silicon carbide epitaxial substrate according to the embodiment. FIGS. 9A to 9D are cross-sectional views of a silicon carbide epitaxial substrate. As depicted in FIG. 9A, the BPD 20 formed by a narrow stacking fault (hatched portion of FIG. 9A) between two partial dislocations (Si(g)) and (C(g)) is present near a surface of the n.sup.+-type silicon carbide substrate 1. Next, as depicted in FIG. 9B, even when thermal stress is applied before the n-type silicon carbide epitaxial layer 2 is epitaxially grown, in the silicon carbide epitaxial substrate according to the embodiment, due to the solid solution strengthening mechanism of the foreign element 23, the partial dislocation Si(g) does not move and therefore, the stacking fault does not expand. Next, as depicted in FIG. 9C, even when the front surface is hydrogen etched in a state of thermal stress being applied, the surface is removed by the hydrogen etching, however, the foreign element 23 is not removed and residual pinning effects continue, whereby crystal defects do not expand. Next, as depicted in FIG. 9D, the n-type silicon carbide epitaxial layer (not depicted) is epitaxially grown. In FIG. 9D, dotted line C indicates the interface between the n.sup.+-type silicon carbide substrate 101 and the n-type silicon carbide epitaxial layer. As depicted in FIG. 4D, due to the start of the epitaxial growth, the stacking fault contracts and the BPD 20 is converted into the TED 21.

(40) As described above, the silicon carbide epitaxial substrate of the embodiment has a region having a high density of a foreign element in the n.sup.+-type silicon carbide substrate. The foreign element becomes an obstacle when a dislocation moves and hinders the movement of the dislocation and therefore, even when thermal stress is applied, a stacking fault in a BPD does not expand and the BPD is easily converted into a TED, thereby enhancing conversion efficiency of BPDs.

(41) Next, for the silicon carbide semiconductor device using the silicon carbide epitaxial substrate according to the embodiment, a silicon carbide PiN diode will be described as an example. FIG. 10 is a cross-sectional view depicting a structure of a silicon carbide semiconductor device according to the embodiment.

(42) As depicted in FIG. 10, the silicon carbide semiconductor device is configured using a silicon carbide substrate in which, at a front surface of an n.sup.+-type silicon carbide substrate (silicon carbide semiconductor substrate of a first conductivity type) 1, an n-type silicon carbide epitaxial layer (first semiconductor layer of the first conductivity type) 2 and a p-type silicon carbide layer (second semiconductor layer of a second conductivity type) 3 are sequentially stacked.

(43) The n.sup.+-type silicon carbide substrate 1 is a silicon carbide single crystal substrate doped with, for example, nitrogen, and polytypes of silicon carbide include 3C—SiC, 4H—SiC, 6H—SiC, etc. In the embodiment, the high-density foreign element region 24 is provided in the n.sup.+-type silicon carbide substrate 1 and a density of the foreign element 23 thereof at a predetermined depth from the front surface of the n.sup.+-type silicon carbide substrate 1 is higher than that of the n.sup.+-type silicon carbide substrate 1.

(44) The n-type silicon carbide epitaxial layer 2 is a drift layer that is doped with, for example, nitrogen and has a carrier concentration that is lower than that of the n.sup.+-type silicon carbide substrate 1. Further, the p-type silicon carbide layer 3 is provided on the n-type silicon carbide epitaxial layer 2; a cathode electrode 6 is provided at a back surface of the n.sup.+-type silicon carbide substrate 1; and an anode electrode 5 is provided at a surface of the p-type silicon carbide layer 3.

(45) Further, a form may be such that a buffer layer that becomes a minority-carrier short-lifetime layer is provided between the n.sup.+-type silicon carbide substrate 1 and the n-type silicon carbide epitaxial layer 2. The buffer layer may be a silicon carbide epitaxial layer (hereinafter, high-density nitrogen layer) doped with, for example, nitrogen (N) at a high concentration or may be a silicon carbide epitaxial layer (hereinafter, codoped layer) to which nitrogen and a foreign element such as boron (B), vanadium (V), titanium (Ti), iron (Fe), chromium (Cr), etc. are simultaneously added (codoped). By providing the buffer layer, holes injected by a p-layer recombine in the buffer layer and are prevented from reaching the n.sup.+-type silicon carbide substrate 1, enabling an occurrence of stacking faults from the n.sup.+-type silicon carbide substrate 1 to be prevented.

(46) Additionally, before the foreign element is further ion implanted, annealing under a constant temperature of 500 degrees C. or higher may be performed to sufficiently contract stacking faults in a BPD. Stacking faults of SiC are known to be temperature unstable and to contract at a temperature of about 500 degrees C. or higher in a state free of external stress and UV irradiation.

(47) (Method of Manufacturing Silicon Carbide Semiconductor Device According to Embodiment)

(48) A method of manufacturing the silicon carbide semiconductor device according to the embodiment will be described taking, as an example, a case in which silicon carbide is used as a semiconductor material and PiN diode is fabricated (manufactured). FIGS. 11 and 12 are cross-sectional views depicting states of the silicon carbide semiconductor device according to the embodiment during manufacture.

(49) First, the n.sup.+-type silicon carbide substrate 1 is prepared and, as described above, the silicon carbide epitaxial substrate having the high-density foreign element region 24 is manufactured (refer to FIGS. 2 and 3). The state up to here is shown in FIG. 11.

(50) Next, on the n-type silicon carbide epitaxial layer 2, the p-type silicon carbide layer 3 is deposited by epitaxial growth. Here, the p-type silicon carbide layer 3 can also be formed at a surface of the n-type silicon carbide epitaxial layer 2 by ion implantation of a p-type impurity. The state up to here is shown in FIG. 12. Next, activation annealing (heat treatment) for activating diffused regions each formed by ion implantation is performed.

(51) Next, for example, titanium (Ti) and aluminum (Al) are deposited at the surface of the p-type silicon carbide layer 3, whereby the anode electrode 5 is formed. Next, for example, nickel (Ni) is deposited at the back surface of the n.sup.+-type silicon carbide substrate 1 and a heat treatment is performed, whereby the cathode electrode 6 is formed. In this manner, a vertical PiN diode depicted in FIG. 10 is completed.

(52) In the embodiment described above, while a PiN diode has been described as an example, the present invention is further applicable to built-in diodes of a silicon carbide MOSFET. FIG. 13 is a cross-sectional view depicting a structure of a trench-type silicon carbide MOSFET.

(53) In FIG. 13, reference numerals 31 to 42, 48, 49 are an n.sup.+-type silicon carbide substrate, an n.sup.−-type drift layer, a first p.sup.+-type region, a second p.sup.+-type region, an n-type region, a p-type base layer (third semiconductor layer), n.sup.+-type source region, a p.sup.+-type contact region, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode (first electrode), and a trench, and a back electrode (second electrode). In the trench-type silicon carbide MOSFET as well, in the n.sup.+-type silicon carbide substrate 31, the high-density foreign element region 24 is provided having a density of the foreign element 23 at a predetermined depth from the front surface of the n.sup.+-type silicon carbide substrate 1 higher than that of the n.sup.+-type silicon carbide substrate 31. Such a vertical MOSFET having a trench gate structure such as this has a built-in diode (parasitic pn diode) that is built therein and formed by the p-type base layer 36 and the n.sup.−-type drift layer 32 as a body diode between a source and a drain.

(54) In such a MOSFET, in addition to a mode (synchronous rectification mode) in which current passes through a MOS channel, a mode (bipolar mode) exists in which current passes through the built-in diode like arrow A in FIG. 13. Similarly to the case of a PiN diode, in the bipolar mode, when hole density in the n.sup.−-type drift layer 32 exceeds a predetermined value, stacking faults expand due to penetrating BPDs in the n.sup.−-type drift layer 32 and the resistance of the n.sup.−-type drift layer 32 increases, whereby forward voltage (Vf) degradation occurs.

(55) Therefore, in the embodiment, the silicon carbide epitaxial substrate that has the high-density foreign element region for which the conversion efficiency of BPDs is enhanced is used. Due to this, in the MOSFET as well, similarly to the case of the PiN diode, the occurrence of stacking faults in the n.sup.+-type silicon carbide substrate 31 is suppressed and performance degradation can be suppressed.

(56) Furthermore, similarly to the case of the PiN diode, a form may be such that a buffer layer that becomes a minority-carrier short-lifetime layer is provided between the n.sup.+-type silicon carbide substrate 31 and the n.sup.−-type drift layer 32. The buffer layer may be the high-density nitrogen layer or the codoped layer. By providing the buffer layer, holes injected from a pn interface recombine in the buffer layer and are prevented from reaching the n.sup.+-type silicon carbide substrate 31, enabling an occurrence of stacking faults from the n.sup.+-type silicon carbide substrate 31 to be prevented.

(57) As described above, a silicon carbide device according to the embodiment uses the silicon carbide epitaxial substrate that has the high-density foreign element region for which the conversion efficiency of BPDs is enhanced, whereby expansion of stacking faults can be suppressed even when high current is applied in a forward direction of the silicon carbide semiconductor device. Therefore, the silicon carbide semiconductor device having high reliability without increases in forward ON voltage can be provided.

(58) In the foregoing, various modifications of the present invention are possible within a range not departing from the spirit of the present invention and in the embodiments described above, for example, dimensions, impurity concentration, etc. of parts are variously set according to required specifications, etc. Further, in the present invention, while in the embodiments, the first conductivity type is set as a p-type and the second conductivity type is set as an n-type, the present invention is similarly implemented when the first conductivity type is set as an n-type and the second conductivity type is set as a p-type.

INDUSTRIAL APPLICABILITY

(59) As described above, the silicon carbide epitaxial substrate, the method of manufacturing a silicon carbide epitaxial substrate, the silicon carbide semiconductor device, and the method of manufacturing a silicon carbide semiconductor device according to the present invention are useful for power semiconductors used in power converting equipment such as inverters, etc. as well as in inverters and the like of electric vehicles and power supply devices of various types of industrial machines and the like.