Power amplifier apparatus

Abstract

A power amplifier apparatus is provided. The power amplifier apparatus includes a number of multi-stage power amplifiers and a bias circuit configured to generate a number of bias signals (e.g., bias current or bias voltage) to control (e.g., activate or deactivate) the multi-stage power amplifiers. In examples disclosed herein, only one of the multi-stage power amplifiers is activated at a given time. In this regard, the bias circuit can generate the bias signals to collectively activate one of the multi-stage power amplifiers, while deactivating the rest of the multi-stage power amplifiers. As such, it may be possible to control a larger number of power amplifier stages based on a smaller number of bias signals. As a result, it may be possible to eliminate a biasing bump pad(s) from the power amplifier apparatus, thus helping to reduce the footprint and cost of the power amplifier apparatus.

Claims

1. A power amplifier apparatus comprising: a first multi-stage power amplifier comprising a first number of stages and configured to amplify a first radio frequency (RF) signal; a second multi-stage power amplifier comprising a second number of stages and configured to amplify a second RF signal; and a bias circuit configured to generate a plurality of bias signals configured to: activate one of the first multi-stage power amplifier and the second multi-stage power amplifier; and deactivate another one of the first multi-stage power amplifier and the second multi-stage power amplifier; wherein a number of the plurality of bias signals is less than a count of the first number of stages and the second number of stages.

2. The power amplifier apparatus of claim 1 wherein the bias circuit is further configured to activate the first multi-stage power amplifier and deactivate the second multi-stage power amplifier concurrently.

3. The power amplifier apparatus of claim 1 wherein the bias circuit is further configured to deactivate the first multi-stage power amplifier and activate the second multi-stage power amplifier concurrently.

4. The power amplifier apparatus of claim 1 wherein the bias circuit is further configured to generate the plurality of bias signals comprising a plurality of bias current signals.

5. The power amplifier apparatus of claim 1 wherein the bias circuit is further configured to generate the plurality of bias signals comprising a plurality of bias voltage signals.

6. The power amplifier apparatus of claim 1 wherein the bias circuit comprises a bias controller configured to: receive a bias indication signal indicative of the one of the first multi-stage power amplifier and the second multi-stage power amplifier to be activated; and generate the plurality of bias signals to activate the one of the first multistage power amplifier and the second multi-stage power amplifier and deactivate the another one of the first multi-stage power amplifier and the second multi-stage power amplifier.

7. The power amplifier apparatus of claim 6 wherein the bias controller is further configured to receive the bias indication signal from a transceiver circuit.

8. The power amplifier apparatus of claim 7 further comprising the transceiver circuit.

9. The power amplifier apparatus of claim 1 wherein the plurality of bias signals comprises: a first bias signal configured to bias the first multi-stage power amplifier; a second bias signal configured to bias the second multi-stage power amplifier; and a common bias signal configured to bias the first multi-stage power amplifier and the second multi-stage power amplifier.

10. The power amplifier apparatus of claim 9 wherein: the first multi-stage power amplifier comprises a first input stage and a first output stage coupled to the first input stage; and the second multi-stage power amplifier comprises a second input stage and a second output stage coupled to the second input stage.

11. The power amplifier apparatus of claim 10 wherein the bias circuit is further configured to: provide the first bias signal to the first output stage; provide the second bias signal to the second output stage; and provide the common bias signal to the first input stage and the second input stage.

12. The power amplifier apparatus of claim 11 wherein the bias circuit is further configured to: assert the common bias signal and the first bias signal above respective biasing thresholds to activate the first multi-stage power amplifier; and assert the common bias signal and de-assert the second bias signal below a respective biasing threshold to deactivate the second multi-stage power amplifier.

13. The power amplifier apparatus of claim 12 wherein the bias circuit is further configured to: assert the common bias signal to activate the first input stage and deactivate the second input stage; assert the first bias signal to activate the first output stage; and de-assert the second bias signal to deactivate the second output stage.

14. The power amplifier apparatus of claim 11 wherein the bias circuit is further configured to: assert the common bias signal and the second bias signal to activate the second multi-stage power amplifier; and assert the common bias signal and de-assert the first bias signal to deactivate the first multi-stage power amplifier.

15. The power amplifier apparatus of claim 14 wherein the bias circuit is further configured to: assert the common bias signal to deactivate the first input stage and activate the second input stage; de-assert the first bias signal to deactivate the first output stage; and assert the second bias signal to activate the second output stage.

16. The power amplifier apparatus of claim 10 wherein the bias circuit is further configured to: provide the first bias signal to the first input stage; provide the second bias signal to the second input stage; and provide the common bias signal to the first output stage and the second output stage.

17. The power amplifier apparatus of claim 16 wherein the bias circuit is further configured to: assert the common bias signal and the first bias signal to activate the first multi-stage power amplifier; and assert the common bias signal and de-assert the second bias signal to deactivate the second multi-stage power amplifier.

18. The power amplifier apparatus of claim 17 wherein the bias circuit is further configured to: assert the common bias signal to activate the first output stage and deactivate the second output stage; assert the first bias signal to activate the first input stage; and de-assert the second bias signal to deactivate the second input stage.

19. The power amplifier apparatus of claim 16 wherein the bias circuit is further configured to: assert the common bias signal and the second bias signal to activate the second multi-stage power amplifier; and assert the common bias signal and de-assert the first bias signal to deactivate the first multi-stage power amplifier.

20. The power amplifier apparatus of claim 19 wherein the bias circuit is further configured to: assert the common bias signal to deactivate the first output stage and activate the second output stage; de-assert the first bias signal to deactivate the first input stage; and assert the second bias signal to activate the second input stage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

(2) FIG. 1 is a schematic diagram of an exemplary multi-stage power amplifier;

(3) FIG. 2 is a schematic diagram of an exemplary power amplifier apparatus configured to reduce a number of biasing bump pads required for biasing a number of multi-stage power amplifiers, such as the multi-stage power amplifier of FIG. 1; and

(4) FIGS. 3A-3C are schematic diagrams providing exemplary illustrations of the power amplifier apparatus of FIG. 2 configured according to different embodiments of the present disclosure.

DETAILED DESCRIPTION

(5) The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

(6) It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

(7) It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

(8) Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

(9) The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

(10) Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

(11) Embodiments of the disclosure relate to a power amplifier apparatus. The power amplifier apparatus includes a number of multi-stage power amplifiers and a bias circuit configured to generate a number of bias signals (e.g., bias current or bias voltage) to control (e.g., activate or deactivate) the multi-stage power amplifiers. In examples disclosed herein, only one of the multi-stage power amplifiers is activated at a given time. In this regard, the bias circuit can generate the bias signals to collectively activate one of the multi-stage power amplifiers, while deactivating the rest of the multi-stage power amplifiers. As such, it may be possible to control a larger number of power amplifier stages based on a smaller number of bias signals. For example, the bias circuit may control a pair of two-stage power amplifiers using three bias signals. As a result, it may be possible to eliminate a biasing bump pad(s) from the power amplifier apparatus, thus helping to reduce the footprint and cost of the power amplifier apparatus.

(12) Before discussing the power amplifier apparatus of the present disclosure starting at FIG. 2, a brief overview of a conventional multi-stage power amplifier is first provided with reference to FIG. 1 to help explain certain key characteristics and operational principles of the multi-stage power amplifier.

(13) FIG. 1 is a schematic diagram of an exemplary multi-stage power amplifier 10. In a non-limiting example, the multi-stage power amplifier 10 is a two-stage power amplifier consisting of an input stage heterojunction bipolar transistor (HBT) 12 and an output stage HBT 14. The input stage HBT 12 may be activated by asserting an input stage bias signal 16 (e.g., a current signal or a voltage signal) above an input bias threshold or deactivated by de-asserting the input stage bias signal 16 to below the input bias threshold. Similarly, the output stage HBT 14 may be activated by asserting an output stage bias signal 18 (e.g., a current signal or a voltage signal) above an output bias threshold or deactivated by de-asserting the output stage bias signal 18 to below the output bias threshold.

(14) When the input stage HBT 12 is activated, the input stage HBT 12 can receive and amplify an RF signal 20 based on an input stage voltage V.sub.CCA. Likewise, when the output stage HBT 14 is activated, the output stage HBT 14 can amplify and output the RF signal 20 based on an output stage voltage V.sub.CCB. Both the input stage voltage V.sub.CCA and the output stage voltage V.sub.CCB can be either envelope tracking (ET) voltages or average power tracking (APT) voltages.

(15) The multi-stage power amplifier 10 also includes a pair of biasing bump pads 22 and 24 configured to couple the input stage bias signal 16 and the output stage bias signal 18 to the input stage HBT 12 and the output stage HBT 14, respectively. Notably, a wireless communication device (e.g., a smartphone) often employs multiple power amplifiers to amplify RF signals in different frequency bands. As such, the number of biasing bump pads required by the wireless communication device increases in proportion to the number of power amplifiers and the number of stages in each of the power amplifiers. In this regard, it may be desirable to reduce the cost of the wireless communication device by reducing the number of the biasing bump pads associated with the power amplifier(s).

(16) In this regard, FIG. 2 is a schematic diagram of a power amplifier apparatus 26 configured to reduce a number of biasing bump pads required for biasing a number of multi-stage power amplifiers, such as the multi-stage power amplifier 10 of FIG. 1. The power amplifier apparatus 26 includes a first multi-stage power amplifier 28 configured to amplify a first RF signal 30 and a second multi-stage power amplifier 32 configured to amplify a second RF signal 34. In a non-limiting example, the first multi-stage power amplifier 28 includes a first input stage 36 and a first output stage 38 coupled to the first input stage 36. Each of the first input stage 36 and the first output stage 38 may include a respective HBT or any type of field-effect transistors (FETs). Similarly, the second multi-stage power amplifier 32 includes a second input stage 40 and a second output stage 42 coupled to the second input stage 40. Each of the second input stage 40 and the second output stage 42 may include a respective HBT or any type of FETs.

(17) Like the multi-stage power amplifier 10 of FIG. 1, each of the first input stage 36, the first output stage 38, the second input stage 40, and the second output stage 42 can be activated by a respective bias signal above a respective bias threshold or deactivated by the respective bias signal below the respective bias threshold. In this regard, the power amplifier apparatus 26 further includes a bias circuit 44 configured to generate a number of bias signals 46 for controlling the first input stage 36, the first output stage 38, the second input stage 40, and the second output stage 42.

(18) In examples disclosed herein, the bias circuit 44 is configured to capitalize on a configuration option that requires only one of the first multi-stage power amplifier 28 and the second multi-stage power amplifier 32 to be activated at any given time. Specifically, the bias circuit 44 is configured to generate the bias signals 46 to collectively activate one of the first multi-stage power amplifier 28 and the second multi-stage power amplifier 32 and deactivate another one of the first multi-stage power amplifier 28 and the second multi-stage power amplifier 32. For example, the bias circuit 44 can generate the bias signals 46 to concurrently activate the first multi-stage power amplifier 28 and deactivate the second multi-stage power amplifier 32 or deactivate the first multi-stage power amplifier 28 and activate the second multi-stage power amplifier 32.

(19) As discussed in detail below, it may be possible to reduce the biasing bump pads in the power amplifier apparatus 26 by generating the bias signals 46 to collectively control the first multi-stage power amplifier 28 and the second multi-stage power amplifier 32. In a non-limiting example, the bias circuit 44 is configured to generate the bias signals 46 that include a first bias signal 48, a second bias signal 50, and a common bias signal 52. The first bias signal 48 is configured to bias the first multi-stage power amplifier 28, the second bias signal 50 is configured to bias the second multi-stage power amplifier 32, and the common bias signal 52 is configured to bias both the first multi-stage power amplifier 28 and the second multi-stage power amplifier 32. In this regard, the bias circuit 44 can use the first bias signal 48, the second bias signal 50, and the common bias signal 52 to collectively activate or deactivate any of the first multi-stage power amplifier 28 and the second multi-stage power amplifier 32.

(20) More specifically, the bias circuit 44 can utilize the bias circuit 44 can use the first bias signal 48, the second bias signal 50, and the common bias signal 52 to collectively control the first input stage 36, the first output stage 38, the second input stage 40, and the second output stage 42. Given that only three (3) bias signals are needed to control the first multi-stage power amplifier 28 and the second multi-stage power amplifier 32, it may be possible to eliminate at least one biasing bump pad from the power amplifier apparatus 26. As a result, it may be possible to reduce the footprint and cost of the power amplifier apparatus 26.

(21) Notably, each of the first multi-stage power amplifier 28 and the second multi-stage power amplifier 32 may include additional stages that need to be biased respectively. In addition, the power amplifier apparatus 26 can be configured to include additional multi-stage power amplifiers for amplifying additional RF signals. In this regard, the bias circuit 44 may help eliminate even more biasing bump pads from the power amplifier apparatus 26 by utilizing the bias signals 46 to collectively control all the additional stages and/or the additional multi-stage power amplifiers.

(22) The bias circuit 44 may receive a bias indication signal 54 indicative of which one of the first multi-stage power amplifier 28 and the second multi-stage power amplifier 32 to be activated. Accordingly, the bias circuit 44 may generate the bias signals 46 to collectively activate one of the first multi-stage power amplifier 28 and the second multi-stage power amplifier 32 and deactivate another one of the first multi-stage power amplifier 28 and the second multi-stage power amplifier 32. The bias circuit 44 may receive the bias indication signal 54 from a transceiver circuit 56, which also generates the first RF signal 30 and the second RF signal 34. The transceiver circuit 56 may be integrated into the power amplifier apparatus 26 or be provided in a separate system-on-chip (SoC) die from the power amplifier apparatus 26.

(23) The bias circuit 44 may be configured to generate the bias signals 46 to collectively control the first multi-stage power amplifier 28 and the second multi-stage power amplifier 32 in accordance to a number of embodiments, as discussed in detail in FIGS. 3A-3C next. In this regard, FIGS. 3A-3C are schematic diagrams providing exemplary illustrations of the power amplifier apparatus 26 of FIG. 2 configured according to different embodiments of the present disclosure. Common elements between FIGS. 2 and 3A-3C are shown therein with common element numbers and will not be re-described herein.

(24) FIG. 3A is a schematic diagram of an exemplary bias circuit 44A, which can be provided in the power amplifier apparatus 26 of FIG. 2 as the bias circuit 44. The bias circuit 44A includes a bias controller 58, which may be implemented by a field-programmable gate array (FPGA), as an example. The bias controller 58 may be configured to receive the bias indication signal 54 and generate the first bias signal 48, the second bias signal 50, and the common bias signal 52 accordingly. Notably, the first bias signal 48, the second bias signal 50, and the common bias signal 52 can be a number of bias current signals or a number of bias voltage signals.

(25) The bias circuit 44A may be configured to include a first biasing bump pad 60, a second biasing bump pad 62, and a common biasing bump pad 64 configured to receive the first bias signal 48, the second bias signal 50, and the common bias signal 52, respectively. The bias circuit 44A may also include a supply bump pad 66 configured to receive a battery voltage V.sub.BAT.

(26) The first biasing bump pad 60 is coupled to the first output stage 38 of the first multi-stage power amplifier 28. Accordingly, the first bias signal 48 is configured to activate or deactivate the first output stage 38 of the first multi-stage power amplifier 28. In a non-limiting example, the first biasing bump pad 60 is coupled to the first output stage 38 via a resistor R.sub.ref2, a transistor Q.sub.6, and a resistor R.sub.b2. The resistor R.sub.ref2 is further coupled to a ground via transistors Q.sub.4 and Q.sub.5. The first biasing bump pad 60 is further coupled to a transistor Q.sub.14 via a resistor R.sub.4.

(27) The second biasing bump pad 62 is coupled to the second output stage 42 of the second multi-stage power amplifier 32. Accordingly, the second bias signal 50 is configured to activate or deactivate the second output stage 42 of the second multi-stage power amplifier 32. In a non-limiting example, the second biasing bump pad 62 is coupled to the second output stage 42 via a resistor R.sub.ref4, a transistor Q.sub.10, and a resistor R.sub.b4. The resistor R.sub.ref4 is further coupled to the ground via transistors Q.sub.12 and Q.sub.11. The second biasing bump pad 62 is further coupled to a transistor Q.sub.13 via a resistor R.sub.3.

(28) The common biasing bump pad 64 is coupled to the first input stage 36 of the first multi-stage power amplifier 28 as well as the second input stage 40 of the second multi-stage power amplifier 32. Accordingly, the common bias signal 52 can be configured to activate or deactivate the first input stage 36 of the first multi-stage power amplifier 28 and the second input stage 40 of the second multi-stage power amplifier 32. In a non-limiting example, the common biasing bump pad 64 is coupled to the first input stage 36 of the first multi-stage power amplifier 28 via a resistor R.sub.ref1, a resistor R.sub.1, a transistor Q.sub.3, and a resistor R.sub.b1. The resistor R.sub.ref1 is further coupled to the ground via transistors Q.sub.1 and Q.sub.2. A coupling node A, which is located in between the resistor R.sub.1 and the transistor Q.sub.3, is coupled to the ground via diodes D.sub.1 and D.sub.2, and the transistor Q.sub.13.

(29) In the same non-limiting example, the common biasing bump pad 64 is coupled to the second input stage 40 of the second multi-stage power amplifier 32 via a resistor R.sub.ref3, a resistor R.sub.2, a transistor Q.sub.9, and a resistor R.sub.b3. The resistor R.sub.ref3 is further coupled to the ground via transistors Q.sub.7 and Q.sub.8. Another coupling node B, which is located in between the resistor R.sub.2 and the transistor Q.sub.9, is also coupled to the ground via diodes D.sub.3 and D.sub.4, and the transistor Q.sub.14.

(30) In one example, the bias circuit 44A is configured to activate the first multi-stage power amplifier 28 and deactivate the second multi-stage power amplifier 32 concurrently. In this regard, the bias controller 58 is configured to assert the first bias signal 48 and the common bias signal 52, while simultaneously de-asserting the second bias signal 50. Herein, an assertion of the first bias signal 48 and the common bias signal 52 means that the bias controller 58 generates the first bias signal 48 and the common bias signal 52 above respective biasing thresholds. In contrast, a de-assertion of the second bias signal 50 means that the bias controller 58 generates the second bias signal 50 below a respective biasing threshold.

(31) The bias controller 58 may assert the first bias signal 48 above a respective biasing voltage of the transistor Q.sub.6 to cause the transistor Q.sub.6 to be turned on. Accordingly, the battery voltage V.sub.BAT can be coupled to the first multi-stage power amplifier 28 to cause the first output stage 38 to be activated. The bias controller 58 may assert the first bias signal 48 above a respective biasing voltage of the transistor Q.sub.14 to cause the transistor Q.sub.14 to be turned on. Accordingly, a voltage at the coupling node B is pulled to the ground. As a result, the transistor Q.sub.9 is turned off to block the common bias signal 52 from the second input stage 40 of the second multi-stage power amplifier 32, thus causing the second input stage 40 of the second multi-stage power amplifier 32 to be deactivated. Notably, the diodes D.sub.3 and D.sub.4 are provided between the coupling node B and the ground to prevent excessive current drain from the common biasing bump pad 64 to the ground via the resistor R.sub.ref3, the diodes D.sub.3 and D.sub.3, and the transistor Q.sub.14.

(32) The bias controller 58 may assert the common bias signal 52 above a respective biasing voltage of the transistor Q.sub.3 to cause the transistor Q.sub.3 to be turned on. Accordingly, the battery voltage V.sub.BAT can be coupled to the first multi-stage power amplifier 28 to cause the first input stage 36 to be activated. The bias controller 58 may assert the second bias signal 50 below a respective biasing voltage of the transistor Q.sub.10 to cause the transistor Q.sub.10 to be turned off, thus blocking the battery voltage V.sub.BAT from the second multi-stage power amplifier 32 to cause the second output stage 42 to be deactivated.

(33) In this regard, since the first input stage 36 and the first output stage 38 of the first multi-stage power amplifier 28 are both activated, the first multi-stage power amplifier 28 is thus activated. In contrast, since the second input stage 40 and the second output stage 42 of the second multi-stage power amplifier 32 are both deactivated, the second multi-stage power amplifier 32 is thus deactivated.

(34) In another example, the bias circuit 44A is configured to deactivate the first multi-stage power amplifier 28 and activate the second multi-stage power amplifier 32 concurrently. In this regard, the bias controller 58 is configured to assert the second bias signal 50 and the common bias signal 52, while simultaneously de-asserting the first bias signal 48. Herein, an assertion of the second bias signal 50 and the common bias signal 52 means that the bias controller 58 generates the second bias signal 50 and the common bias signal 52 above respective biasing thresholds. In contrast, a de-assertion of the first bias signal 48 means that the bias controller 58 generates the first bias signal 48 below a respective biasing threshold.

(35) The bias controller 58 may assert the second bias signal 50 above a respective biasing voltage of the transistor Q.sub.10 to cause the transistor Q.sub.10 to be turned on. Accordingly, the battery voltage V.sub.BAT can be coupled to the second multi-stage power amplifier 32 to cause the second output stage 42 to be activated. The bias controller 58 may assert the second bias signal 50 above a respective biasing voltage of the transistor Q.sub.13 to cause the transistor Q.sub.13 to be turned on. Accordingly, a voltage at the coupling node A is pulled to the ground. As a result, the transistor Q.sub.3 is turned off to block the common bias signal 52 from the first input stage 36 of the first multi-stage power amplifier 28, thus causing the first input stage 36 of the first multi-stage power amplifier 28 to be deactivated. Notably, the diodes D.sub.1 and D.sub.2 are provided between the coupling node A and the ground to prevent excessive current drain from the common biasing bump pad 64 to the ground via the resistor R.sub.ref1, the diodes D.sub.1 and D.sub.2, and the transistor Q.sub.13.

(36) The bias controller 58 may assert the common bias signal 52 above a respective biasing voltage of the transistor Q.sub.9 to cause the transistor Q.sub.9 to be turned on. Accordingly, the battery voltage V.sub.BAT can be coupled to the second multi-stage power amplifier 32 to cause the second input stage 40 to be activated. The bias controller 58 may assert the first bias signal 48 below a respective biasing voltage of the transistor Q.sub.6 to cause the transistor Q.sub.6 to be turned off, thus blocking the battery voltage V.sub.BAT from the first multi-stage power amplifier 28 to cause the first output stage 38 to be deactivated.

(37) In this regard, since the first input stage 36 and the first output stage 38 of the first multi-stage power amplifier 28 are both deactivated, the first multi-stage power amplifier 28 is thus deactivated. In contrast, since the second input stage 40 and the second output stage 42 of the second multi-stage power amplifier 32 are both activated, the second multi-stage power amplifier 32 is thus activated.

(38) FIG. 3B is a schematic diagram of an exemplary bias circuit 44B, which can be provided in the power amplifier apparatus 26 of FIG. 2 as the bias circuit 44. In the bias circuit 44B, the first biasing bump pad 60 is coupled to the first input stage 36 of the first multi-stage power amplifier 28. Accordingly, the first bias signal 48 is configured to activate or deactivate the first input stage 36 of the first multi-stage power amplifier 28. In a non-limiting example, the first biasing bump pad 60 is coupled to the first input stage 36 via the resistor R.sub.ref1, the transistor Q.sub.3, and the resistor R.sub.b1. The resistor R.sub.ref1 is further coupled to a ground via the transistors Q.sub.1 and Q.sub.2. The first biasing bump pad 60 is further coupled to the transistor Q.sub.14 via the resistor R.sub.4.

(39) The second biasing bump pad 62 is coupled to the second input stage 40 of the second multi-stage power amplifier 32. Accordingly, the second bias signal 50 is configured to activate or deactivate the second input stage 40 of the second multi-stage power amplifier 32. In a non-limiting example, the second biasing bump pad 62 is coupled to the second input stage 40 via the resistor R.sub.ref3, the transistor Q.sub.9, and the resistor R.sub.b3. The resistor R.sub.ref3 is further coupled to the ground via the transistors Q.sub.7 and Q.sub.8. The second biasing bump pad 62 is further coupled to the transistor Q.sub.13 via the resistor R.sub.3.

(40) The common biasing bump pad 64 is coupled to the first output stage 38 of the first multi-stage power amplifier 28 as well as the second output stage 42 of the second multi-stage power amplifier 32. Accordingly, the common bias signal 52 can be configured to activate or deactivate the first output stage 38 of the first multi-stage power amplifier 28 and the second output stage 42 of the second multi-stage power amplifier 32. In a non-limiting example, the common biasing bump pad 64 is coupled to the first output stage 38 of the first multi-stage power amplifier 28 via the resistor R.sub.ref2, the resistor R.sub.1, the transistor Q.sub.6, and the resistor R.sub.b2. The resistor R.sub.ref2 is further coupled to the ground via the transistors Q.sub.4 and Q.sub.5. A coupling node A, which is located in between the resistor R.sub.1 and the transistor Q.sub.6, is coupled to the ground via diodes D.sub.1 and D.sub.2 and the transistor Q.sub.13. In the same non-limiting example, the common biasing bump pad 64 is coupled to the second output stage 42 of the second multi-stage power amplifier 32 via the resistor R.sub.ref4, the resistor R.sub.2, the transistor Q.sub.10, and the resistor R.sub.b4. The resistor R.sub.ref4 is further coupled to the ground via the transistors Q.sub.12 and Q.sub.11. Another coupling node B, which is located in between the resistor R.sub.2 and the transistor Q.sub.10, is coupled to the ground via diodes D.sub.3 and D.sub.4 and the transistor Q.sub.14.

(41) In one example, the bias circuit 44B is configured to activate the first multi-stage power amplifier 28 and deactivate the second multi-stage power amplifier 32 concurrently. In this regard, the bias controller 58 is configured to assert the first bias signal 48 and the common bias signal 52, while simultaneously de-asserting the second bias signal 50. Herein, an assertion of the first bias signal 48 and the common bias signal 52 means that the bias controller 58 generates the first bias signal 48 and the common bias signal 52 above respective biasing thresholds. In contrast, a de-assertion of the second bias signal 50 means that the bias controller 58 generates the second bias signal 50 below a respective biasing threshold.

(42) The bias controller 58 may assert the first bias signal 48 above a respective biasing voltage of the transistor Q.sub.3 to cause the transistor Q.sub.3 to be turned on. Accordingly, the battery voltage V.sub.BAT can be coupled to the first multi-stage power amplifier 28 to cause the first input stage 36 to be activated. The bias controller 58 may assert the first bias signal 48 above a respective biasing voltage of the transistor Q.sub.14 to cause the transistor Q.sub.14 to be turned on. Accordingly, a voltage at the coupling node B is pulled to the ground. As a result, the transistor Q.sub.10 is turned off to block the common bias signal 52 from the second output stage 42 of the second multi-stage power amplifier 32, thus causing the second output stage 42 of the second multi-stage power amplifier 32 to be deactivated. Notably, the diodes D.sub.3 and D.sub.4 are provided between the coupling node B and the ground to prevent excessive current drain from the common biasing bump pad 64 to the ground via the resistor R.sub.ref4, the resistor R.sub.2, the diodes D.sub.3 and D.sub.3, and the transistor Q.sub.14.

(43) The bias controller 58 may assert the common bias signal 52 above a respective biasing voltage of the transistor Q.sub.6 to cause the transistor Q.sub.6 to be turned on. Accordingly, the battery voltage V.sub.BAT can be coupled to the first multi-stage power amplifier 28 to cause the first output stage 38 to be activated. The bias controller 58 may assert the second bias signal 50 below a respective biasing voltage of the transistor Q.sub.9 to cause the transistor Q.sub.9 to be turned off, thus blocking the battery voltage V.sub.BAT from the second multi-stage power amplifier 32 to cause the second input stage 40 to be deactivated.

(44) In this regard, since the first input stage 36 and the first output stage 38 of the first multi-stage power amplifier 28 are both activated, the first multi-stage power amplifier 28 is thus activated. In contrast, since the second input stage 40 and the second output stage 42 of the second multi-stage power amplifier 32 are both deactivated, the second multi-stage power amplifier 32 is thus deactivated.

(45) In another example, the bias circuit 44B is configured to deactivate the first multi-stage power amplifier 28 and activate the second multi-stage power amplifier 32 concurrently. In this regard, the bias controller 58 is configured to assert the second bias signal 50 and the common bias signal 52, while simultaneously de-asserting the first bias signal 48. Herein, an assertion of the second bias signal 50 and the common bias signal 52 means that the bias controller 58 generates the second bias signal 50 and the common bias signal 52 above respective biasing thresholds. In contrast, a de-assertion of the first bias signal 48 means that the bias controller 58 generates the first bias signal 48 below a respective biasing threshold.

(46) The bias controller 58 may assert the second bias signal 50 above a respective biasing voltage of the transistor Q.sub.9 to cause the transistor Q.sub.9 to be turned on. Accordingly, the battery voltage V.sub.BAT can be coupled to the second multi-stage power amplifier 32 to cause the second input stage 40 to be activated. The bias controller 58 may assert the second bias signal 50 above a respective biasing voltage of the transistor Q.sub.13 to cause the transistor Q.sub.13 to be turned on. Accordingly, a voltage at the coupling node A is pulled to the ground. As a result, the transistor Q.sub.6 is turned off to block the common bias signal 52 from the first output stage 38 of the first multi-stage power amplifier 28, thus causing the first output stage 38 of the first multi-stage power amplifier 28 to be deactivated. Notably, the diodes D.sub.1 and D.sub.2 are provided between the coupling node A and the ground to prevent excessive current drain from the common biasing bump pad 64 to the ground via the resistor R.sub.ref2, the resistor R.sub.1, the diodes D.sub.1 and D.sub.2, and the transistor Q.sub.13.

(47) The bias controller 58 may assert the common bias signal 52 above a respective biasing voltage of the transistor Q.sub.10 to cause the transistor Q.sub.10 to be turned on. Accordingly, the battery voltage V.sub.BAT can be coupled to the second multi-stage power amplifier 32 to cause the second output stage 42 to be activated. The bias controller 58 may assert the first bias signal 48 below a respective biasing voltage of the transistor Q.sub.3 to cause the transistor Q.sub.3 to be turned off, thus blocking the battery voltage V.sub.BAT from the first multi-stage power amplifier 28 to cause the first input stage 36 to be deactivated.

(48) In this regard, since the first input stage 36 and the first output stage 38 of the first multi-stage power amplifier 28 are both deactivated, the first multi-stage power amplifier 28 is thus deactivated. In contrast, since the second input stage 40 and the second output stage 42 of the second multi-stage power amplifier 32 are both activated, the second multi-stage power amplifier 32 is thus activated.

(49) FIG. 3C is a schematic diagram of an exemplary bias circuit 44C, which can be provided in the power amplifier apparatus 26 of FIG. 2 as the bias circuit 44. In the bias circuit 44C, the first biasing bump pad 60 is coupled to the first output stage 38 of the first multi-stage power amplifier 28. Accordingly, the first bias signal 48 is configured to activate or deactivate the first output stage 38 of the first multi-stage power amplifier 28. In a non-limiting example, the first biasing bump pad 60 is coupled to the first output stage 38 via the resistor R.sub.ref2, the transistor Q.sub.6, and the resistor R.sub.b2. The resistor R.sub.ref2 is further coupled to a ground via the transistors Q.sub.4 and Q.sub.5. The first biasing bump pad 60 is further coupled to the transistor Q.sub.14 via the resistor R.sub.4.

(50) The second biasing bump pad 62 is coupled to the second output stage 42 of the second multi-stage power amplifier 32. Accordingly, the second bias signal 50 is configured to activate or deactivate the second output stage 42 of the second multi-stage power amplifier 32. In a non-limiting example, the second biasing bump pad 62 is coupled to the second output stage 42 via the resistor R.sub.ref4, the transistor Q.sub.10, and the resistor R.sub.b4. The resistor R.sub.ref4 is further coupled to the ground via the transistors Q.sub.12 and Q.sub.11. The second biasing bump pad 62 is further coupled to the transistor Q.sub.13 via the resistor R.sub.3.

(51) The common biasing bump pad 64 is coupled to the first input stage 36 of the first multi-stage power amplifier 28 as well as the second input stage 40 of the second multi-stage power amplifier 32. Accordingly, the common bias signal 52 can be configured to activate or deactivate the first input stage 36 of the first multi-stage power amplifier 28 and the second input stage 40 of the second multi-stage power amplifier 32. In a non-limiting example, the common biasing bump pad 64 is coupled to the first input stage 36 of the first multi-stage power amplifier 28 via the resistor R.sub.ref1, the resistor R.sub.1, the transistor Q.sub.3, and the resistor R.sub.b1. The resistor R.sub.ref1 is further coupled to the ground via transistor Q.sub.1. A coupling node A, which is located in between the resistor R.sub.1 and the transistor Q.sub.3, is coupled to the ground via diodes D.sub.1 and D.sub.2, and the transistor Q.sub.13. The transistor Q.sub.3 is coupled to the transistor Q.sub.1 via a resistor R.sub.fb2. The transistor Q.sub.3, the resistor R.sub.fb2, and the transistor Q.sub.1 collectively form a first closed-loop feedback path 68.

(52) In the same non-limiting example, the common biasing bump pad 64 is also coupled to the second input stage 40 of the second multi-stage power amplifier 32 via the resistor R.sub.ref3, the resistor R.sub.2, transistor Q.sub.9, and the resistor R.sub.b3. The resistor R.sub.ref3 is further coupled to the ground via transistor Q.sub.8. Another coupling node B, which is located in between the resistor R.sub.2 and transistor Q.sub.9, is coupled to the ground via diodes D.sub.3 and D.sub.4 and the transistor Q.sub.14. The transistor Q.sub.9 is coupled to the transistor Q.sub.8 via a resistor R.sub.fb1. The transistor Q.sub.9, the resistor R.sub.fb1, and the transistor Q.sub.8 collectively form a second closed-loop feedback path 70.

(53) Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.