Soft-switching voltage-edge-rate-limiting power inverter

Abstract

An auxiliary resonant soft-edge pole inverter circuit is provided. The power inverter circuitry may include a first pair of capacitors in parallel with a corresponding pair of main power switching modules, each power switching module comprising a switch and a diode in parallel and sharing a common central node with the first pair of capacitors. The power inverter circuit may further include a first pair of auxiliary switches connected in series with a first pair of inductors, respectively, to generate resonant current from a DC power source, the first pair of inductors also sharing the common central node. The power inverter circuitry may further include a second pair of auxiliary switches connected in series with a second pair of capacitors, respectively, the second pair of auxiliary switches also sharing the common central node, the circuit producing an alternating current output at the common central node.

Claims

1. An auxiliary resonant soft-edge pole inverter circuit, comprising: a first pair of capacitors connected in parallel with a corresponding pair of main power switching modules, each power switching module comprising a switch and a diode in parallel and sharing a common central node with the first pair of capacitors; a first pair of auxiliary switches directly connected in series with a first pair of inductors, respectively, to generate resonant current from a DC power source, the first pair of inductors also sharing the common central node; a second pair of auxiliary switches directly connected in series with a second pair of capacitors, respectively, the second pair of auxiliary switches also sharing the common central node, the auxiliary resonant soft-edge pole inverter circuit producing an alternating current output at the common central node; a second pair of diodes connected between the second pair of auxiliary switches and the first pair of inductors, respectively; a third pair of diodes connected in parallel with the second pair of auxiliary switches, respectively, and directly connected to the common central node; a fourth pair of diodes directly connected between the second pair of auxiliary switches and the DC power source, respectively; and a fifth pair of diodes directly connected in series with the first pair of auxiliary switches, respectively.

2. The auxiliary resonant soft-edge pole inverter circuit of claim 1, wherein at least one switch among the first pair of the switches and the second pair of switches comprises an insulated-gate bipolar transistor.

3. The auxiliary resonant soft-edge pole inverter circuit of claim 1, wherein at least one switch among the first pair of the switches and the second pair of switches comprise a metal-oxide-semiconductor field-effect transistor (MOSFET).

4. A power inverter circuit, comprising: a plurality of capacitors comprising a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; a plurality of switches comprising a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch; a plurality of inductors comprising a first inductor and a second inductor; and a plurality of diodes comprising a first diode, a second diode, a third diode, a fourth diode, a fifth diode, a sixth diode, a seventh diode, an eight diode, a ninth diode, and a tenth diode, wherein the first switch is connected in parallel with the first capacitor and the first diode, and the second switch is connected in parallel with the second capacitor and the second diode, wherein the third switch is directly connected in series with the first inductor and the fourth switch is directly connected in series with the second inductor, wherein the fifth switch is directly connected in series with the third capacitor and the sixth switch is directly connected in series with the fourth capacitor, wherein the first and second switches, the first and second diodes, the first and second capacitors, the first and second inductors, and the fifth and sixth switches share a common node, wherein the third diode is connected between the third switch and the first inductor, and the fourth diode is connected between the second inductor and the fourth switch, wherein the fifth diode is connected in parallel with the fifth switch and the sixth diode connected in parallel with the sixth switch, the fifth and sixth diodes both directly connected to the common node, wherein the seventh diode is directly connected between the fourth switch and a DC power source, and the eighth diode is directly connected between the third switch and the DC power source, and wherein the ninth diode is directly connected in series with the third switch, and the tenth diode is directly connected in series with the fourth switch.

5. The power inverter circuit of claim 4, wherein at least one of the plurality of switches comprises an insulated-gate bipolar switches.

6. The power inverter circuit of claim 4, wherein at least one of the plurality of switches comprise a metal-oxide-semiconductor field-effect transistor (MOSFET).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In the following description and drawings, identical reference numerals have been used, where possible, to designate identical features that are common to the drawings.

(2) FIG. 1 is a schematic and timing diagram illustrating an auxiliary resonant soft-edge pole inverter circuit according to various aspects.

(3) FIG. 2A is a schematic and timing diagram illustrating operation of a power inverter in a diode-to-switch (D2S) commutation during time Interval A according to various aspects.

(4) FIG. 2B is a schematic and timing diagram illustrating operation of a power inverter in a D2S commutation during time Interval B according to various aspects.

(5) FIG. 2C is a schematic and timing diagram illustrating operation of a power inverter in a D2S commutation during time Interval C according to various aspects.

(6) FIG. 2D is a schematic and timing diagram illustrating operation of a power inverter in a D2S commutation during time Interval D according to various aspects.

(7) FIG. 2E is a schematic and timing diagram illustrating operation of a power inverter in a D2S commutation during time Interval E according to various aspects.

(8) FIG. 2F is a schematic and timing diagram illustrating operation of a power inverter in a D2S commutation during time Interval F according to various aspects.

(9) FIG. 2G is a schematic and timing diagram illustrating operation of a power inverter in a D2S commutation during time Interval G according to various aspects.

(10) FIG. 2H is a schematic and timing diagram illustrating operation of a power inverter in a D2S commutation during time Interval H according to various aspects.

(11) FIG. 3A is a schematic and timing diagram illustrating operation of a power inverter in a switch-to-diode (S2D) commutation during time Interval H according to various aspects.

(12) FIG. 3B is a schematic and timing diagram illustrating operation of a power inverter in an S2D commutation during time Interval I according to various aspects.

(13) FIG. 3C is a schematic and timing diagram illustrating operation of a power inverter in an S2D commutation during time Interval J according to various aspects.

(14) FIG. 3D is a schematic and timing diagram illustrating operation of a power inverter in an S2D commutation during time Interval K according to various aspects.

(15) FIG. 3E is a schematic and timing diagram illustrating operation of a power inverter in an S2D commutation during time Interval L according to various aspects.

(16) FIG. 4 is a schematic and timing diagram illustrating operation of a power inverter circuit in a D2S commutation during time Interval C.sub.2 according to various aspects.

(17) FIG. 5A-B are state-plane plots of ARSEP and AAERP according to various aspects.

(18) FIG. 6 is a schematic illustrating an auxiliary resonant soft-edge pole inverter circuit with metal-oxide-semiconductor field-effect transistors (MOSFETs) according to various aspects.

(19) The attached drawings are for purposes of illustration and are not necessarily to scale.

DETAILED DESCRIPTION

(20) In the following description, some aspects will be described in terms that would ordinarily be implemented as software programs. Those skilled in the art will readily recognize that the equivalent of such software can also be constructed in hardware, firmware, or micro-code. Because data-manipulation algorithms and systems are well known, the present description will be directed in particular to algorithms and systems forming part of, or cooperating more directly with, systems and methods described herein. Other aspects of such algorithms and systems, and hardware or software for producing and otherwise processing the signals involved therewith, not specifically shown or described herein, are selected from such systems, algorithms, components, and elements known in the art. Given the systems and methods as described herein, software not specifically shown, suggested, or described herein that is useful for implementation of any aspect is conventional and within the ordinary skill in such arts.

(21) The present disclosure provides a soft-switching circuit to control an inverter output dv/dt with less loss, size and weight than prior-art dv/dt limiting methods, while eliminating the drawbacks of prior-art soft-switching circuits. A circuit topology is provided, referred to herein as an auxiliary resonant soft-edge pole (ARSEP) inverter that realizes soft-switching in all of the main and auxiliary switches and ensures that the inverter dv/dt is limited by circuit parameters. The second pair of resonant capacitors will always be fully pre-charged so the inverter dv/dt can be well-controlled.

(22) One embodiment of a single-phase ARSEP inverter is shown in FIG. 1, in which auxiliary circuits are illustrated using a dashed box. Capacitors C.sub.1 and C.sub.2 are connected in parallel with the main switch modules S.sub.1/D.sub.1 and S.sub.2/D.sub.2. Auxiliary switches S.sub.3 and S.sub.4 are connected in series with inductors L.sub.1 and L.sub.2 to generate resonant current.

(23) It is notable that S.sub.3 and S.sub.4 are unidirectional to prevent circulating current. Capacitors C.sub.3 and C.sub.4 have two roles. When S.sub.5 (S.sub.6) is on, C.sub.3 (C.sub.4) facilitates soft-switching of the main switches; when S.sub.5 (S.sub.6) is off, C.sub.3 (C.sub.4) and D.sub.3 (D.sub.4) serve as the turn-off snubber of S.sub.3 (S.sub.4). Diodes D.sub.5 and D.sub.6 enable pre-charging of C.sub.3 and C.sub.4, which prepares them for the next resonant process so that the dv/dt is well-controlled by circuit parameters. Diodes D.sub.7 and D.sub.8 direct residue energy in L.sub.1 and L.sub.2 back to the power source. It is assumed that C.sub.1=C.sub.2=C.sub.a, C.sub.3=C.sub.4=C.sub.b, and L.sub.1=L.sub.2=L. The “+” signs in FIG. 1 define the ports where positive current goes into the devices.

(24) Output Current Jo may be constant during commutation. Since inverter operation is symmetric for positive and negative output current I.sub.o, without losing generality, the circuit operation with a positive output current (I.sub.o>0) will be explained in the following subsections. The output current is generally constant during the commutation because the commutation time is relatively short.

A. Diode-to-Switch Commutation

(25) A commutation in which the output current I.sub.o commutes from a diode to a switch is called a diode-to-switch (D2S) commutation.

(26) Interval A (t<t.sub.0): Initially, S.sub.2 is ON while D.sub.2 actually conducts 1A (FIG. 2A). Voltages v.sub.C1=E, v.sub.C2=0, and v.sub.C3=E due to the presence of D.sub.5. In order to demonstrate the basic operation of the circuit, it is assumed that C.sub.4 is initially pre-charged, i.e., v.sub.C1,0=E. The situation where v.sub.C4,0<E will be discussed further below.

(27) Interval B (t.sub.0≤t<t.sub.1): At t.sub.0, a D2S commutation is commanded. Switch S.sub.2 is turned off while S.sub.3 and S.sub.5 are turned on (FIG. 2B). Since D.sub.2 is conducting, S.sub.2 is turned off with zero-voltage-zero-current switching (ZVZCS). Since i.sub.L1(t.sub.0)=0, S.sub.3 is turned on with ZCS. Since v.sub.C3(t.sub.0)=E, S.sub.5 is turned on with ZVZCS. Current i.sub.L1 increases substantially linearly.

(28) Interval C (t.sub.1≤t<t.sub.2): At t.sub.=1, i.sub.L1 increases to I.sub.o whereupon D.sub.2 stops conducting and L.sub.1 starts to resonate with C.sub.1, C.sub.2, and C.sub.3 (FIG. 2C). Voltage v.sub.o increases while v.sub.C4 stays at E since S.sub.6 is OFF.

(29) Interval D (t.sub.2≤t<t.sub.3): At t.sub.2, v.sub.o reaches E and the resonance stops (FIG. 2D). Current i.sub.L1 supplies I.sub.o. Since i.sub.L1>I.sub.o, the extra current circulates in the circuit shown in FIG. 2D. Based on simulation and experiment, the extra current circulates in the L.sub.1-D.sub.1-S.sub.3 and L.sub.1-S.sub.5-D.sub.3 loops. The current in the L.sub.1-D.sub.6-D.sub.8-S.sub.3 loop is negligible because there are two diodes in this loop. Ideally, ii is constant and is actually at its peak value

(30) $\begin{array}{cc}{I}_{L1p}=\frac{E}{Z_1}+I_o& \left(1\right)\end{array}$
where

(31) $\begin{array}{cc}{Z}_1=\sqrt{\frac{L}{2C_a+C_b}}& \left(2\right)\end{array}$

(32) Interval E (t.sub.3≤t<t.sub.4): At t.sub.3, S.sub.1 is turned on while S.sub.3 and S.sub.5 are turned off so i.sub.L1 starts to charge C.sub.3 (FIG. 2E). Since D.sub.1 is conducting, S.sub.1 is turned on with ZVZCS. Since v.sub.C3(t.sub.3)=0, S.sub.3 and S.sub.5 are turned off with ZVS. The energy in L.sub.1 at t.sub.3 is

(33) $\begin{array}{cc}{W}_{L1}=\frac{1}{2}{L}_1{I}_{L1p}^2>\frac{1}{2}{C}_b{E}^2+\frac{1}{2}{\mathrm{LI}}_o^2& \left(3\right)\end{array}$
Therefore, L.sub.1 has enough energy to charge C.sub.3 to E.

(34) Interval F (t.sub.4≤t<t.sub.5): At t.sub.4, C.sub.3 is charged to E whereupon D.sub.7 starts to conduct (FIG. 2F). The energy transferred to C.sub.3 is ½C.sub.bE.sup.2, so the energy remains in L.sub.1 is still higher than ½LI.sub.o.sup.2 according to (3). Therefore, i.sub.L1(t.sub.4)>I.sub.o, so D.sub.1 still conducts current. Current i.sub.L1 will decrease linearly, and the energy will flow back to the DC source.

(35) Interval G (t.sub.5≤t<t.sub.6): At t.sub.5, i.sub.L1 decreases to I.sub.o while D.sub.1 stops conducting and S.sub.1 starts to conduct (FIG. 2G). Current i.sub.L1 decreases linearly to zero at t.sub.6, which ends the D2S commutation.

B. Switch-to-Diode Commutation

(36) A commutation in which the output current commutes from a switch to a diode is called a switch-to-diode (S2D) commutation.

(37) Interval H (t.sub.6≤t<t.sub.7): Prior to an S2D commutation, the circuit is in Interval H where S.sub.1 is conducting (FIG. 3A).

(38) Interval I (t.sub.7≤t<t.sub.8): At t.sub.7, an S2D commutation is commanded so S.sub.1 is turned off while S.sub.4 and S.sub.6 are turned on. Inductor L.sub.2 starts to resonate with C.sub.1, C.sub.2, and C.sub.4 (FIG. 3B). Since v.sub.C1(t.sub.7)=0, S.sub.1 is turned off with ZVS. Since i.sub.L2(t.sub.7)=0, S.sub.4 is turned on with ZCS. Since v.sub.C4(t.sub.7)=E, S.sub.6 is turned on with ZVZCS. Voltage v.sub.o decreases and v.sub.C3 stays at E since S.sub.5 is OFF.

(39) Interval J (t.sub.8≤t<t.sub.9): At t.sub.8, v.sub.o decreases to zero and i.sub.L2 starts to circulate in the circuit (FIG. 3C). According to the simulation and experiment, i.sub.L2 circulates in the L.sub.2-S.sub.4-D.sub.2 and L.sub.2-D.sub.4-S.sub.6 loops. The current in the L.sub.2-S.sub.4-D.sub.7-D.sub.5 loop is negligible. Ideally, i.sub.L2 is constant and is at its peak value

(40) $\begin{array}{cc}{I}_{L2p}=\sqrt{I_o^2+{\left(\frac{E}{Z_1}\right)}^2}-I_o& \left(4\right)\end{array}$

(41) Interval K (t.sub.9≤t<t.sub.10): At t.sub.9, S.sub.2 is turned on while S.sub.4 and S.sub.6 are turned off. Current i.sub.L2 starts to charge C.sub.4 (FIG. 3D). Since D.sub.2 is conducting, S.sub.2 is turned on with ZVZCS. Since v.sub.C4(t.sub.9)==0, S.sub.4 and S.sub.6 are turned off with ZVS. Unlike the D2S commutation, L.sub.2 may not have sufficient energy to charge C.sub.4 up to E. Here, it is assumed that L.sub.2 has sufficient energy so v.sub.C4 reaches E.

(42) Interval L (t.sub.10≤t<t.sub.11): At t.sub.10, v.sub.C4 reaches E and D.sub.8 starts to conduct. Current i.sub.L2 decreases linearly to zero at t.sub.11, which completes an S2D commutation.

C. Alternative Mode of Operation

(43) According to (4), I.sub.L2p decreases when I.sub.o increases. The energy in L.sub.2 in Interval J is

(44) $\begin{array}{cc}{W}_{L2}=\frac{1}{2}{\mathrm{LI}}_{L2p}^2& \left(5\right)\end{array}$

(45) It may be less than ½C.sub.bE.sup.2, especially when I.sub.o is large or C.sub.a is much smaller than C.sub.b. Therefore, C.sub.4 may not be charged to E even absorbing all energy in L.sub.2. In this case, Interval K ends at t′.sub.10 when i.sub.L2 decreases to zero. The circuit operation will then skip Interval L and goes directly to Interval A. Then, the initial voltage of C.sub.4 for the next D2S commutation v.sub.C4,0 is less than E. In the next D2S commutation, C.sub.4 stays at v.sub.C4,0 in Interval B. Interval C will actually have two subintervals denoted by Intervals C.sub.1 and C.sub.2.

(46) Interval C.sub.1 (t.sub.1≤t<t.sub.1.5): This interval is similar to Interval C (FIG. 2C) except that v.sub.C4 stays at v.sub.C4,0.

(47) Interval C.sub.2 (t.sub.1.5≤t<t.sub.2): At t.sub.1.5, v.sub.o increases to v.sub.C4,0 and D.sub.6 starts to conduct current (FIG. 4). Inductor L.sub.1 starts to resonate with C.sub.1-4. When v, increases to E, i.sub.L1 increases to its peak value

(48) $\begin{array}{cc}{I}_{L1p}^{\prime }=\sqrt{{\left(\frac{E-v_{C4,0}}{Z_3}\right)}^2\left(1-\frac{Z_3^2}{Z_1^2}\right)+{\left(\frac{E}{Z_1}\right)}^2}+I_o& \left(6\right)\end{array}$
where

(49) $\begin{array}{cc}{Z}_3=\sqrt{\frac{L}{2C_a+2C_b}}& \left(7\right)\end{array}$

(50) Since Z.sub.3<Z.sub.1 and I.sub.L1p′>I.sub.L1P, according to (3), L.sub.1 has enough energy to charge C.sub.3 up to E, and the remaining i.sub.L1 is still greater than I.sub.o. This interval ends at t.sub.2 when v.sub.o increases to E. Voltage v.sub.C4 increases to E at t.sub.2, which prepares for the next S2D commutation. This pre-charging feature is not available in AAERP or DARCP, so they may result in high dv/dt.

D. Summary of Circuit Operation

(51) The gating signals of the ARSEP inverter can be generated based on the PWM signal and a time delay td, as shown in FIG. 3. The requirement on td is

(52) $\begin{array}{cc}{t}_d>t_B+t_C=\frac{I_{o}L}{E}+t_C& \left(8\right)\end{array}$
where

(53) $\begin{array}{cc}\frac{\pi }{2{\omega }_1}\le t_C<\frac{\pi }{2{\omega }_3}& \left(9\right)\end{array}$

(54) 0$\begin{array}{cc}{\omega }_1=\frac{1}{\sqrt{L\left(2C_a+C_b\right)}}& \left(10\right)\\ {\omega }_3=\frac{1}{\sqrt{L\left(2C_a+2C_b\right)}}& \left(11\right)\end{array}$

(55) From (8), td is a function of f.sub.0. The first term depends on circuit parameters, and the second term is mainly determined by allowable dv/dt. Therefore, it is possible to reduce t.sub.d through the parameter design to cater to high switching frequencies.

(56) If t.sub.d is constant, all gating signals can be generated without any sensing. Then, t.sub.d should be longer than the maximum possible voltage commutation time

(57) $\begin{array}{cc}{t}_{c,\max }={\left(t_B+t_C\right)}_{\max }=\frac{I_{p}L}{E}+\frac{\pi }{2{\omega }_3}& \left(12\right)\end{array}$

(58) where I.sub.p is the peak output current. If I.sub.o is measured by a current sensor, a lookup table can be used to determine the required t.sub.d. Then, the duration of Intervals D and J as well as the associated losses can be reduced without affecting the dv/dt performance.

(59) The circuit operation can be represented in a more concise way using a state-plane plot as shown in FIG. 5A. The two normalized states for the state-plane plot are defined as:

(60) $\begin{array}{cc}\overline{i}=\frac{i{Z}_1}{E},\overline{v}=\frac{v}{E}& \left(13\right)\end{array}$

(61) The moving directions of the state are indicated by arrows. From t.sub.1 to t.sub.1.5, the state follows a circular arc about the center (1, Ī.sub.o) with a rotational speed of ω.sub.1. Similarly, from t.sub.7 to t.sub.8, the state follows another circular arc about the center (0, Ī.sub.0) with the same speed ω.sub.1. If v.sub.C4,0=E, from Point P, the state will keep following the solid circular arc to Point Q. If v.sub.C4,0<E, from Point P, the state follows the dashed curve and goes to Point R.

(62) The state-plane plot of AAERP is shown in FIG. 5B. When C.sub.3 and C.sub.4 are fully charged, the state follows the solid line to Point Q. However, when C.sub.3 or C.sub.4 is lightly charged (which is likely when I.sub.o is large), the state moves from the origin to Point P and then to Point R, during which high dv/dt will occur. DARCP suffers a similar problem. ARSEP solves the problem by pre-charging C.sub.3 (C.sub.4) through diode D.sub.5 (D.sub.6) so that dv/dt can be well controlled by circuit parameters.

E. Voltage and Current Characteristics

(63) The peak inductor current, di/dt, and dv/dt in the ARSEP inverter can be derived as:

(64) $\begin{array}{cc}{I}_{L,\max }=\frac{E}{Z_3}+I_p=\left(\frac{1}{{\overline{Z}}_3}+1\right)I_p& \left(14\right)\\ \frac{d{i}_L}{{\mathrm{dt}}_{\max }}=\frac{E}{L}& \left(15\right)\\ \frac{d{v}_o}{{\mathrm{dt}}_{\max }}=\frac{0.8E{\omega }_1}{\Delta {\theta }_{T2D}\left({\overline{Z}}_1\right)}& \left(16\right)\end{array}$
where

(65) $\begin{array}{cc}\Delta {\theta }_{S2D}\left({\overline{Z}}_1\right)={\cos }^{-1}\frac{0.1}{\sqrt{{\overline{Z}}_1^2+1}}-{\cos }^{-1}\frac{0.9}{\sqrt{{\overline{Z}}_1^2+1}}& \left(17\right)\end{array}$
is the angle being swept when v.sub.o decreases from 0.9 to 0.1, as shown in FIG. 5A, because dv/dt defined by the NEMA MG-1 standard is the average voltage-change rate when the voltage changes between 10% and 90%. The normalized impedance is defined as

(66) $\begin{array}{cc}\overline{Z}=\frac{I_{p}Z}{E}& \left(18\right)\end{array}$

F. Example

Table 1—ARSEP Inverter Design Specification (Example)

(67) TABLE-US-00001 Item Value DC-bus voltage, E 200 V  Peak output current, I.sub.p 20 A  Maximum voltage edge rate, dv/dt.sub.limit  200 V/μs Maximum current edge rate, di/dt.sub.limit   50 A/μs Maximum inductor current, I.sub.L,limit 50 A  Switching frequency, f.sub.sw  10 kHz Maximum commutation time 5 μs

(68) By way of example, given the specifications in Table 1, an ARSEP inverter may be designed as follows. Referring to (14)

(69) $\begin{array}{cc}{\overline{Z}}_3>\frac{I_p}{I_{L,\mathrm{limit}}-I_p}=0.67& \left(19\right)\end{array}$

(70) It is selected that Z.sub.3=1 to limit the maximum inductor current. Based on (2) and (7), it can be concluded that Z.sub.1>Z.sub.3, so it is selected that Z.sub.1=1.1. Subsequently, according to (16) and (17)
Δθ.sub.S2D=0.583 rad  (20)

(71) $\begin{array}{cc}{\omega }_1=\frac{\frac{dv}{{\mathrm{dt}}_{\mathrm{limit}}}{\mathrm{\Delta \theta }}_{S2D}}{0.8E}=0.729\mathrm{rad}/\mathrm{\mu s}& \left(21\right)\end{array}$

(72) Based on Z.sub.1, Z.sub.3, and ω.sub.1, the values of the resonant components are calculated to be L=15 μH, C.sub.a=50 nF, and C.sub.b=25 nF. In order to maximize the benefit of soft switching, C.sub.b should be large enough so that S.sub.3 and S.sub.4 are over-snubbed. With this design, according to (12) and (14)-(16), t.sub.cmax=3.9 μs, I.sub.Lmax=40 A, di.sub.L/dt.sub.max=13.3 A/μs, and dv.sub.o/dt.sub.max=200 V/μs, which satisfy NEMA standards.

(73) FIG. 6 illustrates an example of the circuit. The switches may be include metal-oxide-semiconductor field-effect transistors (MOSFETs) (as shown in FIG. 6), an insulated-gate bipolar junction transistor (IGBT), or other suitable transistor. When the switches labelled S.sub.3 and S.sub.4 are MOSFET devices, there are diodes in series with the MOSFET “switch” (labeled D.sub.9 and D.sub.10 in FIG. 6), since the unidirectional switches S.sub.3 and S.sub.4 should conduct current in one direction only.

(74) The presently disclosed ARSEP circuit may be implemented to control power inverters in hybrid and electric vehicles, aircraft actuators, ship propulsion, and grid integration of renewable energy sources, or other applications.

(75) In various aspects and examples, the auxiliary resonant soft-edge pole inverter circuit may include a first pair of capacitors (C.sub.1 and C.sub.2) in parallel with a corresponding pair of main power switching modules, each power switching module comprising a switch (S.sub.1/S.sub.2) and a diode (D.sub.1/D.sub.2) in parallel and sharing a common central node with the first pair of capacitors.

(76) The auxiliary resonant soft-edge pole inverter circuit may further include a first pair of auxiliary switches (S.sub.3 and S.sub.4) connected in series with a first pair of inductors (L.sub.1 and L.sub.2) to generate resonant current from a DC power source (E), the first pair of inductors also sharing the common central node.

(77) The auxiliary resonant soft-edge pole inverter circuit may further include a second pair of auxiliary switches (S.sub.5 and S.sub.6) connected in series with a second pair of capacitors (C.sub.3 and C.sub.4). The second pair of auxiliary switches (S.sub.5 and S.sub.6) also sharing the common central node, the circuit producing an alternating current output at the common central node.

(78) The auxiliary resonant soft-edge pole inverter circuit may further include a second pair of diodes (D.sub.3 and D.sub.4) connected between the second pair of auxiliary switches (S.sub.5 and S.sub.6) and the inductors (L.sub.1 and L.sub.2).

(79) The auxiliary resonant soft-edge pole inverter circuit may further include a third pair of diodes (D.sub.5 and D.sub.6) connected in parallel with the second set of auxiliary switches (S.sub.5 and S.sub.6) and sharing the common central node.

(80) The auxiliary resonant soft-edge pole inverter circuit may further include a fourth pair of diodes (D.sub.7 and D.sub.9) connected between the second pair of auxiliary switches (S.sub.3 and S.sub.4) and the DC power source (E).

(81) The auxiliary resonant soft-edge pole inverter circuit may further include a fifth pair of diodes (D.sub.9 and D.sub.10) respectively connected in series with the second pair of auxiliary switches (S.sub.3 and S.sub.4).

(82) In various aspects and examples, the power inverter may include a plurality of capacitors comprising a first capacitor C.sub.1, a second capacitor C.sub.2, a third capacitor C.sub.3, and a fourth capacitor C.sub.4. The power inverter may further include a plurality of switches. The switches may include a first switch S.sub.1, a second switch S.sub.2, a third switch S.sub.3, a fourth switch S.sub.4, a fifth switch S.sub.5, and a sixth switch S.sub.6. The power inverter may include a plurality of inductors. The inductors may include a first inductor L.sub.1 and a second inductor L.sub.2. The power inverter may further include a plurality of diodes comprising a first diode D.sub.1 and a second diode D.sub.2.

(83) The first switch S.sub.1 may be connected in parallel with the first capacitor C.sub.1 and the first diode D.sub.1. The second switch S.sub.2 may be connected in parallel with a second capacitor C.sub.2 and a second diode D.sub.2.

(84) The third switch S.sub.3 may be connected in series with the first inductor L.sub.1. The fourth switch S.sub.4 may be connected in series with the second inductor L.sub.2.

(85) The fifth switch S.sub.5 may be connected in series with the third capacitor C.sub.3 and the sixth switch S.sub.6 may be connected in series with the fourth capacitor C.sub.4.

(86) The first switch S.sub.1, the second switch S.sub.2, the first diode D.sub.1, the second diode D.sub.2, the first capacitor C.sub.1, the second capacitor C.sub.2, the first inductor L.sub.1, the second inductor L.sub.2, and the fifth switch S.sub.5 and the sixth switch S.sub.6 may share a common node.

(87) In some examples, the diodes further comprise third diode D.sub.3 and fourth diode D.sub.4. The third diode D.sub.3 may be connected between the third switch S.sub.3 and the first inductor L.sub.1. The fourth diode D.sub.4 may be connected between the second inductor L.sub.2 and the fourth switch S.sub.4.

(88) In some examples, the diodes may further include a fifth diode D.sub.5 and sixth diode D.sub.6. The fifth diode D.sub.5 may be connected in parallel with the fifth switch S.sub.5 and the sixth diode D.sub.6 may be connected in parallel with the sixth switch S.sub.6. Further, the fifth diode D.sub.5 and the sixth diode D.sub.6 may both connect to the common node.

(89) In some examples, the diodes may include a seventh diode D.sub.7 and an eight diode D.sub.8. The seventh diode D.sub.7 may be connected between the fourth switch S.sub.4 and a DC power source E. The eight diode D.sub.8 may be connected between the third switch S.sub.3 and the DC power source E.

(90) In some examples, the third switch S.sub.3 and the fourth switch S.sub.4 may include MOSFETs. In such examples, the diodes may further include a diode D.sub.9 and a diode D.sub.10. The diode D.sub.9 may be connected in series with the third switch in S.sub.3. The diode D.sub.10 may be connected in series with the fourth switch in S.sub.4. Alternatively or in addition, the power inverter may include switch circuitry (identified as 602 and 604 in FIG. 6). The switch circuitry may include a series connection of a diode and a MOSFET.

(91) The invention is inclusive of combinations of the aspects described herein. References to “a particular aspect” and the like refer to features that are present in at least one aspect of the invention. Separate references to “an aspect” (or “embodiment”) or “particular aspects” or the like do not necessarily refer to the same aspect or aspects; however, such aspects are not mutually exclusive, unless so indicated or as are readily apparent to one of skill in the art. The use of singular or plural in referring to “method” or “methods” and the like is not limiting. The word “or” is used in this disclosure in a non-exclusive sense, unless otherwise explicitly noted.

(92) The invention has been described in detail with particular reference to certain preferred aspects thereof, but it will be understood that variations, combinations, and modifications can be effected by a person of ordinary skill in the art within the spirit and scope of the invention.