TRUE RANDOM NUMBER GENERATOR (TRNG) CIRCUIT USING A DIFFUSIVE MEMRISTOR

Abstract

A true random number generator device based on a diffusive memristor is disclosed. The random number generator device includes a diffusive memristor driven by a pulse generator circuit. The diffusive memristor produces a stochastically switched output signal. A comparator circuit receives the stochastically switched output signal from the diffusive memristor and generates an output signal having a random pulse width. An AND gate logic circuit is driven by a clock signal and the output signal from the comparator circuit. The AND gate logic circuit produces a combined output signal. A counter circuit receives the combined output signal from the AND gate logic circuit and generates a random bit string output signal.

Claims

1-4. (canceled)

5. A random number generator device, comprising: a diffusive memristor device driven by a pulse generator circuit, the diffusive memristor device producing a stochastically switched output signal; a comparator circuit that receives the stochastically switched output signal from the diffusive memristor device and generates an output signal having a random pulse width; an AND gate logic circuit driven by a clock signal and the output signal from the comparator circuit, the AND gate logic circuit producing a combined output signal; and a counter circuit that receives the combined output signal from the AND gate logic circuit and generates a random bit string output signal.

6. The random number generator device of claim 5, wherein the random bit string output signal has a frequency that is a fraction of the frequency of the clock signal.

7. The random number generator device of claim 5, wherein the counter circuit is one of a single bit counter circuit or a multi-bit counter circuit.

8. The random number generator device of claim 5, wherein the diffusive memristor device includes a dielectric layer formed from silver doped silicon oxide (Ag:SiO.sub.x), wherein the Ag:SiO.sub.x dielectric layer is disposed between a bottom electrode and a top electrode.

9. The random number generator device of claim 8, wherein at least one of the bottom electrode or the top electrode includes a layer of one of platinum (Pt), palladium (Pd) or titanium nitride (TiN).

10. The random number generator device of claim 8, wherein dielectric layer includes silver nanoparticles disposed within the silicon oxide, and wherein the diffusive memristor device further includes a silver layer formed between the dielectric layer and the top electrode.

11. The random number generator device of claim 8, wherein the diffusive memristor device is formed on a semiconductor substrate.

12. The random number generator device of claim 11, wherein the semiconductor substrate includes a silicon wafer substrate, and wherein the diffusive memristor device further includes a titanium adhesion layer interposed between the silicon wafer substrate and the bottom electrode.

13. The random number generator device of claim 5, wherein the diffusive memristor device includes a dielectric layer formed from a metal doped oxide, a metal bottom electrode and a metal top electrode, wherein the metal doped oxide is disposed between the metal bottom electrode and the metal top electrode.

14. The random number generator device of claim 13, wherein dielectric layer includes metal nanoparticles disposed within the oxide, and wherein the diffusive memristor device further includes an additional metal layer formed between the dielectric layer and the metal top electrode.

15. The random number generator device of claim 14, wherein a metal corresponding to the metal nanoparticles is same as a metal included in the additional metal layer.

16. The random number generator device of claim 15, wherein the metal includes one of silver (Ag), copper (Cu) or lithium (Li) and the oxide includes a silicon oxide (SiO.sub.x).

17. The random number generator device of claim 13, wherein at least one of the metal top electrode or the metal bottom electrode includes one of platinum (Pt), palladium (Pd) or titanium nitride (TiN).

18-20. (canceled)

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] FIGS. 1a-1e illustrate a schematic diagram of a diffusive memristor, and graphs of the switching and delay time characteristics of the diffusive memristor.

[0021] FIGS. 2a-2b illustrate a circuit diagram of a diffusive memristor based true random number generator (TRNG) circuit and graphs of waveforms corresponding to each stage of the circuit.

[0022] FIGS. 3a-3c illustrate an experimental demonstration of the diffusive memristor based TRNG circuit along with graphs showing the monitored output of a counter forming part of the circuit.

[0023] FIGS. 4a-4i illustrate graphical data showing the physical origin of stochastic delay time associated with the diffusive memristor.

[0024] FIG. 5 illustrates a schematic diagram showing various layers of a diffusive memristor device.

DETAILED DESCRIPTION

[0025] FIGS. 1a-1e illustrate a schematic diagram of a diffusive memristor 120, and graphs of the switching and delay time characteristics of the diffusive memristor, exhibiting a stochastic threshold switching behavior for the diffusive memristor device 120. FIG. 1a schematically shows an optical microscopic image of a 5×5 μm.sup.2 silver (Ag):silicon dioxide (SiO.sub.2) cross-point device 100 that forms a Ag:SiO.sub.2 diffusive memristor 120 used in conjunction with the true random number generator (TRNG) device described in greater detail below. The scale bar shown in FIG. 1a represents 50 μm.

[0026] The inset portion of FIG. 1a shows the geometry and layer structure of one implementation of the diffusive memristor 120. In some implementations, the diffusive memristor device 120 includes a metal bottom electrode layer 130, a metal top electrode layer 150, and a dielectric insulating switching layer 140 disposed between the top and bottom electrode layers. In some implementations, the top electrode 150 is formed of platinum (Pt) or gold (Au). In some implementations, the bottom electrode 130 is formed of platinum (Pt). In some implementations, the switching layer 140 is formed of Ag:SiO.sub.2. In some implementations, the thickness of a Pt top electrode layer 150 is 20 nanometers (nm), or in a range thereabouts. In some implementations, the thickness of a Au top electrode layer 150 is 30 nm, or in a range thereabouts. In some implementations, the thickness of a Pt bottom electrode layer 130 is 15 nm, or in a range thereabouts. In some implementations, the thickness of a Ag: SiO.sub.2 switching layer 140 is 10 nm, or in a range thereabouts.

[0027] In some implementations, a silver (Ag) layer 144 is formed and disposed between the Ag:SiO.sub.2 switching layer 140 and the top electrode layer 150 to provide an additional supply of silver (Ag) for optimal operation of the switching layer 140. In some implementations, the thickness of the Ag layer 144 is 5 nm, or in a range thereabouts.

[0028] FIG. 1b is a graph showing 50 consecutive DC switching cycles of the diffusive memristor 120 connected in series with a 4.7 mega-ohm (MΩ) resistor. The graph of FIG. 1b shows that the Ag: SiO.sub.2 based diffusive memristor device 120 does not require electroforming and exhibits reliable threshold under quasi-DC sweeps with a >10.sup.5 ON/OFF window, a sub-100 nano-ampere (nA) operation current and an extremely low (e.g., less than a pico-ampere (pA)) leakage current in the OFF state. The diffusive memristor device 120 abruptly reaches a low resistance state at a threshold voltage of around 0.5 volts (V) (ON-switching), followed by a spontaneous relaxation back to the high resistance state when the voltage sweeps back to below 0.3 V (self-OFF-switching), which demonstrates the volatility of the diffusive memristor device 120. Multiple switching sweeps of the diffusive memristor device 120 also shows cycle-to-cycle variations in threshold voltage, which demonstrates the stochastic nature of the switching behavior associated with the memristor device 120.

[0029] FIG. 1c is a graph showing pulse switching behavior of the diffusive memristor 120. Under a voltage pulse (300 microseconds (μs) in the case represented in the graph), the diffusive memristor device 120 abruptly turns ON after a finite delay time. The inset portion of FIG. 1c shows a circuit 180 that is used for the measurements with a resistor 182 connected in series with the diffusive memristor device 120. In some implementations, the resistor 182 is 120 kilo-ohm (kΩ). In greater detail, the graph of FIG. 1c shows the voltage across series resistor 182 (V.sub.out) when a 300 μs pulse of 0.5 V (V.sub.in) is applied to the memristor device 120. Under this specific applied input voltage V.sub.in, there is a finite delay time (called incubation period, which is of the order of 130 μs) before the output voltage V.sub.out abruptly increases, indicating ON-switching of the diffusive memristor device 120. When the applied voltage V.sub.in is removed, the diffusive memristor device 120 relaxes to the OFF state within 100 μs, as read by a subsequent 50 mV pulse.

[0030] FIG. 1d is a graph showing a distribution of the delay time for different input pulse amplitudes (0.4 to 0.9 volts (V) at 50 hertz (Hz)). From the graph of FIG. 1d it can be understood that a higher voltage (e.g., 0.9 V) leads to a shorter average delay time with a narrower distribution (184). The stochastic delay time can be linked to the process of forming the silver (Ag) conduction channel(s). The delay time is also dependent on pulse frequency. A higher frequency leads to shorter delay times even with the same voltage amplitude and pulse width (0.5 V, 300 μs).

[0031] FIG. 1e illustrates a schematic diagram showing various layers of the diffusive memristor device 120. As shown in FIG. 1e, in some implementations, the diffusive memristor 120 is fabricated on a semiconductor substrate 102. In some implementations, the substrate 102 is a silicon (Si) wafer. In other implementations, semiconductor substrate 102 is made of a material other than Si wafer.

[0032] In some implementations, an oxide layer, such as silicon oxide (SiO.sub.2) layer 104, is formed on the substrate 102. In some implementations, the circuit device 100 includes a titanium (Ti) layer 106 deposited on the surface of the silicon oxide layer 104 to create an adhesion surface for a bottom electrode 130. The Ti layer 106 has a thickness of 1.5 nm or in a range thereabout, in some implementations.

[0033] As described previously, in some implementations, the diffusive memristor device 120 includes a platinum (Pt) layer that creates the bottom electrode 130, and a silver doped silicon oxide (Ag: SiO.sub.2) layer that creates a dielectric insulating switching layer 140. In some implementations, the dielectric insulating switching layer 140 includes silver nanoclusters 142. In such implementations of the diffusive memristor device 120, an additional silver (Ag) layer 144 is formed on the dielectric insulating layer 140. A platinum (Pt) layer is formed on the silver layer 144 that creates the top electrode 150. In some implementations, a gold (Au) layer that creates a bonding electrode 160 is formed on the top surface of the top electrode 150. The bonding electrode 160 is included for better contact with measurement probes.

[0034] In the implementation shown in FIG. 1e, the Pt layer forming the bottom electrode 130 is fabricated to a thickness of approximately 15 nm, the Ag: SiO.sub.2 layer that creates the dielectric insulating switching layer 140 is fabricated to a thickness of approximately 10 nm, the additional Ag layer 144 is fabricated to a thickness of approximately 5 nm, and the Pt layer forming the top electrode 150 is fabricated to a thickness of approximately 20 nm. The optional Au layer forming the bonding electrode 160 is fabricated to a thickness of approximately 30 nm. Variations on the thickness of each layer are also within the scope of the present invention.

[0035] The Ag layer 5 nm 144 that is formed and disposed between the Ag: SiO.sub.2 switching layer 140 and the Pt top electrode 150 operates as a reservoir of silver (Ag) atoms to avoid any silver (Ag) depletion during switching. In some implementations, after fabrication, the silver (Ag) doping ratio in the Ag: SiO.sub.2 switching layer 140 is around 17% (atomic ratio), as determined by X-ray photoelectron spectroscopy (XPS). In some implementations, a 10 nm thick Ag: SiO.sub.2 switching layer 140 deposited on a thin SiN.sub.x membrane includes dense silver (Ag) nanoclusters 142 that are uniformly dispersed in the SiO.sub.2 matrix of the switching layer 140. The majority of the Ag nanoclusters 142 are 2 to 5 nm in diameter, with a few outliers of 10 nm.

[0036] FIGS. 2a-2b illustrate a circuit diagram of a diffusive memristor based true random number generator (TRNG) circuit 200, and graphs of waveforms corresponding to each stage of the circuit, respectively. As shown in FIG. 2a, the TRNG device 200 includes a diffusive memristor 260, a voltage source 202, a series resistor 204, a comparator (CMP) 210, an AND gate 220, a clock circuit 230, and a counter 240. In some implementations, the diffusive memristor 260 is an example of the diffusive memristor 120 described with respect to FIGS. 1a-1e. Accordingly, in the following sections, the description of the TRNG device 200 is with respect to the Ag: SiO.sub.2 diffusive memristor 120. However, the TRNG device 200 can include other types of diffusive memristor 260 in other implementations. For example, in some implementations, the diffusive memristor 260 is an example of the diffusive memristor 500 described with respect to FIG. 5.

[0037] FIG. 2b shows a series of six graph panels depicting schematic pulse waveforms at each stage of the circuit (as labeled in FIG. 2a at each of the numbered nodes 1-6), and illustrates the working principle of the diffusive memristor TRNG circuit 200. The stochastic delay time of the diffusive memristor 260 leads to variations of the pulse width (shown at node 3; comparator output 212) and then random numbers of clock pulses that are sent to the counter 240 (shown at node 5). The bit status (counter 240 output shown at node 6) before, during and after flipping is labeled in red in graph Panel 6. The bit flipping is triggered by the rising edge of the clock signal and hence the bit flipping frequency is half of the clock frequency. The output of the counter 240 is random due to the random times of bit flipping, as determined by the random numbers of clock pulses sent to the counter 240 (V.sub.5).

[0038] The stochastic delay time of the Ag: SiO.sub.2 based diffusive memristor 260 during ON-switching is utilized as the source of randomness for the TRNG circuit 200. In some implementations, the voltage source 202 generates a voltage pulse (V.sub.1) of fixed width that is applied across the diffusive memristor 260 and series resistor 204 (FIG. 2b, Panel 1). Under the applied voltage, the diffusive memristor 260 is turned ON and hence the output voltage (V.sub.2) across the series resistor 204 suddenly increases after a stochastic delay time (FIG. 2b, Panel 2). When voltage V.sub.2 is higher than a reference voltage to the comparator 210 (V.sub.ref), the comparator output voltage (V.sub.3) goes to a logic high level (FIG. 2b, Panel 3), and V.sub.2 and V.sub.3 fall back to zero when the single input pulse (V.sub.1) ends.

[0039] Since the delay time characteristic of the diffusive memristor 260 is random, the output voltage pulse V.sub.3 (212) from the comparator 210 has a random width. Voltage V.sub.3 (FIG. 2b, Panel 3) and a high frequency clock signal 232 (V.sub.4) from the clock circuit 230 (FIG. 2b, Panel 4) are sent to inputs of the AND gate 220, whose output voltage pulses (V.sub.5 in FIG. 2b, Panel 5) are sent to the counter 240. The graph in FIG. 2b, Panel 6 shows the binary bit (counter 240 output at node 5, in red (250) in FIG. 2b, Panel 6) stays at its pre-status (“0”) before the diffusive memristor 260 is turned ON, flips rapidly (triggered by clock signals 232) until the single input pulse (V.sub.1) from the voltage source 202 ends and then stays at its post-status (“1”). The bit flipping in the counter 240 is triggered by the rising edge of the clock signal 232, and hence has a frequency half of the clock frequency (232). The bit on which the counter 240 stops is random, because the stochastic delay time of the diffusive memristor 260 leads to a random pulse width from the comparator 210 (V.sub.3) and thus a random number of clock pulses from the clock circuit 230 that are sent to the counter 240. In some implementations, the random bit generation rate of the diffusive memristor based TRNG circuit 200 is increased using a multi-bit counter, with which one stochastic volatile switching event can produce more than one binary bit.

[0040] FIGS. 3a-3c illustrate an experimental demonstration of the diffusive memristor based TRNG circuit 200 circuit along with graphs showing the monitored output of a counter forming part of the circuit. FIG. 3a shows a photo of a circuit built on a breadboard. FIG. 3b shows the monitored output of one counter, for example counter 240, in response to an input voltage pulse (1 kHz) applied, for example by voltage source 202, to the diffusive memristor 2600. FIG. 3c shows the monitored output (of counter 240) of one random binary output flipping from “1”.fwdarw.“0”.fwdarw.“0”.fwdarw.“1”.fwdarw.“0” over continuous switching cycles.

[0041] The diffusive memristor based TRNG circuit 200 was experimentally implemented by a simple circuit built on a breadboard (FIG. 3a). To demonstrate the operation of the diffusive memristor based TRNG circuit 200, the lowest order bit at the output of the counter 240 was monitored by an oscilloscope during operation (FIG. 3b). A pulse train of constant amplitude (V.sub.1=0.4 V) with a pulse width of 300 μs and 700 μs spacing (i.e., 1 kHz frequency) was generated by the voltage source 202. As shown in FIG. 3b, the bit was initially at a low logic level (“0”). After the delay time (once the diffusive memristor 260 switched to the ON state) the counter 240 started receiving clock signals (at 4 MHz) from the clock circuit 230 and the bit flipped rapidly between low and high level (“0” and “1”). At the end of the input pulse (V.sub.1), the counter 240 stopped counting and kept its last state “1” until receiving the next counting signal. This “1” was the output bit read by a microcontroller connected to the TRNG circuit 200. Due to the stochastic nature of the delay time for each cycle, the output of the counter 240 after each pulse was totally unpredictable and flipped randomly between “0” and “1”. FIG. 3c shows the monitored binary bits randomly flipped from “1”.fwdarw.“0”.fwdarw.“0”.fwdarw.“1”.fwdarw.“0” during four continuous ON-switching cycles.

[0042] To assess the performance of the diffusive memristor based TRNG circuit 200, randomness testing for 76 million binary bits was carried out using the standard statistical testing package developed by the National Institute of Standards and Technology (NIST 800-22 test suite). A microcontroller's built-in 16-bit counter with 11.0592 MHz crystal oscillation frequency was used as the clock signal (e.g., representing the output signal of clock circuit 230) and the 6 lowest-order bits were collected. Each input pulse provides 6 random binary bits, for a total bit generation rate of 6 kbs.sup.−1. According to the test protocol, 76 million bits were collected and divided into 76 sequences (1 million bits each) for the NIST tests, which returned two statistics: P-value (except non-overlapping-template and random excursions variant), and pass rate. The bits are considered random and successfully pass the test only if the P-value is greater than 0.0001 and the pass rate exceeds the minimum value defined by NIST. As shown in Table 1, the diffusive memristor based TRNG circuit 200 passed all 15 NIST tests without any post-processing.

TABLE-US-00001 TABLE 1 Min. pass SUCCESS/ Parameter P-Value Pass Rate rate FAILURE  1. Approximate 0.00983  75/76 72/76 SUCCESS Entropy  2. Block 0.768138 75/76 72/76 SUCCESS Frequency  3. Cumulative  0.046525, 73/75, 74/76 72/76 SUCCESS Sums 0.426525  4. FFT 0.739918 75/76 72/76 SUCCESS  5. Frequency 0.477737 74/76 72/76 SUCCESS  6. Linear 0.350485 76/76 72/76 SUCCESS Complexity  7. Longest Run 0.042413 76/76 72/76 SUCCESS  8. Non — 11052/11248 10656/11248 SUCCESS Overlapping Template  9. Overlapping 0.592591 75/76 72/76 SUCCESS Template 10. Random — 360/368 344/368 SUCCESS Excursions 11. Random — 818/828 774/828 SUCCESS Excursions Variant 12. Rank 0.094936 76/76 72/76 SUCCESS 13. Runs 0.042413 75/76 72/76 SUCCESS 14. Serial  0.739918, 76/75, 76/76 72/76 SUCCESS 0.795464 15. Universal 0.000954 76/76 72/76 SUCCESS

[0043] FIGS. 4a to 4i illustrate graphical data showing the physical origin of stochastic delay time associated with the diffusive memristor. The stochastic delay time is clarified by nanoparticle dynamics simulations. FIG. 4a is a signal graph that shows the switching of the simulated memristor conductance when forty eight (48) rectangular voltage pulses are applied, with conductance normalized by the maximum memristor conductance, and FIG. 4b is a signal graph that shows the variation of voltage across the memristor, normalized by the threshold voltage Vth. FIG. 4c shows the switching to the low resistive state at time measured from the beginning of the corresponding pulses. The randomness of the resistive switching can be understood from this graph. FIG. 4d shows the two chosen resistive switches with different delay time and FIG. 4e shows corresponding particle probability distributions (over graph panels numbered 1-18) at points marked on FIG. 4d by yellow points having corresponding numbers 1-18. The inset in FIG. 4d shows the circuit model used during the simulation, and specifically shows that the diffusive memristor 120 is connected with a parallel capacitor and a series resistor. FIG. 4f shows potential normalized by thermal fluctuations across the sample used in the simulations. The delay time is composed of charging time of capacitor, time of silver (Ag) particles detaching from the silver (Ag) reservoir (144) and the silver (Ag) transportation time until the formation of conduction channel(s) within the switching layer 140, while the stochasticity is mainly attributed to the stochastic detaching process associated with the silver (Ag) particles.

[0044] For the simulations depicted in FIGS. 4a to 4e, the following voltage pulse parameters were used: voltage pulse duration κt.sub.p=80 (allowing enough time to switch to low resistive state for every pulse), inter-pulse interval κΔt=360 (allowing enough times to relax) and voltage amplitude V.sub.am/V.sub.th=1.5, potential versus temperature as in FIG. 4f (all times measured in unit of thermal relaxation time 1/κ). FIGS. 4g and 4h show the experimental delay time distributions in micro seconds under 0.4 V in FIGS. 4g and 0.7 V in FIG. 4h fitted by equation (2). FIG. 4i shows the fitting curve of to vs. pulse amplitudes according to equation (3). The fitted probability distributions appear to be consistent with experimental results.

[0045] With continued reference to FIGS. 4a to 4i, the physical origin of stochastic switching delay time in a Ag: SiO.sub.2 diffusive memristor is described in more detail. The physical origin and stochastic nature of the delay time is demonstrated by nanoparticle dynamical simulations, performed utilizing a generalized model that links electrical, nano-mechanical and thermal degrees of freedom. In these simulations, multi-switching-cycles under a train of pulses are simulated, unlike previous studies that mainly focused on response to a single pulse. In addition to the equations for heat and Ag-nanoparticle dynamics used in previous model, both external and intrinsic memristor capacitances are taken into account to better resemble real conditions during experiments. FIGS. 4a and 4b show the simulation results of forty eight (48) volatile switching cycles: switching of conductance G (normalized by its maximum value) is shown in FIG. 4a, while the voltage across the memristor is shown in FIG. 4b. With the same input pulses, random delay time during ON-switching is observed in FIG. 4c (with time counted from the moment when the corresponding voltage pulse was applied). The delay time statistics from simulations confirm a shorter delay time and a narrower distribution with increasing applied voltage amplitudes, similar to experimental results shown in FIG. 1d. Moreover, the obtained distribution statistics of simulated and measured delay times are very similar.

[0046] Evolution of silver (Ag) nanoparticle density distribution during two typical switching cycles (with G(t) presented in FIG. 4d) with quite different delay times is shown step by step in FIG. 4e (panels 1-18). A circuit model 416 used during the simulation is schematically shown in the inset in FIG. 4d. The circuit model 416 includes a diffusive memristor, a parallel capacitor and a series resistor. The capacitor represents capacitances from the device itself and also from the external circuits during electrical measurements such as cables and breadboards. As mentioned above, a series resistor is used to limit the operation current. When a voltage is applied, the voltage across the memristor gradually increases (FIG. 4d, the red curve 414). As soon as the voltage exceeds the threshold V.sub.th, silver (Ag) nano-particles can randomly detach from the silver (Ag)-electrode and form a large cluster nearby (FIG. 4e, Panel 1). Some particles escape from the cluster and start to diffuse towards the right electrode Pt (shown on the right side of memristor; inset FIG. 4d) driven by the electric field (FIG. 4e, Panel 2) and the memristor resistance starts to decrease resulting in higher energy dissipation. This results in positive feedback: more particles travelling towards the platinum (Pt) electrode enhance the device conductance, so the heat dissipation and temperature increase activating even more particle diffusion towards the platinum (Pt) electrode. Finally, some silver (Ag) particles arrive at the platinum (Pt) electrode and more and more particle start to diffuse from the large left cluster (FIG. 4e, Panel 3).

[0047] After that, silver (Ag) nanoparticles gradually migrate towards the other terminal (forming bridge spans, FIG. 4e, Panel 4) and the device resistance continuously drops (and its conductance rises, FIG. 4d) until the formation of silver (Ag) conduction channel(s) that bridge the two terminals and bring the device to the ON state (FIG. 4e, Panel 5). After the voltage pulse is off, the capacitor gradually discharges and the voltage across the memristor decays (FIG. 4d). The conduction channel breaks (FIG. 4e, Panel 6), then is further fragmented (FIG. 4e, Panel 7), and silver (Ag) particles are gradually absorbed by the silver (Ag) electrode driven by interfacial energy minimization (FIG. 4e, Panels 8, 9), bringing the device to the OFF state. For the case of a shorter delay (second cycle in FIG. 4d), particles detach faster and start to diffuse just after detaching from the silver (Ag)-electrode (FIG. 4e, Panels 10-14), while the relaxation part of the cycle (FIG. 4e. Panels 15-18) is almost the same as described above.

[0048] FIG. 4f shows the potential profile used for the simulation, which includes two energy scales: the interfacial energy responsible for detaching the Ag-electrode and formation of large metallic clusters near the device terminal and a weaker nanoparticle-pinning energy with many smaller wells between the electrodes. The delay time during ON switching includes three steps: (i) the formation of a voltage across the device terminal (charging capacitor), (ii) silver (Ag) nanoparticles escaping from the big potential wells associated with interfacial energy, corresponding to detaching from the left Ag reservoir/large Ag-cluster (FIG. 4e, Panels 1-2) and then (iii) transportation through the small pinning wells to the other terminal until the formation of silver (Ag) bridge(s) (FIG. 4e, Panels 2-4). The time needed to charge the capacitor (i) is deterministic in nature and delays setting voltage across the device, while the time for silver (Ag) transportation (iii) is very short (from spot 2 to spot 4, due to a fast increase in device temperature and, thus, very fast diffusion) and in practice can be neglected. Hence the stochasticity in delay time is mainly due to the silver (Ag) detaching process (ii). The escape time (t.sub.e) of a particle from the primary potential well (interfacial barrier) is naturally random and its distribution can be estimated by solving the Fokker-Plank equation with parabolic well and delta-function (for classical) or ground state (for quantum) initial distribution of silver (Ag)-nanoparticles in the potential minima. In classical limit the delay time distribution has the form shown by equation (1):

[00001]$\begin{array}{cc}P\left(t_e\right)=\frac{C{e}^{-\frac{A}{1-e^{-2{\mathrm{kt}}_e}}}}{\sqrt{1-e^{-2{\mathrm{kt}}_e}}}{\left(e^{2k{t}_e}-1\right)}^{-1}& \left(1\right)\end{array}$

In equation (1), A and k are fitting parameters related to potential curvature and depth of the well, and C is a normalization constant. Adding the deterministic RC effect, the distribution of stochastic delay time (t) can be determined using equations (2) and (3):

[00002]$\begin{array}{cc}P\left(t\right)=\frac{C{e}^{-\frac{A}{1-e^{-2k\left(t-t_0\right)}}}}{\sqrt{1-e^{-2k\left(t-t_0\right)}}}{\left(e^{2k\left(t-t_0\right)}-1\right)}^{-1}& \left(2\right)\\ t_0=-{\tau }_0\ln \left(1-\frac{V_{tr}}{V}\right)+t_1& \left(3\right)\end{array}$

where τ.sub.0 is characteristic “RC” time, V.sub.tr is a threshold when the memristor can switch to its low resistance state if V(t) >V.sub.tr, and t.sub.1 is associated with any other deterministic voltage-independent delays (e.g., characteristic temperature relaxation time). FIGS. 4g and 4h show the fitting results for the distribution of delay time under 0.4 V and 0.7 V from experiments based on Equation (2) while FIG. 4i shows the relationship between to and applied voltages with a curve fit based on Equation (3). Similarly, a very good agreement was obtained for the simulated distribution of delay time, and RC deterministic time delays to, thus, justifying a good agreement between experimental and simulated data. The results show that the stochastic process of silver (Ag) atoms detaching from the silver (Ag) reservoir is responsible for the stochasticity in delay time during ON-switching.

[0049] As discussed above, earlier approaches utilizing switching variations to build TRNG circuits have defined a threshold value for some switching characteristic (for example SET voltage or read current). In earlier approaches, the TRNG circuit will output a logic level 1 if the measured value exceeds the threshold, and output a logic level 0 otherwise. Complicated feedback and post-processing (such as von Neumann corrections) are needed to correct the ratio of 1 s to 0 s (bias) and improve the randomness to acceptable standards before running NIST tests. This is because the distribution of 0 and 1 bits generated is highly dependent on the exact distribution of the measured characteristic. If the median value shifts over time, then 0 and 1 outputs will not be equally probable.

[0050] In contrast to the earlier approaches, the diffusive memristor based TRNG circuit, e.g., TRNG device 200, more efficiently exploits variations in switching characteristics as sources of randomness, which is distinct from the previous threshold-value approaches. As shown in FIG. 2, the measured delay time is used to determine how many clock pulses are sent to a counter, e.g., counter 240. As a result, the mapping between analog delay time and a binary value implemented by the circuit 200 is highly chaotic when the clock frequency is fast. Each bit generated by the circuit 200 is very sensitive to even small variations in delay time, which makes the reliability of the described approach immune to global shifts/drifts in the delay time distribution with fast enough clock signal. The described circuit and method accordingly exploits intrinsic stochasticity in memristive devices for security applications.

[0051] In some implementations, pulse parameters are chosen to optimize bitrate and ensure the randomness of bits generated by the TRNG circuit 200. For example, in some implementations, a sufficiently large pulse width and amplitude is selected such that the TRNG devices turn ON every cycle. This prevents situations where there is no switching to the low resistive state during pulses, which can cause no random number generation. In some implementations, the interval between pulses is increased so that the device is always fully relaxed and nonzero delay time occurs during every ON-switching cycle. This prevents situations where there is insufficient time to relax to the high resistive state during the inter-pulse interval, which can also cause no random number generation.

[0052] Randomness from volatile switching with a high ON/OFF ratio is easier to exploit than small noises or current fluctuations. As a result, simpler circuits are required. The diffusive memristor TRNG circuit 200 can be built into memory subsystems, reducing chip area and increasing security. As revealed by simulations, the stochasticity is derived from the process of ionic motion, indicating that the diffusive memristor TRNG circuit 200 is more resistant to harsh environments than other electron-based TRNGs. Moreover, when the TRNG is operating, varying temperature affects the distribution by shifting its maximum towards lower time delays. However, the high frequency clock used to generate random numbers ensures that the randomness is not affected.

[0053] The current bit generation rate using the diffusive memristor TRNG circuit 200 is 6 kbs.sup.−1, which is sufficient for many encryption applications, such as Secure Session Layer (SSL) keys, car keys, and identification cards. In some implementations, to further increase the bit rate for other applications, a counter with more bits is used in the TRNG circuit. A higher frequency clock signal causes higher order bits to flip frequently to guarantee the generation of high quality random bit streams. This, however, comes at the cost of increased power consumption.

[0054] In some implementations, the diffusive memristor TRNG circuit 200 is combined with a linear-feedback shift register (LFSR) for higher bit rates with little increase in power consumption. The bitrate can be readily increased by 50 times (to around 300 kbs.sup.−1) implementing this method. In some implementations, a bitrate over 100 MHz is achieved by using a LFSR with more bits. In addition to circuit solutions, device engineering that leads to a higher switching speed of the diffusive memristors also improve the bitrate without changing the TRNG circuit. For example, the switching matrix can be changed. Alternatively, other memristive devices can be used. For example, niobium dioxide (NbO.sub.2) could be a good candidate for the TRNG circuit because of its sub-ns switching speed, albeit with relatively high operation current (around 300 μA) and voltage (around 1.5 V), even with small device size. In some implementations, parallel operation of several diffusive memristor TRNG devices leads to increased bitrates by simultaneously generating multiple random sequences. In some implementations, circuit area is reduced by three dimensional (3D) vertical stacking of the TRNG devices.

[0055] The operations of the diffusive memristor TRNG circuit (such as circuit 200) can be further characterized in response to temperature effects and long pulse cycling. The diffusive memristor TRNG circuit 200 still functions satisfactorily and passes the NIST tests even at 85° C. The experiment/testing collected 11 M binary bits under 1 kHz pulses (voltage amplitude: 0.5 V and pulse width: 300 μs). Unlike in operation at room temperature, only the 3 lowest-order bits can be collected, which means the bitrate decreases from 6 kbs.sup.−1 to 3 kbs.sup.−1. at 85° C. However, this will not be a problem if the clock frequency is increased accordingly. Utilizing a clock signal greater than 8×11.0592=88.4736 MHz, it is possible to keep the bitrate steady at 6 kbs.sup.−1. The required clock frequency is dependent on the spread of delay time, and so the decreased bitrate could be a result of the decreased standard deviation of delay time at high temperatures.

[0056] Possible degradation due to long pulse cycling is the other concern for the memristive switching based TRNG circuit. For example, in one case, 54 million bits were collected from a single diffusive memristor before the device failed and got stuck at the ON state (each cycle produced 6 random bits with endurance of around 10.sup.7 cycles). However, the randomness in memristors is sufficient to generate high quality random bits even after long cycling using the method and circuit described herein, in contrast to previous attempts to build memristive switching based TRNG circuits.

[0057] FIG. 5 illustrates a schematic diagram showing various layers of a diffusive memristor device 500. In some implementations, the diffusive memristor 500 exhibits similar switching and electrical characteristics as the diffusive memristor 120. In some implementations, the diffusive memristor 500 is an example of the diffusive memristor 260 used in the TRNG circuit 200.

[0058] As shown in FIG. 5, the diffusive memristor 500 is fabricated on a semiconductor substrate 500. In some implementations, the substrate 500 is a silicon (Si) wafer. In other implementations, semiconductor substrate 102 is made of a different material.

[0059] In some implementations, an oxide layer 504 is formed on the substrate 502. In some implementations, the oxide layer 504 includes a silicon oxide (SiO.sub.x). In some implementations, the oxide layer 504 includes silicon dioxide (SiO.sub.2).

[0060] In some implementations, a metal adhesion layer 506 is deposited on the surface of the oxide layer 504 to create an adhesion surface for a bottom metal electrode 530. In some implementations, the metal adhesion layer 506 has a thickness of 1.5 nm or in a range thereabout. In some implementations, the metal in the adhesion layer 506 is titanium (Ti).

[0061] The diffusive memristor device 500 includes a metal bottom electrode layer 530. In some implementations, the metal bottom electrode 530 is fabricated to a thickness of approximately 15 nm. In some implementations, the metal bottom electrode 530 includes one of platinum (Pt), palladium (Pd) or titanium nitride (TiN).

[0062] The diffusive memristor device 500 includes a metal-doped dielectric oxide layer 540 that creates a switching layer. In some implementations, the oxide layer 540 is fabricated to a thickness of approximately 10 nm. In some implementations, the oxide layer 540 includes metal nanoclusters 542. In some implementations, the oxide in the layer 540 is a silicon oxide (SiO.sub.x). In some implementations, the silicon oxide is silicon dioxide (SiO.sub.2). In some implementations, the metal in the layer 540 is one of silver (Ag), copper (Cu) or lithium (Li).

[0063] In some implementations of the diffusive memristor device 500 with the metal nanoclusters 542, an additional metal layer 544 is formed on the dielectric insulating layer 540, with the same metal that is used for doping the oxide layer 540 being used for the nanoclusters 542 and the additional metal layer 544. For example, in some cases, the oxide layer 540 comprises a silver (Ag)-doped silicon dioxide (SiO.sub.2) layer. In such implementations, the metal nanoclusters 542 are silver (Ag) nanoclusters, and the additional metal layer 544 includes a silver (Ag) layer. As another example, in some cases, the metal in the layer 540 is copper (Cu) and the additional metal layer 544 includes a copper (Cu) layer. As another example, in some cases, the metal in the layer 540 is lithium (Li) and the additional metal layer 544 includes a lithium (Li) layer.

[0064] The additional metal layer 544 operates as a reservoir of metal atoms to avoid any metal depletion during switching using the oxide layer 540. In some implementations, the additional metal layer 544 is fabricated to a thickness of approximately 5 nm. In some implementations, the metal nanoclusters 542 are not present. In some implementations, the additional metal layer 544 is not present.

[0065] The diffusive memristor device 500 includes a metal top electrode 550. In some implementations, the metal top electrode 550 is fabricated to a thickness of approximately 20 nm. In some implementations, the metal top electrode 550 includes the same metal as the metal bottom electrode 530. For example, the metal top electrode 550 can include platinum (Pt) when the metal bottom electrode 530 includes platinum (Pt). However, in other implementations, the metal top electrode 550 and the metal bottom electrode 530 include different metals. For example, in some implementations, the metal top electrode 550 includes one of palladium (Pd) or titanium nitride (TiN).

[0066] In some implementations, a bonding layer 560 is formed on the top surface of the metal top electrode 550. The bonding layer 560, which is optional, is included in some implementations for better contact with measurement probes. In some implementations, the bonding layer 560 is fabricated to a thickness of approximately 30 nm. In some implementations, the bonding layer 560 includes gold (Au) as the bonding metal. In other implementations, the bonding layer 560 includes platinum (Pt) as the bonding metal.

[0067] In the above manner, a novel diffusive memristor TRNG device utilizing stochastic delay time as the source of randomness can be implemented. The diffusive memristor TRNG circuit has a simple structure, and shows evident advantages in circuit complexity, scalability and power consumption, compared to prior TRNG devices.

[0068] Device Fabrication. In some implementations, the diffusive memristor device 120 (or the diffusive memristor device 260) described herein is fabricated on a silicon (Si) wafer 102 that includes a 100 nm thermally grown silicon oxide (SiO.sub.2) layer 104 on top that forms the substrate for the device. For the 5×5 μm.sup.2 micro-device (e.g., crossbar device 100), the bottom electrode is patterned by ultraviolet photolithography. After that, a 1.5 nm thick titanium (Ti) adhesion layer 106 and a 15 nm thick platinum (Pt) bottom electrode 130 are deposited sequentially in an electron beam evaporator, followed by a lift-off process in acetone. A 10 nm silver doped silicon oxide (Ag:SiO.sub.2) blanket layer 140 is prepared by radio-frequency (RF) co-sputtering from silicon oxide (SiO.sub.2) and silver (Ag) targets (power for SiO.sub.2: 270 watts (W) and Ag: 12 W). The top electrode is defined by a second photolithography step and a 15 s oxygen (O.sub.2) descum, metallization of a 5 nm silver (Ag) layer 144 using RF sputtering (100 W) and 20 nm platinum (Pt) layer 150/30 nm gold (Au) layer 160 deposition using electron beam evaporator and lift-off. The extra silver (Ag) layer 144 provides the diffusive memristor device 120, and more specifically the dielectric switching layer 140 a reservoir of silver (Ag) ions, while the gold (Au) layer 160 is added as an optional feature to improve the contact between electrical contact pads and probe tips.

[0069] Electrical Characterization. In one implementation, DC electrical characterizations are carried out using a Keysight B1500 semiconductor parameter analyzer operating in a voltage-sweep mode. In this implementation, voltage pulses are generated through a Keysight 33220A function/arbitrary waveform generator while the output waveforms are monitored by a Keysight MSO-X 3104T mixed signal oscilloscope. During all the electrical measurements, the bottom electrodes 130 are connected to a resistance to ground while the top electrodes 150/160 are biased.

[0070] Physical Characterization. The X-ray photoelectron spectroscopy (XPS) depth profile is acquired in a Physical Electronics Instruments (PHI) quantum 2000.

[0071] NIST Randomness Tests. In one implementation, a microcontroller (IAP15F2K61S2) is introduced to collect a large number of bits from the diffusive memristor TRNG device 200. To generate those sequences, input pulses (0.5 V, pulse width: 300 μs) at a frequency of 1 kHz are continuously sent by a voltage source 202 to the diffusive memristor 120 and a series resistor, for example resistor 204. The microcontroller's built-in 16-bit counter (11.0592 MHz) is used as the clock signal and collects the 6 lower-order bits (6 kbs.sup.−1). NIST Statistical Test Suite (Special Publication 800-22) are downloaded from the NIST websites and then run in a virtual Linux system machine using the GNU Compiler Collection (GCC) compiler. The test suite contains 15 randomness tests and each test targets a specific aspect of randomness. Each test returned two statistics, P-value (except non-overlapping-template and random excursions variant) and pass rate. The bits are considered to be random if and only if the P-value >0.0001 and the pass rate exceeds the minimum pass rate for each test.

[0072] Diffusive memristor dynamical simulations. To simulate resistive switching in the diffusive memristor 120, a generalized model is used where electric, heat and Ag-nanoparticle degrees of freedom were considered. In contrast, the memristor self-capacitance was also taken into account, which is important to describe the delay time distributions. The diffusion of silver (Ag)-nanoparticles is described by the Langevin equation (4), shown below:

[00003]$\begin{array}{cc}\eta \frac{d{x}_i}{dt}=-\frac{\partial U\left(x_i\right)}{\partial x_i}+\alpha \frac{V\left(t\right)}{L}+\sqrt{2\eta k_{B}T}\zeta & \left(4\right)\end{array}$

In equation (4), x.sub.i describes the location of the i.sup.th Ag-nanoparticle, t is time, and η is the viscosity of Ag-nanoparticles. The potential profile U(x.sub.i), where Ag nanoparticles diffuse, is formed due to interfacial interactions, attracting small particles to the Ag-electrode and to the large cluster located near the electrode as well as large number of small minima due to pinning of Ag-nanoparticles to the device inhomogeneities and SiO.sub.2 matric structure as well as repulsion from the Pt-electrode. The particular shape of potential (the potential profile used in simulations is shown in FIG. 4f) does not significantly affect the result. The only important property of the potential is the large minima associated with interfacial energy comparing with both temperature and depths of multiwell pinning potentials; the repulsive potential barrier of the Pt-electrode should be strong enough to ensure relaxation to high resistive state on a reasonable time scale when no voltage is applied. The second term in the right-hand-side of equation (4) is related to the electric bias/tilt of the potential in the electric field

[00004]$\frac{V\left(t\right)}{L}$

if Ag-nanoparticles accumulate effective charge a (the strength of this electric force tilt of the potential used in simulation is given in Supplementary FIG. 8a (inset)). The last term in equation (4) represents the unbiased δ-correlated white noise ζ: ζ(t)=0, ζ(0)ζ(t)=δ(t). The noise intensity is controlled by the temperature T (see FIG. 4f to estimate k.sub.BT.sub.0 with the Boltzmann constant k.sub.B and the background temperature T.sub.0 with respect to the potential used in the simulations). In particular, the noise is responsible for overcoming the interfacial barrier which is suppressed by the electric force (in the simulations the electric field decreases the interfacial potential well by a factor of 1.6 at V.sub.th); this results in switching the system to its low resistance state when a voltage pulse is applied. In addition, the noise generates the diffusion of Ag-nanoparticles toward the Ag-electrode when voltage is off resulting in the thermal relaxation of the memristors.

[0073] The heat dynamics in the memristor are described by Newton's cooling law, given by equation (5):

[00005]$\begin{array}{cc}\frac{dT}{dt}={ℂ}_T^{-1}Q-\kappa \left(T-T_0\right)& \left(5\right)\end{array}$

In equation (5), .sub.T is the memristor heat capacitance, Q=V(t).sup.2/R(x.sub.1, x.sub.2, . . . , x.sub.N) is Joule heat power with memristor resistance R(x.sub.1, x.sub.2, . . . , x.sub.N) which depends on Ag-nanoparticle locations, K is the heat transfer coefficient describing heat flux from the device. Note that the actual system temperature and the macroscopic-cluster temperature can be significantly different. We assume the resistance has a tunneling nature and is described by the equation R(x)=R(x.sub.1, x.sub.2, . . . , x.sub.N)=R.sub.tΣ.sub.0.sup.Ne.sup.(x.sup.i+1.sup.−x.sup.i.sup.)/λ where x.sub.0 and x.sub.N+1 are positions of the device terminals, R.sub.t is the resistance amplitude, and A is the tunneling length. The minimum possible resistance occurs when all Ag-nanoparticles are equally separated and has the value R.sub.min=(N+1)R.sub.te.sup.(x.sup.N+1.sup.−x.sup.0.sup.)/((N+1)λ) (the value of λ/L=0.12 was used for 1D, and 0.2 was used for 3D simulations).

[0074] As a distributed system with high resistance the memristor can have a capacitance (C.sub.M) which was not considered in previous models. In general, this capacitance could be different in the two memristor states, but for simplicity, it was assumed that C.sub.M is a constant and is not a function silver (Ag) nano-particle locations. A simple consideration of a circuit that includes the memristor resistance connected in parallel to the memristor capacitance results in equation (6) for voltage drop V(t) across the memristor:

[00006]$\begin{array}{cc}{\tau }_0\frac{dV}{dt}=V_{ex}\left(t\right)-\left(1+\frac{R_{ex}}{R\left(x\right)}\right)V& \left(6\right)\end{array}$

In equation (6), “RC” time τ.sub.0=C.sub.MR.sub.ex with the resistance R.sub.ex of external wires connected in sequence with the memristor. In some implementations, κτ.sub.0=16 and

[00007]$\frac{R_{ex}}{R_{\min }}=0.5$

are used.

Other Embodiments

[0075] Although a few implementations have been described in detail above, other modifications are possible. In addition, other components can be added to, or removed from, the described diffusive memristor and the diffusive memristor based true random number generator device. Accordingly, other implementations are within the scope of the following claims.