DEAD-TIME CONTROL METHOD FOR POWER ELECTRONICS CONVERTERS AND A CIRCUIT FOR THE APPLICATION OF THIS METHOD

Abstract

A dead time control method (100) comprising the steps of: converting the DC link voltage, output current and output voltage to digital values with an ADC (Analog to Digital converter) (102); calculating the hysteresis band for adaptive hysteresis current control using the values read by the ADC and updating the band value via recalculating it at each sampling time (103); calculating the IrefH and IrefL values using the hysteresis band and Iref (103a); generating the PWM signal by hysteresis current control (104), generating two auxiliary control signals as VP, VN (105); in the region where VP=1 and VN=0, applying of the drive signal of T.sub.1 without setting dead time wherein T.sub.1 is the conduction duration of an upper switch, and not applying the drive signal of T.sub.2 wherein T.sub.2 is the turn off duration of said upper switch and is the conduction duration of a lower switch (106).

Claims

1. A dead time control method to keep the switching frequency constant, for hysteresis current control in power electronics converters, comprising the steps (100) of; converting the DC link voltage, output current and output voltage to digital values with an ADC (Analog to Digital converter) (102); calculating the hysteresis bandwidth value for adaptive hysteresis current control using the values read by the ADC and updating the bandwidth value by recalculating it, in each sampling time (103), calculation of the IrefH and IrefL values of the upper and lower bands of the current reference using the calculated hysteresis bandwidth value of the step 103 and Iref (103a), generating the PWM signal by hysteresis current control (104), generating two auxiliary control signals as VP, VN (105), wherein in this step (105) these auxiliary control signals (VP, VN) are generated taking into account the regions in which the lower and upper band of the current reference (i.e. IrefL and IrefH) are positive and negative, applying, in the region where VP=1 and VN=0, the drive signal of T.sub.1 without setting dead time and not applying the drive signal of T.sub.2 wherein T.sub.1 is the conduction duration of an upper switch and T.sub.2 is the turn off time of said upper switch and is the conduction duration of a lower switch, (106), applying, in the region where VP=0 and VN=1, the driving signal of T.sub.2 without setting dead time and not applying the driving signal of T.sub.1 (107), and applying the driving signals of T.sub.1 and T.sub.2 by setting dead time in the region where VP=1 and VN=1 (108).

2. The method (100) according to claim 1, wherein the hysteresis bandwidth is calculated in step “Calculating the hysteresis bandwidth value for adaptive hysteresis current control using the values read by the ADC and updating the bandwidth value by recalculating it, in each sampling time (103)”, according to the formula of: $h=\frac{T_p.Math.\left(m_2+m_{\mathrm{ref}}\right).Math.\left(m_1-m_{\mathrm{ref}}\right)}{m_1+m_2}$ and ΔI=h/2 wherein T.sub.p is the switching period, ΔI is the hysteresis band, h is the amount of fluctuation in the current, m.sub.1 is the slope of the inductance current within time t1, m.sub.2 is the absolute value of the slope of the inductance current within time t2; m.sub.ref is the slope value of the current reference.

3. The method (100) according to claim 1, wherein the upper and lower bands of the current reference (IrefH and IrefL) in the step “Calculation of the IrefH and IrefL values of the upper and lower bands of the current reference using the calculated hysteresis bandwidth value of the step 103 and Iref (103a)”, are calculated via adding the calculated bandwidth value to the current reference to obtain the upper band value; and via deducting the calculated bandwidth value from the current reference, to obtain the lower band value.

4. The method (100) according to claim 1, wherein the first of the auxiliary control signals (VP) is generated in case the upper band (IrefH) is positive and the second of the auxiliary control signals (VN) is generated in case the lower band (IrefL) is negative in the step (105) of generating two auxiliary control signals VP, VN.

5. A dead time control circuit (2 or 2′ or 2′) for application of a method (100) according to claim 1, comprising a processor (10) converting the read analog values of the voltage and current into digital values; calculating the hysteresis bandwidth value and updating the bandwidth value via recalculating it in each sampling time; generating upper and lower band values (IrefH, IrefL) using the calculated hysteresis bandwidth via adding and subtracting the hysteresis bandwidth value to/from the current reference (Iref), generating the PWM signal relative to the hysteresis bandwidth; generating two auxiliary control signals, as one of which is VP when the upper band IrefH is positive and the other is VN when the lower band IrefL is negative and a logic circuit and a simulation circuit (1) generating driving signals of PWMH_ and PWML_.

6. The dead time control circuit (2) according to claim 5, comprising and gate (211), transistor (222), MOSFET (223) and resistors (221).

7. The dead time control circuit (2′ or 2″) according to claim 5, which is composed of FPGA and/or CPLD and/or DAC and/or comparator and/or logic elements.

8. The dead time control circuit (2′ or 2″) according to claim 5, comprising resistors (221), capacitor (225), diodes (224) and a NOT gate (212).

9. The dead time control circuit (2) according to claim 5, comprising 4 and gates (211), 2 NPN transistors (222), 1 MOSFET (223) and at least 8 resistors (221).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0104] FIG. 1: are topological views of the circuit.

[0105] FIGS. 1a and 1b: topological views of the circuit of which the subject method of the invention is applied in two different embodiments. The invention is applied to two level voltage sourced inverter in these embodiments (Application circuit).

[0106] FIG. 2: is the schematic diagram showing the generation of pulse wide regulated signals and the application of generated signals to a dead time control circuit in the circuit subject to invention. The signals of which the pulse wide is regulated are: the signals of PWM (Pulse-Width Modulation), EN_L (i.e.: VN) and EN_H (i.e.: VP). With this circuit the signals of PWMH (Pulse-Width Modulation High), PWML (Pulse-Width Modulation Low) are generated as well.

[0107] FIG. 3: is the dead time control circuit according to the invention.

[0108] FIG. 4: are the dead time control circuits.

[0109] FIGS. 4a and 4b: are the other dead time control circuits in which the subject method of the invention is applied.

[0110] FIG. 5: is the flow chart of the dead time control method according to the invention.

[0111] FIG. 6: is the graph showing the driving signals and current change in the hysteresis current control method in the conventional method in the prior art.

[0112] FIG. 7: is a graph showing the state that the current cannot be retained in the band due to the effect of dead time when a constant hysteresis band is used in the conventional method (in the prior art), that is, the state where the current flows out from the band.

[0113] FIG. 8: In the conventional method (in the prior art), when the adaptive (i.e. variable) hysteresis band is used, it is the graph showing the state that the current cannot be retained within the band i.e. the state that the current flows over the band due to the dead time effect.

[0114] FIG. 9: The variable definitions for the controlling of hysteresis current control with constant frequency.

[0115] FIG. 10: Generation of VP and VN auxiliary control signals.

[0116] FIG. 11: When fsw_ref=10 kHz, it is the simulation results while dead time prevention is active.

DESCRIPTION OF THE REFERENCES IN THE FIGURES

[0117] For comprehensibility of the invention, the parts in the attached figures have been individually numbered and corresponding definitions are provided below. [0118] 1. Invention circuit [0119] 2. Dead time control circuit [0120] 2′ Dead time control circuit [0121] 2″ Dead time control circuit [0122] 3. Application circuit [0123] 10. Processor [0124] 121. Comparator [0125] 122 DAC [0126] 123 Flip Flop [0127] 211 AND gate [0128] 212 NOT gate [0129] 221 Resistor [0130] 222 Transistor [0131] 223 MOSFET [0132] 224 Diode [0133] 225 Capacitor [0134] 226 Comparator [0135] Y: Load [0136] V.sub.s: Grid voltage [0137] L.sub.f: Filter inductance of inverter output [0138] C.sub.f: Filter capacitor [0139] L.sub.s: Filter inductance of the grid [0140] D.sub.1 and D.sub.2: Diodes [0141] T.sub.1 and T.sub.2: Switches [0142] ADC: An Analog-Digital Converter [0143] CAP: CAPTURE unit [0144] DSP: Digital Signal Processing unit [0145] Analog HCC: Analog Hysteresis Current Control [0146] 100. Dead time control method

DETAILED DESCRIPTION OF THE INVENTION

[0147] An invention circuit (1) and a dead time control circuit (2 or 2′) are used in the method according to the invention. PWM, PWMH, PWML and EN_L, EN_H signals, which are going to be used at the input of the dead time circuit (2 or 2′), are generated with the invention circuit (1). On the other hand, PWMH_ and PWML signals, which are going to be applied to power electronics converters, for example to a two level voltage sourced inverter, are generated in the dead time circuit (2 or 2′).

[0148] Application circuit (3) comprises a diode (D.sub.1) to which an upper switch (T.sub.1) is parallel connected and a diode (D.sub.2) to which a lower switch (T.sub.2) is parallel connected. At the output of the application circuit (3). which is a two level half bridge inverter topology, grid voltage (V.sub.s) and filter components (L.sub.f, C.sub.f, L.sub.s) as to be filter inductance of inverter output (L.sub.f), filter capacitor (C.sub.f) and filter inductance of the grid (L.sub.s) are provided. Ground of the grid voltage (V.sub.s) is connected to the middle point of DC link capacitors (225) which are serial connected at the input. DC input voltage is converted to AC voltage (V.sub.o) at the output via power elements. V.sub.o voltage of the output of the inverter, which is in the form of square wave, is converted into sinusoidal form with filter elements and the energy is transmitted to grid voltage (V.sub.s).

[0149] Invention circuit (1) is composed of a processor (10) and two AND gates (211) to which the processor (10) is connected with a NOT gate (212).

[0150] The processor (10) comprises an analog and a digital part. Digital Signal Processing (DSP) and digital control is provided at the digital part. The processor (10) comprises at least one comparator (121), at least one DAC (Digital-Analog Converter) (122) and at least one Flip Flop (123). The analog part comprises two comparators (121) and an SR flip flop (123) connected to these comparators (121). The analog part is the section realizing analog HCC in the processor. Controlling of the phase arm is provided with the analog part. The PWM signal comes from the output of the SR flip flop (123). EN_H (VP) and EN_L (VN) signals are generated via calculating hysteresis band in the processor (10). Driving signals (PWMH_ and PWML_) which is stated in the method is provided at the output of the dead time circuit (2, 2′ and 2″). Developed dead time circuit can be applied not only with analog elements but also can be provided using FPGA (Field Programmable Gate Array) or CPLD (Complex Programmable Logic Device).

[0151] Dead time control circuit (2) comprises 4 AND gates (211), 2 NPN transistors (222), 1 MOSFET (223) and resistors (221). In this circuit (2); a first resistor (R1) (221) is connected to the gate port of the element MOSFET (223) (M1) and a second resistor (R2) (221) is connected to the drain port of the MOSFET (223) (M1). PWM signal is applied to the MOSFET (M1) (223) via the first resistor (R1). VCC signal is applied to the drain port of the MOSFET (M1) (223) via the second resistor (R2) (221). One input pin (Indicated with the number 12 in FIG. 3) of a first AND gate (IC1D) (211) is connected in between MOSFET (M1) (223) and the second resistor (R2). A third resistor (R3) (221) is connected to the other input pin (indicated with the number 13 in FIG. 3) of this first AND gate (IC1D) (211) and resistor (R3) (221) is grounded from its other end. Furthermore, EN_L signal is applied to this input pin (13). First input pin (4) of a second AND gate (IC1B) (211) is connected to the output of this first AND gate (IC1D). Also a first NPN transistor (Q2) (222) is connected to the output of the first AND gate (211) via another resistor (R5) (221). VCC voltage is given to collector terminal of this transistor (Q2) (222) via yet another resistor (R7) (221). Emitter terminal is grounded. First input pin (10) of a third AND gate (IC1C) (211) is connected to the collector terminal of this first transistor (Q2) (222).

[0152] On the other hand, in this circuit (2), PWM signal is applied to the first pin (1) of a fourth AND gate (IC1A) (211). EN_H signal is applied to the second pin (2) as well. This second pin is also connected to the ground via another resistor (R4) (221). Second input pin (9) of the third AND gate (IC1C) is connected to the output (3) of this fourth AND gate (211). Also a second NPN type transistor (Q1) (222) is connected to this output (3) via another resistor (R6) (221). Collector of this second transistor (Q1) (222) is connected to VCC voltage via again another resistor (R8) (221). Emitter of this second transistor (Q1) (222) is again connected to the ground. Second input pin (5) of the second AND gate (IC1B) (211) is connected to the collector of this second transistor (Q1) (222).

[0153] In this circuit (2), the output (8) of the third AND gate (211) represents PWMH_ signal. The output (6) of the second AND gate (211) represents PWML_ signal. These two signals (PWMH_ and PWML_) are applied as the gate signals (gate signals of T.sub.1 and T.sub.2 switches of FIG. 1) to the power electronics element (for example two level voltage sourced inverter) of the application circuit (3) (FIG. 1).

[0154] Numerations of input and output pins of the elements presented in the dead time circuit (2″) of FIG. 3, are independent from the references presented above in the parts list.

[0155] In FIG. 3, PWM, EN_L (i.e. VN) and EN_H (i.e. VP) signals are generated in the processor (10). After producing signals with the processor (10), the dead time control circuit (2″) works as follows: In the state of EN_H(VP) signal is active and EN_L(VN) signal is passive (i.e. the major part of positive half period of output current), before being used of the dead time circuit (2) as the invention circuit, when PWM signal generated in the processor (10) is active, MOSFET (223) turns on and both input signals of the AND gate (IC1D) (211), using EN_L signal as input, become logic 0 as well. Therefore, the output of this AND gate (IC1D) (211) is 0. As a result of this, the transistor Q2 (222) remains in cut off mode and one input of the AND gate (IC1C) (211) becomes logic 1. On the other hand, since the output of the IC1D which is logic 1, is directly used as input of IC1B, one input of the IC1B becomes logic 1 as well, wherein IC1D is the first AND gate (211) and IC1B is the second AND gate (211). And now if we turn to the AND gate (211) in the name of IC1A: since PWM is active, one input of this AND gate (211) is logic 1 and its other input is logic 1 since EN_H is active. As a result, the output of IC1A is logic 1. Therefore, HX is also logic 1 and the output of the IC1C is high since both two inputs of the third AND gate (211) in the name of IC1C is logic1, and this signal is used as the gate signal of upper switch of the two level inverter. On the other hand, since the output of the AND gate (211) in the name of IC1A is logic 1, the transistor Q1 (222) turns on and the other input of the AND gate (211) in the name of IC1B becomes logic 0. Thus, the output of the AND gate IC1B is logic 0 and signal is not applied to the lower switch of the two level inverter. If PWM signal is not active, output of all AND gates (211) are logic 0 and the gate signals (gate signals of T.sub.1 and T.sub.2 switches in FIG. 1) are not active. This working principle realizes in the case of EN_H=1 and EN_L=0.

[0156] Let's examine the case of EN_H=0 and EN_L=1 (i.e. the major part of negative half period of the output current). If the PWM signal is not active, both inputs of AND gate IC1D (211) are logic 1 and the output of this AND gate (211) becomes logic 1. As a result, the transistor Q2 (222) turns on and one of the inputs of the AND gate IC1C (211) becomes logic 0. IF the other input of the AND gate (211) IC1C (211) is named as HX, this HX input is logic 0, since the output of the AND gate IC1A (211) is logic 0. Thus, at the output of the AND gate IC1C (211), logic 0 signal is provided. This signal is the signal of upper switch (T.sub.1) of the inverter and this means the gate signal (PWMH_) of the upper switch (T.sub.1) is not active. On the other hand, since output of the AND gate IC1A (211) is logic 0, the transistor Q1 (222) is in cut off and one input of the AND gate IC1B (211) becomes logic 1. If the other input of the AND gate IC1B (211) is named as LX, this LX input is also logic 1, since the output of the AND gate IC1D (211) is logic 1. As a result, the output of the AND gate IC1B (211) becomes logic 1 and in this case, gate signal (PWML_) of the lower switch (T.sub.2) of the inverter becomes active. IF PWM signal becomes active, output of the all AND Gates (211) become logic 0 and in this case, gate signals of none of the switches will not be active. This working principle realizes in the case of EN_H=0 and EN_L=1.

[0157] Finally let's examine the case of EN_H=1 and EN_L=1 (i.e. around the zero crossing zone of the output current) In here we should state specifically the following situation. Since getting the Q1 and Q2 transistors (222) in the cutoff mode are slow, this function is used as adding dead time in the present invention. If we clarify working principle for this range: if PWM signal is active, MOSFET (M1) (223) turns on and one input of the AND gate IC1D (211) becomes logic 0. As a result, the output of the AND gate IC1D is logic 0. Since both two inputs of the AND gate IC1A (211) is logic 1, its output is logic 1. If the PWM signal is not active, MOSFET (M1) (223) gets in cut-off state and both two inputs of the AND gate IC1D (211) are logic 1 and its output is logic 1. As to one input of the AND gate IC1A (211) is logic 0, the output of it, is logic 0. Active and passive states of PWM signal results in as such. One more time, let's check the active state of PWM signal. The condition of being active of the PWMH_ signal, to be applied to the upper switch (T.sub.1) in the inverter of FIG. 1, is possible when the two inputs of the AND gate IC1C (211) are logic 1. In here, the condition of adding dead time for PWMH_ signal, is provided using the characteristic of transistor Q2 (222) which gets into cut-off state slowly wherein the transistor Q2 (222) was in conduction state before. Since the transistor Q2 (222) gets into cut-off state slowly, the output of the AND gate IC1C (211) becomes logic 1 with delay and the rising edge of PWMH_ signal is delayed forwardly as long as the duration of this delay time. Likewise, when the PWM signal passes into passive state, the transistor Q1 (222) which is in conduction state, will turn off lately and the other input of AND gate IC1B (211), whose one input is logic 1, will become logic 1 with delay. Therefore, the rising edge of PWML_ signal will be delayed as long as this delay. Thus, process of adding dead time of the output current, at the zero crossing zone is provided in this way.

[0158] The method subject to invention (100) works as following steps. [0159] Reading the DC link voltage, output current and grid voltage by sensors (101), [0160] Converting the analog voltage and current values that are read to digital values with an ADC (102), [0161] Calculation of the hysteresis band by digital part of the processor (10) for adaptive hysteresis current control and updating the band value at each sampling time (103), [0162] Calculation of the IrefH and IrefL values using the hysteresis band and Iref (103a), [0163] Generating of the PWM signal by digital part of the processor (10) according to the hysteresis band (104), [0164] After generating PWM signal, generating two auxiliary control signals taking into account of the positive and negative regions of the lower and upper bands (IrefL and IrefH) of the current reference, i.e. generating the first one of the auxiliary control signals (VP) when upper band (IrefH), is in positive state and generating the second one of the auxiliary control signals (VN) when lower band (IrefL) is in negative state (105), [0165] Not applying negative signal in the region where current (Iref) is positive and thereby without applying dead time, only applying positive signal without delay (106). [0166] Likewise, not applying positive signal in the region where current (Iref) is negative and thereby, only generating negative signal without dead time (107), [0167] In the region where first auxiliary control signal (VP) is logic 1 and second auxiliary control signal (VN) is logic 1 and when upper band (IrefH) of the current is positive and lower band of the current is negative, generating signals via setting dead time between upper and lower signals and switching all the switches (T.sub.1 and T.sub.2) (108).

[0168] The steps of 102, 103, 104, 105 are processed by processor (10) in the method (100) subject to invention.

[0169] Furthermore, frequency is measured via reading the PWM signal by CAPTURE (CAP) unit in the method (100) subject to invention.

[0170] The process of measuring the frequency via reading the PWM signal by a CAPTURE (CAP) unit is executed for measuring the frequency and to see the result of the method.

[0171] In the step of 103, 2 comparators (121), a DAC (Digital Analog Converter) (122) and 1 SR flip flop (123) are used for applying adaptive hysteresis current control. In the preferred embodiment, these components are located in the processor (10). The step 103 is executed by the processor (10). How the calculation of the step 103 is provided, is defined below:

[0172] In order to solve the variable frequency problem of classical hysteresis control, it is a must to control the band. So as to make the switching frequency constant, the requirement for controlling the band is described on the FIG. 9.

[0173] The band value providing the switching frequency to be constant, is obtained mathematically using definitions indicated in FIG. 9. The variables used in the band calculation are listed below:

[0174] T.sub.p: Switching period

[0175] t.sub.1: conduction duration of the upper switch

[0176] t.sub.2: turn off duration of the upper switch and conduction duration of the lower switch at the same time

[0177] Δi.sub.1: the increase of the inductance current in t.sub.1 time

[0178] Δi.sub.2: the decrease of the inductance current in t.sub.2 time

[00001]$\frac{{\mathrm{di}}^{*}}{dt}\text{:}$

derivative of reference of current

[0179] Δi.sub.1: the increase of the reference of current in t.sub.1 time

[0180] Δi.sub.2: the increase of the reference of current in t.sub.2 time

[0181] ΔI: Hysteresis band

[0182] h: Fluctuation amount in current

[0183] m.sub.1: slope of inductance current in t.sub.1 time

[0184] m.sub.2: absolute value of slope in inductance current in t.sub.2 time

[0185] m.sub.ref: slope of current reference

[0186] In order to find h value for a constant period/frequency; in the equilibrium of T.sub.p=t.sub.1+t.sub.2; t.sub.1 and t.sub.2 time can be written in terms of m.sub.1, m.sub.2 and m.sub.ref slopes and circuit parameters. The increase amount in the inductance current in t.sub.1 range is obtained as follows:

Δi.sub.1=h+Δi.sub.1*  (1)

[00002]$\begin{array}{cc}\Delta i_1=\frac{{\mathrm{di}}_L}{\mathrm{dt}}{t}_1=m_1{t}_1& \left(2\right)\\ m_1=\frac{V_L\left(t_1\right)}{L}=\frac{V_{\mathrm{dcP}}-V_s}{L}& \left(3\right)\end{array}$

[0187] The change amount of the current reference in t.sub.1 range is found as follows:

[00003]$\begin{array}{cc}\Delta i_1^{*}=\frac{{\mathrm{di}}^{*}}{\mathrm{dt}}{t}_1=m_{\mathrm{ref}}{t}_1& \left(4\right)\end{array}$

[0188] The following equilibriums are obtained using the equilibriums (1) and (4).

[00004]$\begin{array}{cc}{m}_1{t}_1=h+m_{\mathrm{ref}}{t}_1& \left(5\right)\\ t_1=\frac{h}{m_1-m_{\mathrm{ref}}}& \left(6\right)\end{array}$

[0189] A similar way is used for obtaining t.sub.2.

[00005]$\begin{array}{cc}h=\Delta i_2+\Delta i_2^{*}& \left(7\right)\\ \Delta i_2=\frac{{\mathrm{di}}_L}{\mathrm{dt}}{t}_2=m_2{t}_2& \left(8\right)\\ m_2=-\frac{V_L\left(t_2\right)}{L}=\frac{V_{\mathrm{dcN}}+V_s}{L}& \left(9\right)\end{array}$

[0190] Is obtained. The change amount of the current reference in t.sub.2 range is as follows:

[00006]$\begin{array}{cc}\Delta i_2^{*}=\frac{{\mathrm{di}}^{*}}{\mathrm{dt}}{t}_2=m_{\mathrm{ref}}{t}_2& \left(10\right)\end{array}$

[0191] Via using (7), (8) and (10):

[00007]$\begin{array}{cc}h=m_2{t}_2+m_{\mathrm{ref}}{t}_2& \left(11\right)\\ t_2=\frac{h}{m_2+m_{\mathrm{ref}}}& \left(12\right)\end{array}$

[0192] Is obtained. Total period is calculated using the equilibriums (6) and (12).

[00008]$\begin{array}{cc}{T}_p=t_1+t_2& \left(13\right)\\ T_p=\frac{h}{m_1-m_{\mathrm{ref}}}+\frac{h}{m_2-m_{\mathrm{ref}}}& \left(14\right)\end{array}$

[0193] From here, hysteresis band for a constant period is:

[00009]$\begin{array}{cc}h=\frac{T_p.Math.\left(m_2+m_{\mathrm{ref}}\right).Math.\left(m_1-m_{\mathrm{ref}}\right)}{m_1+m_2}& \left(15\right)\end{array}$

[0194] obtained as ΔI=h/2. Via adding this obtained band value to the current reference, the upper band value is obtained; and via deducting this obtained band value from the current reference, the lower band value is obtained.

[0195] A processor unit (10), for example a microprocessor can be used in the step 104, for generating PWM signal.

[0196] Control signals generated in the step 105 are indicated in FIG. 10 as VP and VN signals.

[0197] After generating PWM signal in the step 105 in the method (100) subject to invention, firstly two auxiliary control signal are produced as VP and VN showed in FIG. 10, taking into account the regions wherein lower band (IrefL) and upper band (IrefH) of the current reference are positive and negative. VP signal represents the positive state of the upper band (IrefH). In other words, the signal VP is the signal which is logic 1 when the upper band is positive and logic 0 when the upper band is negative. VN signal represents the negative state of the lower band (IrefL). In other words, the signal VN is the signal which is logic 1 when the lower band is negative and logic 0 when the lower band is positive. The aim of these signals is not applying negative signal in the region where the current is positive and thereby only applying positive signal without setting dead time and without delay. Likewise, positive signal will not be applied in the region where current is negative, only negative signal will be generated without dead time. In other words, when the upper current reference (IrefH) is positive, due to the reason that only upper switch (T.sub.1) and lower diode (D.sub.2) will be in conduction, dead time is not added to the signal of upper switch (T.sub.1) and signal is not applied to the lower switch (T.sub.2). Likewise, when the lower current reference (IrefL) is negative, due to the reason that only lower switch (T.sub.2) and upper diode (D.sub.1) will be in conduction, dead time is not added to the driving signal of lower switch (T.sub.2). When upper band of the current (IrefH) is positive and the lower band (IrefL) of it is negative, the signals are generated via setting dead time in between lower and upper signals. Thanks to the dead time generated in this way, overflowing outside the band is prevented and holding the frequency constant is possible.

[0198] If the signal of the current becomes both positive and negative within the switching period, dead time will be set between the signals and both switches will be switched. This region (i.e., the region where VP=logic 1 and VN=logic 1, or the region in which the EN_H=logic 1 and EN_L=logic 1 in the dead time circuit (2) according to the invention) corresponds to the region where the current change is not very fast. Therefore, no significant overflow occurs in this range and the last generated gate signals are applied to the switches (T.sub.1 veT.sub.2). (It is applied to the output of the dead time circuit (2, 2, 2″) of FIG. 3 or FIG. 4 and to the application circuit (3) of FIG. 1.

[0199] In the present invention, the processor (10) further generates VP and VN signals and upper (IrefH) and lower (IrefL) band values. These upper and lower band values (IrefH, IrefL) are obtained by adding and subtracting the bandwidth value to the current reference (Iref) wherein the bandwidth value is found by calculation. In adaptive hysteresis current control, this band value is calculated and updated at each sampling period. Thus, a variable band value is obtained within one period of the current reference. Thus, the frequency is kept constant. The method according to the invention can also be applied to constant hysteresis band current control. However, since the frequency is desired to be constant in the applications, adaptive hysteresis current control with constant frequency is sampled in this specification. The analog part of the processor is the unit which performs the classical hysteresis current control. When the output current passes the upper band (IrefH), PWM becomes 0 (PWM=0) while PWM becomes 1 (PWM=1) when the current passes the lower band (IrefL). Thus, VP, VN and PWM signals are generated by processor (10). PWMH and PWML signals are obtained thanks to the method of the invention. However, in the zero crossing region of the output current, both VP and VN become logic 1. In this case, both the upper (T.sub.1) switch and the lower (T.sub.2) switch are actively used in the application circuit (3). In this case, dead time must be added to the rising edges of the switches. However, this dead time has no adverse effect on the method of the invention in current control.

[0200] In the other dead time circuits (2′ and 2″) (which are also used in the simulation) to which the method (100) is applied, the dead time addition process to the rising edge of the gate signal is performed with the structure composed of resistor (221), capacitor (225) and diode (224). Equivalent two different dead time circuit (2′ and 2″) are used for upper and lower switches.

[0201] The dead time circuit (2′) of FIG. 4-a comprises a parallel connected resistor (221) and a diode (224). PWMH signal is applied to this group. The output of the group consisting of this resistor (221) and diode (224) is connected to both a capacitor (225) and the + end of a comparator (226). The − end of the comparator (226) is connected to a power source. The power supply is grounded. The output of the comparator (226) is connected to a NOT gate (212) and the output of the NOT gate (212) is connected to an input of an AND gate (211). The other input of this AND gate (211) is provided with a PWML signal. The PWML_ signal is received from the output of this AND gate (211).

[0202] The dead time circuit (2″) of FIG. 4-b comprises a resistor (221) and a diode (224) connected in parallel. PWML signal is applied to this group. The output of the group consisting of this resistor (221) and diode (224) is connected to both a capacitor (225) and the + end of a comparator (226). The − end of the comparator (226) is connected to a power source. The power supply is grounded. The output of the comparator (226) is connected to a NOT gate (212) and the output of the NOT gate (212) is connected to an input of an AND gate (211). The PWMH signal is provided to the other input of this AND gate (211). The PWMH_ signal is received from the output of this AND gate (211).

[0203] The dead time circuit (2′) in FIG. 4-a works as follows: The PWML_ signal is applied to the lower switch (T.sub.2) in the application circuit (3). In order of this signal to be active, both inputs of the AND gate with the number 211 (211) must be logic 1. PWML refers to a signal without dead-time. Our aim is to shift the rising edge of this signal as the duration as dead time. So this signal is already logical 1. For the other input of AND gate (211) to be logic 1, the output of comparator (226) must be active. There is a constant voltage supply in the negative input of comparator (226). The positive input of comparator (226) is the voltage of the capacitor (225). This capacitor is rapidly charged via diode (224) when PWMH is active, and slowly discharged via resistor (221) when PWMH is not active. While the capacitor (225) is discharged, the PWML_ signal is not generated until the voltage value of the capacitor (225) falls below the value of the voltage source connected to the negative input of the comparator (226). Thus, the rising edge of the PWML signal is delayed as long as the dead time. A similar process is performed in the other dead time circuit (2″) of FIG. 4-b to generate the PWMH_ signal. As a result, the gate signals of the switches (T.sub.1, T.sub.2) are thus obtained.

[0204] When there is no dead time, the frequency change obtained by simulation is indicated by fsw. The received simulation results are indicated in FIG. 11 in the case when the desired reference switching frequency as to be constant, in other words the frequency at which the user wants to work is fsw_ref=10 kHz and when the dead time method is active. In here, the fluctuation in the switching frequency appears to be very low. In this embodiment, the method (100) is applied to two-level single-phase voltage sourced inverters. It has been shown that dead time problems are significantly reduced by this way. The developed method (100) can also be applied to three-level inverters and other power electronics converters.

[0205] The invention is not limited to the embodiments described above, and the person skilled in the art can easily introduce different embodiments of the invention. They should be considered within the scope of the invention as claimed by the claims.