BUILDING BLOCK FOR ELECTRO-OPTICAL INTEGRATED INDIUM-PHOSPHIDE BASED PHASE MODULATOR

Abstract

A photonic integrated circuit, PIC, comprising a plurality of semiconductor layers on a substrate, the plurality of semiconductor layers forming a PIN or PN doping structure, the PIC comprising a waveguide arranged for conducting light waves; an optical element connected to the waveguide, wherein the optical element, in operation, is in reverse-bias mode, and wherein the optical element comprises a contact layer arranged for connecting to a voltage source; wherein the waveguide comprises conducting contacts proximal to the optical element, and wherein the PIC further comprises at least one isolation section arranged in between the optical element and the conducting contacts. Corresponding methods of operation of such a PIC are also presented herein.

Claims

1. A photonic integrated circuit, PIC, comprising a plurality of semiconductor layers on a substrate, the plurality of semiconductor layers forming at least one of a PIN or PN doping structure, the PIC comprising: a waveguide arranged for conducting light waves, the waveguide comprising a waveguiding layer, which is one of the layers of the plurality of semiconductor layers; an optical element comprising a waveguiding layer, which is one of the layers of the plurality of semiconductor layers, which waveguiding layers of the waveguide and the optical element are connected to one another, wherein the optical element is operable in reverse-bias mode, and wherein the optical element comprises a contact layer arranged for connecting to a voltage source, wherein the waveguide comprises at least one conducting contact proximal to the optical element; and at least one isolation section arranged between the contact layer and the at least one conducting contact.

2. The photonic integrated circuit according to claim 1, wherein the at least one isolation section is arranged between the optical element and the at least one conducting contact.

3. The photonic integrated circuit according to claim 1, wherein the at least one conducting contact is configured on both sides of the optical element with respect to a direction of the light waves in the waveguide.

4. The photonic integrated circuit according to claim 2, wherein the at least one conducting contact is configured on both sides of the optical element with respect to a direction of the light waves in the waveguide.

5. The photonic integrated circuit according to claim 1, wherein the at least one conducting contact extends over substantially the entire waveguide.

6. The photonic integrated circuit according to claim 1, wherein at least one of: the at least one isolation section is arranged between the optical element and the at least one conducting contact, and the at least one conducting contact extends over substantially the entire waveguide; or the at least one conducting contact is configured on both sides of the optical element with respect to a direction of the light waves in the waveguide, and the at least one conducting contact extends over substantially the entire waveguide.

7. The photonic integrated circuit according to claim 1, wherein the at least one conducting contact is connected to an electrical ground.

8. The photonic integrated circuit according to claim 7, wherein the PIC further comprises a grounding hole arranged for allowing a contact between a conducting contact and an n-doped layer wherein distance between an edge of the grounding hole and the waveguide is at least 10 μm, the distance being measured in a direction perpendicular to that of propagation of light in the waveguiding layer.

9. The photonic integrated circuit according to claim 8, wherein at least one dimension of a cross section of the grounding hole in a plane parallel to the direction of propagation of light in the waveguiding layer is at least 20 μm.

10. The photonic integrated circuit according to claim 1, wherein the length of the at least one conducting contact measured in a direction of propagation of light in the waveguiding layer is at least 20 μm.

11. The photonic integrated circuit in accordance with claim 1, wherein the at least one conducting contact comprises at least one of Titanium, Gold or Platinum.

12. The photonic integrated circuit according to claim 1 wherein the optical element is at least one of a Electro-Refractive Modulator, ERM, or Photodetector.

13. The photonic integrated circuit of claim 1 wherein the at least one conducting contact comprises a plurality of conducting contacts, wherein the plurality of conducting contacts are connected to one another by a metallic conducting layer.

14. A method of operating a photonic integrated circuit, PIC, comprising applying a reverse bias voltage to at least one conducting contact, the PIC comprising a plurality of semiconductor layers on a substrate, the plurality of semiconductor layers forming at least one of a PIN or PN doping structure, the PIC comprising: a waveguide arranged for conducting light waves, the waveguide comprising a waveguiding layer, which is one of the layers of the plurality of semiconductor layers; an optical element comprising a waveguiding layer, which is one of the layers of the plurality of semiconductor layers, which waveguiding layers of the waveguide and the optical element are connected to one another, wherein the optical element is operable in reverse-bias mode, and wherein the optical element comprises a contact layer arranged for connecting to a voltage source, wherein the waveguide comprises the at least one conducting contact proximal to the optical element; and at least one isolation section arranged between the contact layer and the at least one conducting contact.

15. The method of operating the photonic integrated circuit according to claim 14 comprising connecting at least one of the at least one conducting contact to an electrical ground.

16. A method of fabricating a photonic integrated circuit, PIC, comprising providing a plurality of semiconductor layers on a substrate, the plurality of semiconductor layers forming at least one of a PIN or PN doping structure, the PIC comprising: a waveguide arranged for conducting light waves, the waveguide comprising a waveguiding layer, which is one of the layers of the plurality of semiconductor layers; an optical element comprising a waveguiding layer, which is one of the layers of the plurality of semiconductor layers, which waveguiding layers of the waveguide and the optical element are connected to one another, wherein the optical element is operable in reverse-bias mode, and wherein the optical element comprises a contact layer arranged for connecting to a voltage source, wherein the waveguide comprises at least one conducting contact proximal to the optical element; and at least one isolation section arranged between the contact layer and the at least one conducting contact.

17. The method of fabricating a photonic integrated circuit according to claim 16, wherein the at least one isolation section is arranged between the optical element and the at least one conducting contact.

18. The method of fabricating a photonic integrated circuit according to claim 16, wherein the at least one conducting contact is configured on both sides of the optical element with respect to a direction of the light waves in the waveguide.

19. The method of fabricating a photonic integrated circuit according to claim 16, wherein the at least one conducting contact extends over substantially the entire waveguide.

20. The method of fabricating a photonic integrated circuit according to claim 16, wherein the optical element is any at least one of a Electro-Refractive Modulator, ERM, or Photodetector.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0032] FIG. 1 illustrates a schematic layout of a tunable laser as commonly employed in a Photonic Integrated Circuit, PIC.

[0033] FIG. 2 illustrates voltage levels measured on the different Electro-Refractive modulators, ERMs, as a function of the voltage applied to the ERM in the long arm of the coarse tuning AMZI.

[0034] FIG. 3a illustrates a cross section of a device according to the present disclosure.

[0035] FIG. 3b illustrates the different layers of a device according to the present disclosure.

[0036] FIG. 3c illustrates a cross section of a device according to the present disclosure.

[0037] FIG. 4 illustrates a cross section of a grounded waveguide section according to the present disclosure.

[0038] FIG. 5 illustrates a three dimensional sketch of a waveguide ridge with two isolation section, a grounding section and an opening to a substrate layer.

DETAILED DESCRIPTION

[0039] FIG. 1 illustrates a schematic layout of a tunable laser as commonly employed in a Photonic Integrated Circuit, PIC. This device 1 has three AMZIs, 10, 20, 30 each with two ERMs 11, 12; 21, 22; 31, 32; that are 2.118 mm long plus a so-called in-line ERM 40 to tune the cavity mode independently. All ERMs have isolation sections at both ends that are 30 μm long. The ERMs are operated using a voltage that put the pin-junction in the device under reverse bias. The layout also comprises a semiconductor optical amplifier, SOA, 41.

[0040] FIG. 2 illustrates, in 50, voltage levels measured on the different Electro-Refractive modulators, ERMs, as a function of the voltage applied to the ERM in the long arm of the coarse tuning AMZI. Presented are the voltages recorded on the ERM in 51 the short arm of the coarse tuning AMZI; in 52, the long arm of the middle AMZI; and in 53, the long arm of the fine tuning AMZI In 54 the measured voltage on the fine tuning AMZI is presented when the cavity ERM and the two ERMs in the medium tuning AMZI are grounded. This clearly points that by effectively grounding the optical elements, the interference in other neighbouring optical elements can be effectively reduced. The latter observation points towards a possible solution and improvement of the ERM building block. This is depicted in FIG. 3.

[0041] FIG. 3a illustrates a cross section of a photonic integrated circuit according to the present disclosure. Next to the ERM 11 there will be an isolation section 72 on both sides, and next to the isolation sections 72 there will be another short ERM section that is to be connected to ground 71. A waveguide 74 comprises a waveguiding layer 65, and is arranged for conducting light waves. The waveguide 74 also comprises conducting contacts 69 that allow either a connection to a voltage source or to an electrical ground according to the present disclosure.

[0042] The length of the isolation section then determines the dark current of the ERM to a large extent. A typical length of an isolation section 72 is currently 50 μm. This length stems from the current design rules of the Smart Photonics process. However this length can be in principle be shortened to approximately 20 μm if the etch depth (down to approx. halfway layer III-1) of the section is similar and if the application allows for the increase dark current on the ERM. The limit of 20 μm stems from the fabrication process of the currently used metallization process (a lift-off process).

[0043] The length of the grounding section will be also be 50 μm determined by the current design rule. It could be shorter. The currents that will flow are estimated to be at most in the order of a microampere. Therefore even a 20 μm long grounding contact (a practical limit in the current technology) is not expected to have a prohibitively large electrically resistance. For the etch depth it is important that the highly doped layer III-2 is fully etched away. Less deep etching in the waveguide for isolation is possible, but current levels from the ERM to the grounding contact will start to rise. It depends on the application of the circuit and electronics if this is tolerable. The metallization used for the ground contacts can be the same as that for the phase modulators. For example, the contacts are made from any of Titanium/Platinum/Gold, Ti/Pt/Au, contact with 300 Nano metre, nm, thickness for the gold deposited by evaporation.

[0044] It should be noted that photonic integrated devices on InP are described here, but in principle other integration schemes that use similar ridge waveguide technology and other semiconductor systems would have similar issues. However we are not aware of other material systems being used commercially to this purpose.

[0045] The additional ground contacts 71 as in FIG. 3 are all contacted using metal routing on the chip surface in the current Smart Photonics integration scheme. This will lead to a large number of metal connections on the chip. The different layers are further elaborated with the help of FIG. 3b.

[0046] FIG. 3b illustrates the different layers of a device according to the present disclosure. FIG. 3b and the corresponding description is to be understood as an example. The features of the present disclosure are not limited to the exact values as presented here. Layer III-3, indicated as 61, is a p-doped contact layer with a high doping concentration of the order of 1.5E19. A typical material employed may be a p-doped InGaAs. Layer 61 is 300 nm thick. Layer III-2, indicated as 62, is also p-doped, but has a lower doping concentration of the order of 1E18 per cubic centimetre, cm.sup.−3. Layer 62 is made of InP and has a thickness of 1000 nm.

[0047] Layer III-1, indicated as 63, is a p-doped layer made of InP, that is about 300 nm thick. This layer has a lower doping concentration of the order of 1E17 cm.sup.−3. Layer II-2, indicated as 64, is an n-doped layer made of InP, that is about 200 nm thick. The doping concentration is of the order of 1E16 cm.sup.−3. Layer II-1, indicated as 65, is an n-Q1.25 waveguide layer. The waveguide layer 65 has a doping concentration of about 1E16 cm.sup.−3 and is 500 nm thick.

[0048] Layers I-2 and I-1, indicated as 66 and 67 respectively, are both n-doped and have a doping concentration of 1E17 cm.sup.−3 and 1E18 cm.sup.−3 respectively. They are both made of InP and have thickness of 500 nm each. Layer 68 is the substrate on which all the subsequent layers have been assembled. It is also referred to as I-0 and is usually an n-doped InP with a doping concentration of 1E18 cm.sup.−3 to 4E18 cm.sup.−3. As mentioned previously, the values are merely exemplary and are not limiting.

[0049] FIG. 3c illustrates a cross section of a device according to the present disclosure. There are a number of issues to be considered. It is possible that the isolation in the perpendicular direction of the waveguides needs to be considered. The trenches next to the passive waveguides are 20 μm wide as shown in FIG. 3c. The etching is deeper than the isolation etch, but the distance is typically three to five times, maybe more, smaller.

[0050] FIG. 4 illustrates, in 100, a cross section of a grounded waveguide section according to the present disclosure. The invention is more general that providing contacts on phase modulators. It also applies to other reverse biased components such as amplifiers used in detectors, as well as in passive components. Another point is that it may be wise to contact all passive components and keep them at a reverse bias voltage of approximately 3 to 4 Volts. There are a number of reasons one might want to do this. Having contacts 102 on all passive devices solves the issue of the electrical isolation using far fewer required contacts (without changing the technology). The design of contacts for passive components may be slightly different than FIG. 4.

[0051] The cross-section of the waveguide would be similar to that in FIG. 4. In case one would want to contact passive devices such as a multi-mode interference coupler, the waveguide section will become significantly wider (e.g. 8 μm instead of 2 μm). Metallization of such wider structures may pose issues in the fabrication. The application of the voltage also reduces the free carrier concentration in the waveguides and thus reduces the propagation loss by up to 0.5 dB per cm. It also clears out the free carriers that are produced in the passive waveguide by the light going through the waveguide which can induce increased absorption. The maximum power handling of a passive waveguide may possibly be increased as well but this needs to be investigated. A third advantage is that the carriers induced by the light create phase noise on the optical signal. This can be an issue in very narrow linewidth CW lasers and definitely plays a role in mode-locked lasers. The free carrier concentration will vary with time due to thermal effects but also the built-in potential of the PIN structure makes that the waveguides forward biases itself (like a solar cell) in a way that is hard to predict. This light generated current can go anywhere in the p-doped layers and flow to waveguide sections with lower intensity. The free carrier effects in the passive waveguides are currently under investigation.

[0052] FIG. 5 illustrates a three dimensional sketch 110 of a waveguide ridge with two isolation section 112, a grounding section 113 and an opening 114 to a substrate layer 111. One possible way to avoid this is to make a local contact to the n-doped layers in the substrate as depicted schematically in FIG. 4. This will require a change in the existing processing scheme. A hole will have to be etched next to the waveguide where the contact to the waveguide to the highly doped layer I-0.

[0053] A metallization scheme such as the currently used Ti—Pt—Au layer system (typical 60-75-500 nm thickness respectively) and contact annealing can be used since it will provide a good Ohmic contact on both n doped InP and p doped InGaAs. The size 116 of the opening 114 towards the layer I-0 can be equally long as the grounding contact and it is estimated it will need to be minimally 20 μm wide. In FIG. 5 a drawing to scale is presented of a 2 μm wide ridge waveguide, with two 20 μm isolation sections, a 20 μm long grounding section in the middle and the opening for access to layer I-0, before planarization and metallization are applied to show the structure. The opening 114 is 10 μm away, 115, from the waveguide in order not to affect the light propagation in the waveguide.

[0054] Since current levels are expected to be limited to 1 μA or less, the resistance value of the contact may be relatively high (e.g. several hundred Ω). It might be that the etched hole may be of the same depth as that of the deeply etched ridge waveguides in which case the metal would be contacted a lower doped InP layer. This needs more investigation and trials.

[0055] The grounding of the p-side of the waveguide will be more easily achieved in the semi-insulating substrate technology. In this technology scheme where a top n-contact level is already available that can be used to connect the top p-contacts of the grounded waveguide section.

[0056] These combinations of two isolation sections and one grounding section can also be used together with other reverse biased components. A specific example is a photodetector where it will prevent leakage current and therefore a dark current level, to other detectors or biased components as well as dark currents due to photo-generated currents in other passive waveguide components connected to the photodetector.

[0057] The electrical isolation of the phase modulator building block in the Smart Photonics platform needs to be addressed. A possible solution is to add grounding contacts adjacent to the phase modulator separated by isolation sections. The grounding contacts can in principle be realized by making a contact locally to the n-side of the chip. There are arguments to have all passive components contacted and kept at ground voltage connected to the n-side, or at a reverse bias voltage of a few volts to reduce propagation losses and possibly stabilize the optical path length to a higher degree than the current situation.

[0058] Generally, the invention includes the use of ground contacts and isolation sections to prevent cross-talk between any elements in Smart Photonics platform, both active and passive. The application to electro-optic phase modulators is just one example of an active component.