ANALOG-TO-DIGITAL CONVERTER CAPABLE OF CANCELLING SAMPLING NOISE

Abstract

The present application discloses an analog-to-digital converter capable of cancelling sampling noise, which comprises: a sampling circuit configured to acquire an analog input signal; a sampling noise cancelling circuit has an input end connected with an output end of the sampling circuit, and is configured to cancel noise generated by the sampling circuit; a comparator has an input end connected with an output end of the sampling noise cancelling circuit, and an output end connected with an input end of a logic circuit, and is configured to compare magnitudes of output signals of the sampling noise cancelling circuit and output a comparison result to the logic circuit; and the logic circuit has an output end connected with the sampling circuit, and is configured to output a digital output signal, and process the comparison result to obtain a control signal by which an output voltage of the sampling circuit is controlled.

Claims

1. An analog-to-digital converter capable of cancelling sampling noise, comprising: a sampling circuit, a sampling noise cancelling circuit, a comparator and a logic circuit, wherein the sampling circuit is configured to acquire an analog input signal; the sampling noise cancelling circuit has an input end connected with an output end of the sampling circuit, and is configured to cancel noise generated by the sampling circuit; the comparator has an input end connected with an output end of the sampling noise cancelling circuit, and an output end connected with an input end of the logic circuit, and the comparator is configured to compare magnitudes of output signals of the sampling noise cancelling circuit and output a comparison result to the logic circuit; and the logic circuit has an output end connected with the sampling circuit, and is configured to output a digital output signal, and configured to process the comparison result to obtain a control signal by which an output voltage of the sampling circuit is controlled.

2. The analog-to-digital converter capable of cancelling the sampling noise according to claim 1, wherein the sampling circuit includes a first sampling capacitor array, a first switch and a second switch; the sampling noise cancelling circuit includes an amplifier, a second capacitor and a third switch; the first sampling capacitor array has a lower plate connected respectively with one end of the second switch and one of a reference voltage or the logic circuit, and an upper plate connected separately with one end of the first switch and an input end of the amplifier, the other end of the first switch is grounded or connected with a DC voltage, and the other end of the second switch is connected with the analog input signal; the input end of the amplifier is connected with the one end of the first switch, and an output end of the amplifier is connected with a lower plate of the second capacitor; and an upper plate of the second capacitor is connected separately with one end of the third switch and the input end of the comparator, and the other end of the third switch is grounded or connected with a DC voltage.

3. The analog-to-digital converter capable of cancelling the sampling noise according to claim 2, wherein a falling edge of the third switch is later than that of the first switch and earlier than that of the second switch.

4. The analog-to-digital converter capable of cancelling the sampling noise according to claim 2, wherein the first switch and the third switch are grounded; and in a time period of t.sub.0-t.sub.1, the first switch, the second switch and the third switch are on, the analog input signal is followed and stored on the first sampling capacitor array, the input end of the amplifier and the upper plate of the second capacitor are grounded, and a voltage across the second capacitor is cleared; at the time t.sub.1, the first switch is off, and the input signal at the time t.sub.1 V.sub.in(t.sub.1) and the sampling noise v.sub.ns1 are stored together on the first sampling capacitor array; and the upper plate of the first sampling capacitor array is open, and a voltage across the first sampling capacitor array is kept constantly at V.sub.in(t.sub.1)+v.sub.ns1; in a time period of t.sub.1-t.sub.2, the first switch is in an off state, the third switch is in an on state, the input signal V.sub.in in the time period of t.sub.1-t.sub.2 is still connected with the lower plate of the first sampling capacitor array, the voltage across the first sampling capacitor is kept unchanged, and a voltage on the input end of the amplifier is a difference between V.sub.in and the voltage across the first sampling capacitor array, i.e., V.sub.in−V.sub.in(t.sub.1)−v.sub.ns1, and is amplified by A times and then stored on the capacitor C2, wherein A is a gain of the amplifier; at the time t.sub.2, the third switch is off, a noise V.sub.ns2 of the third switch is fixed on the second capacitor, the input signal at the time t.sub.2 is V.sub.in(t.sub.2), and a total voltage acquired by the second capacitor is A.Math.[V.sub.in(t.sub.2)−V.sub.in(t.sub.1)−v.sub.ns1]+v.sub.ns2; after the time t.sub.2, a conversion process of the analog-to-digital converter begins, the comparator performs comparisons for multiple times, and the logic circuit feeds a result of each comparison back to the lower plate of the first sampling capacitor array, so that a voltage on the input end of the comparator is pulled down towards 0; and at a time when the conversion is ended, an equivalent signal at the lower plate of the first sampling capacitor array is the digital output signal D.sub.out; and since the voltage on the input end of the comparator is 0 at the end of conversion, the digital output signal D.sub.out can be obtained as
D.sub.out=V.sub.in(t.sub.2)+v.sub.ns2/A.

5. The analog-to-digital converter capable of cancelling the sampling noise according to claim 1, wherein the analog-to-digital converter includes but is not limited to a successive approximation register analog-to-digital converter.

6. The analog-to-digital converter capable of cancelling the sampling noise according to claim 2, wherein the analog-to-digital converter includes but is not limited to a successive approximation register analog-to-digital converter.

7. The analog-to-digital converter capable of cancelling the sampling noise according to claim 3, wherein the analog-to-digital converter includes but is not limited to a successive approximation register analog-to-digital converter.

8. The analog-to-digital converter capable of cancelling the sampling noise according to claim 4, wherein the analog-to-digital converter includes but is not limited to a successive approximation register analog-to-digital converter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above and/or additional aspects and advantages of the present application become apparent and easily understood from the following description of the embodiments in combination with the accompanying drawings.

[0039] FIG. 1 is a structural schematic diagram of an SAR ADC and a driving circuit in a stage preceding to the SAR ADC.

[0040] FIG. 2 is a structural schematic diagram of the existing SAR ADC.

[0041] FIG. 3 is a structural schematic diagram of an analog-to-digital converter capable of cancelling sampling noise according to an embodiment of the present application.

[0042] FIG. 4 is structural schematic diagram of the analog-to-digital converter capable of cancelling sampling noise in different phases according to an embodiment of the present application.

DETAILED DESCRIPTION

[0043] Embodiments of the present application are described below in detail. Examples of the embodiments are shown in the accompanying drawings, wherein same or similar reference numerals indicate the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present application, but should not be construed as limiting the present application.

[0044] An analog-to-digital converter capable of cancelling sampling noise provided according to an embodiment of the present application is described below with reference to the accompanying drawings.

[0045] Taking a successive approximation register (SAR) analog-to-digital converter as an example, the analog-to-digital converter capable of cancelling the sampling noise of the present application is introduced.

[0046] FIG. 3 is a structural schematic diagram of an analog-to-digital converter capable of cancelling sampling noise according to an embodiment of the present application.

[0047] As shown in FIG. 3, the analog-to-digital converter capable of cancelling the sampling noise includes a sampling circuit, a sampling noise cancelling circuit, a comparator and a logic circuit.

[0048] The sampling circuit is configured to acquire an analog input signal.

[0049] An input end of the sampling noise cancelling circuit is connected with an output end of the sampling circuit. The sampling noise cancelling circuit is configured to cancel noise generated by the sampling circuit.

[0050] The comparator has an input end connected with an output end of the sampling noise cancelling circuit, and an output end connected with an input end of the logic circuit; and the comparator is configured to compare magnitudes of output signals of the sampling noise cancelling circuit and output a comparison result to the logic circuit.

[0051] An output end of the logic circuit is connected with the sampling circuit, and the logic circuit is configured to output the digital output signal, and process the comparison result to obtain a control signal, and an output voltage of the sampling circuit controlled according to the control signal.

[0052] Further, the sampling circuit includes a first sampling capacitor array, a first switch and a second switch;

[0053] The sampling noise cancelling circuit includes an amplifier, a second capacitor and a third switch;

[0054] The first sampling capacitor array has a lower plate connected separately with one end of the second switch and a reference voltage or the logic circuit, and an upper plate connected separately with one end of the first switch and an input end of the amplifier, the other end of the first switch is grounded or connected with a DC voltage, and the other end of the second switch is connected with the analog input signal.

[0055] The input end of the amplifier is connected with the one end of the first switch, and an output end of the amplifier is connected with a lower plate of the second capacitor.

[0056] An upper plate of the second capacitor is connected separately with one end of the third switch and the input end of the comparator, and the other end of the third switch is grounded or connected with a DC voltage.

[0057] It may be understood that the present embodiment of the present application adds a sampling noise cancelling circuit between the sampling circuit and the comparator. The sampling noise cancelling circuit includes one amplifier, one capacitor C.sub.2 and one switch Φ.sub.3.

[0058] Further, a falling edge of the third switch Φ.sub.3 is later than that of the first switch Φ.sub.1 and earlier than that of the second switch Φ.sub.2.

[0059] In the present solution, the falling edge of the switch Φ.sub.3 is later than that of Φ.sub.1 and earlier than that of Φ.sub.2. The sampling noise generated by the sampling switch Φ.sub.1 is stored in the sampling capacitor array C.sub.1 on one hand, and may also be stored in C.sub.2 after being amplified by the amplifier on the other hand. The sampling noises in C.sub.1 and C.sub.2 have opposite polarities and may cancel each other. Although the added switch Φ.sub.3 may introduce additional sampling noise, the noise may be attenuated greatly by the gain of the amplifier. Therefore, compared with the prior art, by using the present solution, the total amount of the sampling noise in the ADC system may be reduced greatly.

[0060] As shown in FIG. 4, a working principle of the SAR ADC of the present solution is described below. To simplify the expression, the logic circuit and the switch 12 are omitted in the drawing, and the first switch and the third switch are grounded.

[0061] In a time period of t.sub.0-t.sub.1, Φ1, Φ2 and Φ3 all are on, and the analog input signal is followed and stored on the capacitor array C.sub.1; and meanwhile, the input end of the amplifier and the upper plate of the capacitor C.sub.2 are grounded, so the voltage on two ends of the capacitor C.sub.2 is cleared.

[0062] At the time t.sub.1, Φ.sub.1 is off, and the input signal V.sub.in(t.sub.1) at this time and the sampling noise v.sub.ns1 of the switch are stored together on the capacitor array C.sub.1. Thereafter, since the upper plate side of the C.sub.1 is open, there is no charging-discharging path, because the voltage on two ends of the C.sub.1 is always kept at V.sub.in(t.sub.1)+v.sub.ns1.

[0063] In the time period of t.sub.1-t.sub.2, Φ.sub.1 is in an off state, and Φ.sub.3 is still in an on state. The input signal yin at this time is still connected with the lower plate of C.sub.1, and the voltage on two ends of C.sub.1 is kept unchanged, so the voltage on the input end of the amplifier is a difference between V.sub.in and the voltage on two ends of C.sub.1, i.e., V.sub.in−V.sub.in(t.sub.1)−v.sub.ns1, and this voltage is amplified by A times and then stored on the capacitor C.sub.2, where A is a gain of the amplifier.

[0064] At the time t.sub.2, t.sub.3 is off, and the noise v.sub.ns2 of the switch Φ.sub.3 is fixed on the capacitor C.sub.2. At this time, the input signal is V.sub.in(t.sub.2), so a total voltage acquired by the capacitor C.sub.2 is A.Math.[V.sub.in(t.sub.2)−V.sub.in(t.sub.1)−V.sub.ns1]+V.sub.ns2.

[0065] After the time t.sub.2, a conversion process of the ADC begins, the comparator performs comparisons for multiple times, and the logic circuit feeds a result of each comparison back to the lower plate of the sampling capacitor array, so that the voltage on the input end of the comparator is approximate to 0. At the time when the conversion is ended, an equivalent signal of the lower plate of the capacitor array C.sub.1 is the digital output signal D.sub.out. Since the voltage on the input end of the comparator is 0 at the end of conversion, the digital output signal D.sub.out can be obtained as:

D.sub.out=V.sub.in(t.sub.2)+v.sub.ns2/A  (3)

[0066] In the above formula, a variance v.sub.ns1.sup.2 of the noise v.sub.ns2 introduced by the switch Φ.sub.3 is kT/C.sub.2.

[0067] Comparing the formula (1) and formula (3), it may be seen that through the present solution, the sampling noise v.sub.ns1 is cancelled, and the noise v.sub.ns2 introduced by the switch Φ.sub.3 is attenuated by the gain of the amplifier, which is reduced by A times. Therefore, the SAR ADC proposed by the present solution may adopt a small sampling capacitor C.sub.1 to lower the requirement on the driving capacity of the driving circuit, thereby reducing greatly the power consumption, area and design complexity.

[0068] In conclusion, the sampling noise cancelling circuit is used in the successive approximation register analog-to-digital converter, which may cancel the noise generated by the sampling circuit. The sampling noise cancelling circuit of the present embodiment is not limited to the application in the successive approximation register analog-to-digital converter, and may still be suitable for other analog-to-digital converters.

[0069] The above description is a single-terminal circuit structure of the ADC. It should be noted that the embodiment of the present application is also suitable for the ADC of a differential circuit structure.

[0070] Further, during the period when the first switch and the third switch are on, the upper plate of the capacitor is grounded. In practical circuit design, the upper plate of the capacitor may be connected to any DC voltage according to the requirement.

[0071] The analog-to-digital converter capable of cancelling the sampling noise according to the present embodiment adds a sampling noise cancelling circuit between the sampling circuit and the comparator, which may cancel the noise generated by the sampling circuit, so that a small sampling capacitor may be used in the ADC without causing signal-to-noise ratio loss, and the reduction of the sampling capacitor lowers the requirement on the driving capacity of the driving circuit, thereby reducing the power consumption, area and design complexity of the driving circuit.

[0072] In the description of the present application, it should be understood that an orientation or positional relationship indicated by terms “center”, “longitudinal”, “transverse”, “length”, “width”, “thickness”, “upper”, “lower”, “front”, “rear”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inner”, “outer”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc. is based on the orientation or positional relationship shown in the drawings, and is only for convenience in describing the present application and simplifying the description, rather than indicating or implying specified devices or elements must have a specific orientation or must be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application.

[0073] In addition, terms “first” and “second” are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined with “first” and “second” may explicitly or implicitly include at least one of the features. In the description of the present application, “a plurality of” means at least two, for example, two or three, etc.

[0074] In the present application, unless otherwise defined and limited clearly, the terms “mount”, “connected”, “connection” and “fixed” should be understood in a broad sense, for example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; and it may be a direct connection or an indirect connection through an intermediate medium, and may also be an internal communication of two elements or an interaction relationship of two elements, unless otherwise specified. For those ordinarily skilled in the art, the specific meaning of the above terms in the present application may be understood in specific circumstances.

[0075] In the present application, unless otherwise specified or defined clearly, the first feature is “on” or “under” the second feature, which may refer to that the first feature and the second feature are in direct contact, or the first feature and the second feature are in indirect contact through an intermediate medium. Moreover, the first feature is “on” and “above” the second feature, which may refer to that the first feature is directly above or obliquely above the second feature, or only refers to that a level of the first feature is higher than the second feature. Moreover, the first feature is “below” and “under” the second feature, which may refer to that the first feature is directly below or obliquely below the second feature, or only refers to that the level of the first feature is lower than the second feature.

[0076] In the description of the present application, descriptions with reference to terms “one embodiment”, “some embodiments”, “examples”, “specific examples”, or “some examples” etc. mean specific features, structures, materials, or characteristics described in conjunction with the embodiment(s) or example(s) are contained in at least one embodiment or example of the present application. In the present specification, the schematic representations of the above terms are not necessary for the same embodiment(s) or example(s). Moreover, the described specific features, structures, materials or characteristics may be combined in an appropriate way in any or more embodiments or examples. Furthermore, different embodiments or examples and features of different embodiments or examples described in the present specification may be combined by those skilled in the art without contradicting each other.

[0077] Although the embodiments of the present application have been shown and described above, it may be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Changes, modifications, replacements or variations may be made by those skilled in the art for the above embodiments within the scope of the present application.