RESISTIVE SUB-MODULE HYBRID MMC AND DIRECT CURRENT FAULT PROCESSING STRATEGY THEREOF

Abstract

The present disclosure discloses a resistive sub-module hybrid MMC and a direct current fault processing strategy thereof. The hybrid MMC prevents fault current from entering a direct current system from the alternating current side by artificially creating three-phase earthing short circuit on the alternating current side of a converter during the direct current fault processing process, and can reduce the number of required power electronic devices compared with the module hybrid MMC. At the same time, the direct current fault processing speed of the hybrid MMC is fast, and the duration of the artificially creating three-phase short circuit fault in the fault processing process is less than 60 ms, which will not have a great impact on the alternating current system. The present disclosure greatly reduces the cost of building an overhead line high-voltage flexible direct current transmission system, and has very strong reference significance and use value in engineering.

Claims

1. A resistive sub-module hybrid MMC comprising: a three-phase six-bridge arm structure, wherein each phase comprises an upper bridge arm and a lower bridge arm, wherein the upper bridge arm comprising N.sub.1 half-bridge arm sub-modules, N.sub.2 resistive sub-modules and a bridge arm reactor in series from a high voltage terminal to a low voltage terminal; the lower bridge arm comprising a bridge arm reactor, N.sub.2 resistive sub-modules and N.sub.1 half-bridge sub-modules in series from the high voltage terminal to the low voltage terminal, where N.sub.1 and N.sub.2 are natural numbers greater than 1; a middle node of the upper bridge arm and the lower bridge arm of phase A is connected with a a first end of alternating current breaker BR.sub.1, and a second end of the alternating current breaker BR.sub.1 is grounded; a middle node of the upper bridge arm and the lower bridge arm of phase B is connected with a first end of an alternating current breaker BR.sub.2, and a second end of the alternating current breaker BR.sub.2 is grounded; a middle node of the upper bridge arm and the lower bridge arm of phase C is connected with a first end of an alternating current breaker BR.sub.3, and a second end of the alternating current breaker BR.sub.3 is grounded.

2. The resistive sub-module hybrid MMC according to claim 1, wherein the N.sub.2 of resistive sub-modules in each bridge arm is less than or equal to 30% of N.sub.1.

3. The resistive sub-module hybrid MMC according to claim 1, wherein the high voltage terminal of a direct current side of the MMC is connected with a direct current line through a smoothing reactor and a mechanical switch in sequence.

4. The resistive sub-module hybrid MMC according to claim 1, further comprising two IGBT T.sub.1-T.sub.2 with anti-parallel diodes and a resistor R.sub.0, wherein an emitter of the IGBT T.sub.1 is connected with the collector of the IGBT T.sub.2 and serves as the high voltage terminal of the sub-module, a collector of IGBT T.sub.1 is connected with a first end of resistor R.sub.0, and a second end of the resistor R.sub.0 is connected with the emitter of the IGBT T.sub.2 and serves as the low voltage terminal of the sub-module.

5. A direct current fault processing strategy applied to the resistive sub-module hybrid MMC, the resistive sub-module hybrid MMC comprising: a three-phase six-bridge arm structure, wherein each phase comprises an upper bridge arm and a lower bridge arm, wherein the upper bridge arm comprising N.sub.1 half-bridge arm sub-modules, N.sub.2 resistive sub-modules and a bridge arm reactor in series from a high voltage terminal to a low voltage terminal; the lower bridge arm comprising a bridge arm reactor, N.sub.2 resistive sub-modules and N.sub.1 half-bridge sub-modules in series from the high voltage terminal to the low voltage terminal, where N.sub.1 and N.sub.2 are natural numbers greater than 1; a middle node of the upper bridge arm and the lower bridge arm of phase A is connected with a a first end of alternating current breaker BR.sub.1, and a second end of the alternating current breaker BR.sub.1 is grounded; a middle node of the upper bridge arm and the lower bridge arm of phase B is connected with a first end of an alternating current breaker BR.sub.2, and a second end of the alternating current breaker BR.sub.2 is grounded; a middle node of the upper bridge arm and the lower bridge arm of phase C is connected with a first end of an alternating current breaker BR.sub.3, and a second end of the alternating current breaker BR.sub.3 is grounded; wherein the high voltage terminal of a direct current side of the MMC is connected with a direct current line through a smoothing reactor and a mechanical switch in sequence; wherein the direct current fault processing strategy comprises the following steps: (1) during normal operation, keeping the alternating current circuit breakers BR.sub.1, BR.sub.2 and BR.sub.3 of the MMC in open state, keeping the mechanical switches in closed state, keeping all resistive sub-modules in bypass state, and monitoring the bridge arm current of each bridge arm of the MMC at the same time; (2) after the direct current fault occurs, if the converter station where the MMC is located first detects that the bridge arm current exceeds the threshold, immediately locking all half-bridge sub-modules in the MMC and conducting all resistive sub-modules, closing alternating current circuit breakers BR.sub.1, BR.sub.2 and BR.sub.3 at the same time, and then sending a direct current fault processing instruction to the converter station at the other end connected with the MMC; (3) when the converter station at the other end receives the direct current fault processing instruction or detects that the current of its own MMC bridge arm exceeds the threshold, similarly, immediately locking all half-bridge sub-modules in the MMC and conducting all resistive sub-modules, and closing the alternating current circuit breakers BR.sub.1, BR.sub.2 and BR.sub.3; (4) after a certain period of time t.sub.3, when the current flowing through the mechanical switches at both ends of the fault line is reduced to a certain size, the converter stations at both ends issuing an opening signal to their respective mechanical switches, the mechanical switches complete turning on to realize the physical isolation of the fault line, and at the same time, the converter stations at both ends issuing an opening signal to the alternating current circuit breakers BR.sub.1, BR.sub.2 and BR.sub.3 of their respective MMC; (5) after a certain time t.sub.4, the alternating current circuit breakers BR.sub.1, BR.sub.2 and BR.sub.3 of the MMC at both ends returning to the open state, and completing the direct current fault processing.

6. The direct current fault processing strategy according to claim 5, wherein in step (2) and step (3), it is determined that the MMC bridge arm current exceeds the threshold when the following relation holds;
max(I.sub.pa,I.sub.na,I.sub.pb,I.sub.nbI.sub.pc,I.sub.nc)>2I.sub.rate where I.sub.pa is the upper arm current of phase A of the MMC, I.sub.na is the lower arm current of phase A of the MMC, I.sub.pb is the upper arm current of phase B of the MMC, I.sub.nb is the lower arm current of phase B of the MMC, I.sub.pc is the upper arm current of phase C of the MMC, I.sub.nc is the lower arm current of phase C of the MMC, I.sub.rate is rated current of IGBT in the sub-module.

7. The direct current fault processing strategy according to claim 5, wherein in step (5), reclosing operation is required after direct current fault processing is completed, and the specific implementation method is as follows: for a temporary direct current fault, after a certain de-ionization time, issuing a closing signal to the mechanical switches at both ends of the fault line, and at the same time, issuing an instruction to unlock the half-bridge sub-module and bypass the resistive sub-module to the MMC at both ends, so that the system can recover to the steady-state operation state; for a permanent direct current fault, after a certain de-ionization time, issuing a closing signal to the mechanical switches at both ends of the fault line, and at the same time, issuing an instruction to unlock the half-bridge sub-module and bypass the resistive sub-module to the MMC at both ends; as it is a permanent direct current fault, if it is detected again that the bridge arm current of the MMC of a converter station at one end exceeds the threshold after a certain time, performing the direct current fault processing again according to steps (2)-(5).

8. The direct current fault processing strategy according to claim 5, wherein: when the half-bridge sub-module in the MMC is locked and the resistive sub-module is put into operation, the resistor in the resistive sub-module forms an LC oscillation attenuation loop together with the smoothing reactor, the bridge arm reactor and the direct current line, so that the direct current fault current quickly drops to the current range that the mechanical switch is capable of being turned off within t.sub.3 after the half-bridge sub-module is locked and the resistive sub-module is put into operation, and finally the mechanical switch is turned on.

9. The direct current fault processing strategy according to claim 5, wherein during the t.sub.3+t.sub.4 period of fault processing, three-phase inter-phase short circuit is actively created on the MMC valve side by closing the alternating current circuit breakers BR.sub.1, BR.sub.2 and BR.sub.3, which prevents the current of the alternating current system from flowing into the direct current system and accelerates the process of fault current oscillation attenuation, and the total duration of t.sub.3+t.sub.4 does not exceed 60 ms.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to explain the embodiments of the present disclosure or the technical scheme in the prior art more clearly, the drawings needed in the embodiments will be briefly introduced hereinafter. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained according to these drawings without paying creative labor.

[0031] FIG. 1 is a schematic diagram of the topological structure of a resistive sub-module hybrid MMC according to the present disclosure;

[0032] FIG. 2 is a schematic structural diagram of a test system used in a specific embodiment of the present disclosure;

[0033] FIG. 3 is a schematic diagram of the current waveform flowing through the quick mechanical switch in the fault processing process according to the present disclosure;

[0034] FIG. 4 is a schematic diagram of the direct current voltage waveform of the MMC1 in the fault processing process according to the present disclosure;

[0035] FIG. 5 is a schematic diagram of the direct current waveform of the MMC1 during fault processing according to the present disclosure;

[0036] FIG. 6 is a schematic diagram of the active power waveform of the MMC1 during fault processing according to the present disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] The technical scheme in the embodiments of the present disclosure will be described clearly and completely hereinafter with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without paying creative labor belong to the scope of protection of the present disclosure.

[0038] The purpose of the present disclosure is to provide a resistive sub-module hybrid MMC and a direct current fault processing strategy thereof. The ratio of resistive sub-modules required by the hybrid MMC is only 30% of all half-bridge sub-modules, and direct current faults can be isolated within 50 ms, which greatly reduces the cost of building an overhead line high-voltage flexible direct current transmission system, and has very strong reference significance and use value in engineering.

[0039] In order to make the above objects, features and advantages of the present disclosure more obvious and understandable, the present disclosure will be further explained in detail hereinafter with reference to the drawings and specific embodiments.

[0040] FIG. 1 is a schematic diagram of the topological structure of a resistive sub-module hybrid MMC according to the present disclosure. As shown in FIG. 1, the resistive sub-module hybrid MMC of the present disclosure is a three-phase six-bridge arm structure. Each phase comprises an upper bridge arm and a lower bridge arm. Each bridge arm comprising N sub-modules SM.sub.n and a bridge arm reactor connected in series, n□[1, N]. The N sub-modules SM.sub.n comprise N.sub.1 half-bridge sub-modules HBSM.sub.n1 and N.sub.2 resistive sub-modules RSM.sub.n2, i.e., N=N.sub.1+N.sub.2, where N, N.sub.1 and N.sub.2 are natural numbers greater than 1, n1□[1, N.sub.1], n2□[1, N.sub.2]. The outlet of the direct current side of the converter is connected with the direct current line through a smoothing reactor L.sub.dc and a quick mechanical switch K. N.sub.1 half-bridge sub-modules connected in series, N.sub.2 resistive sub-modules connected in series and a bridge arm reactor are respectively arranged in all upper bridge arms of the MMC according to the sequence from the high voltage terminal to the low voltage terminal. A bridge arm reactor, N.sub.2 resistive sub-modules connected in series and N.sub.1 half-bridge sub-modules connected in series are respectively arranged in all lower bridge arms of the MMC according to the sequence the high voltage terminal to the low voltage terminal. The connection points of the upper bridge arm and the lower bridge arm of phase A are grounded through an alternating current breaker BR.sub.1. The connection points of the upper bridge arm and the lower bridge arm of phase B are connected through an alternating current breaker BR.sub.2. The connection points of the upper bridge arm and the lower bridge arm of phase C are grounded through an alternating current breaker BR.sub.3. The number N.sub.2 of resistive sub-modules in each bridge arm is less than or equal to 30% of N.sub.1. The structure of the resistive sub-module is similar to that of the conventional half-bridge sub-module, that is, the high voltage terminal and the low voltage terminal of the sub-module have two parallel branches, one of which comprising IGBT T1 and an anti-parallel diode D1, and the other comprising IGBT T2, an anti-parallel diode D2 and a sub-module resistance in series.

[0041] For the above hybrid MMC, the direct current fault processing strategy comprises the following steps:

[0042] (1) during normal operation, keeping BR.sub.1, BR.sub.2 and BR.sub.3 in open state, keeping K in closed state; at the same time, the bridge arm currents of each bridge arm are monitored, which are the upper arm current I.sub.pa of phase A, the lower arm current I.sub.na of phase A, the upper arm current I.sub.pb of phase B, the lower arm current I.sub.nb of phase B, the upper arm current I.sub.pc of phase C, and the lower arm current I.sub.nc of phase C;

[0043] (2) After the direct current fault occurs, after t.sub.1 time, a converter station first detects that the current of each bridge arm satisfies the following relational expression, immediately locks all half-bridge sub-modules in the MMC and conducting all resistive sub-modules, closes alternating current switches BR.sub.1, BR.sub.2 and BR.sub.3, and sends a locking command to other converter stations at the same time;

max(I.sub.pa,I.sub.na,I.sub.pb,I.sub.nb,I.sub.pc,I.sub.nc)>2I.sub.rate

[0044] where I.sub.rate is rated direct current of IGBT in the sub-module;

[0045] (3) After other converter stations receives the locking signal or detects that the current of its own bridge arm exceeds the threshold, similarly, the converter stations immediately lock all half-bridge sub-modules in the MMC and conduct all resistive sub-modules, and close the alternating current switch BR.sub.1, the alternating current switch BR.sub.2 and the alternating current switch BR.sub.3 at the same time, in which it takes time t.sub.2 from the time when the first converter station is closed to the time when all converter stations in direct current network complete closing.

[0046] (4) After time t.sub.3 passes after all converter stations are locked, after the current flowing through the quick mechanical switches K at both ends of the fault line is reduced to 0.2 kA, the corresponding converter station issues an opening signal to the quick mechanical switches; the quick mechanical switch completes turning on to realize the physical isolation of the fault line, and at the same time, issues an opening signal to BR.sub.1, BR.sub.2 and BR.sub.3.

[0047] After the half-bridge sub-module in the MMC is locked and the resistive sub-module is connected, the equivalent resistor of the resistive sub-module, the smoothing reactor, the bridge arm reactor and the direct current line together form a RL attenuation loop, so that the direct current fault current quickly drops to the current range that the quick mechanical switch is capable of being turned off within t.sub.3 after the half-bridge sub-module is locked and the resistive sub-module is connected, and finally the quick mechanical switch K is turned on for fault.

[0048] (5) After t.sub.4 time (the longest period is half a cycle, that is, 10 ms), BR.sub.1, BR.sub.2 and BR.sub.3 return to the open state, and the direct current fault processing is completed. During the fault processing period t.sub.3+t.sub.4, three-phase inter-phase short circuit is actively created on the converter station valve side by closing BR.sub.1, BR.sub.2 and BR.sub.3, which prevents the current of the alternating current system from flowing into the direct current system and accelerates the process of fault current oscillating to 0, wherein the total duration of t.sub.3+t.sub.4 does not exceed 60 ms.

[0049] When the fault processing is completed, reclosing operation is required after direct current fault processing is completed, and the specific implementation mode is as follows:

[0050] for a temporary direct current fault, after de-ionization time t.sub.5, issuing a closing signal to the quick mechanical switches K, and issuing an instruction to unlock the half-bridge sub-module and bypass the resistive sub-module to the MMC at both ends, so that the system can recover to the steady-state operation state;

[0051] for a permanent direct current fault, after de-ionization time t.sub.5, issuing a closing signal to the quick mechanical switches K, and issuing an instruction to unlock the half-bridge sub-module and bypass the resistive sub-module to the MMC at both ends; as it is a permanent fault, if it is detected again that the bridge arm current value of a converter station exceeds the threshold after time t.sub.6, processing the fault again according to the above steps.

[0052] In the specific embodiment of the direct current fault processing process of the two-terminal direct current transmission test system shown in FIG. 2, the converter stations on both sides adopt the resistive sub-module hybrid MMC proposed by the present disclosure, and the specific parameters are shown in table 1:

TABLE-US-00001 TABLE 1 parameter value direct current voltage 400 kV rated power 400 MW effective value of alternating current 230 kV side voltage equivalent reactance of an alternating 10 mH current system Transformation ratio of a converter 230 kV/200 kV transformer rated capacity of a converter 480 MW transformer number of half-bridge sub-modules 200 per bridge arm number of resistive sub-modules per 60 bridge arm Sub-module capacitance C.sub.0 6667 μF Sub-module resistance R.sub.0 0.6667 Ω rated capacitance voltage of a 2 kV sub-module bridge arm reactance 76 mH line length 100 km rated current of IGBT 1.5 kA

[0053] Simulation scenario: in steady-state operation, the converter station MMC1 at the first side controls direct current voltage, the converter station MMC2 at the second side controls transmission power, and MMC1 transmits 400 MW active power to the MMC2. At 1.5 s, a temporary ground short circuit fault occurs at the midpoint of the direct current line, and the fault lasts for 0.1 s.

[0054] (1) After t.sub.1=3 ms, the MMC1 detects that the bridge arm current exceeds the threshold 3 kA, immediately locks all half-bridge sub-modules and conducts all resistive sub-modules, closes alternating current switches BR.sub.1, BR.sub.2 and BR.sub.3, and issues an opening signal to mechanical switches K on both sides of the line, and at the same time sends a locking command to the MMC2.

[0055] (2) After t.sub.2=1 ms, the MMC2 detects that the bridge arm current exceeds the threshold 3 kA, immediately locks all half-bridge sub-modules and conducts all resistive sub-modules, and closes alternating current switches BR.sub.1, BR.sub.2 and BR.sub.3.

[0056] (3) After t.sub.3=40 ms, the fault currents flowing through the mechanical switches K on both sides of the line are all reduced to 0.2 kA, the switches on both sides completes turning on, the fault line is isolated, and the signals of turning on BR.sub.1, BR.sub.2 and BR.sub.3 are sent to converter stations on both sides.

[0057] (4) After t.sub.4=10 ms, BR.sub.1, BR.sub.2 and BR.sub.3 of converter stations on both sides return to the open state, and the direct current fault processing is completed.

[0058] The above process takes a total of 54 ms, and the fault line is successfully isolated at 1.544 s, in which the converter stations BR.sub.1, BR.sub.2 and BR.sub.3 on both sides are closed for 51 ms, which has less impact on the alternating current system. The current waveform flowing through the mechanical switches K on both sides of the line in the process is shown in FIG. 3.

[0059] After the fault processing is completed, wait for t.sub.5=300 ms for the de-ionization time, a closing signal is issued to the quick mechanical switch K, an instruction to unlock the half-bridge sub-module and bypass the resistive sub-module is issued to the MMC on both sides, and finally the system returns to the steady-state operation state. In the process from fault to recovery to steady-state operation, the direct current voltage waveform of the MMC1 is shown in FIG. 4, the direct current waveform is shown in FIG. 5, and the active power waveform transmitted to the MMC2 is shown in FIG. 6.

[0060] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. It is sufficient to refer to the same and similar parts among each embodiment.

[0061] In the present disclosure, a specific example is applied to illustrate the principle and implementation of the present disclosure, and the explanation of the above embodiments is only used to help understand the method and its core idea of the present disclosure. At the same time, according to the idea of the present disclosure, there will be some changes in the specific implementation and application scope for those skilled in the art. To sum up, the contents of this specification should not be construed as limiting the present disclosure.