INTERNAL POWER SUPPLY FOR AMPLIFIERS

Abstract

An internal power supply for an amplifier is disclosed. The internal power supply floats according to a common mode voltage at the input to the amplifier and according to an input voltage at an input stage of the amplifier. Powering the input stage of the amplifier using the floating supply allows for the use of low voltage devices even when the range of possible common mode voltages includes high voltages. The use of low voltage devices can correspond to performance improvement for the amplifier and can help reduce the size of the amplifier. The internal supply can accommodate both positive and negative common mode voltages and can be used for current sense amplifiers of any gain.

Claims

1. A power supply comprising: a selector circuit configured to receive a common mode voltage (V.sub.CM), an upper external voltage (V.sub.DD), and a lower external voltage (V.sub.GND), the selector circuit configured to: output a maximum voltage (V.sub.MAX) as the larger of the common mode voltage (V.sub.CM) and the upper external voltage (V.sub.DD); and output a minimum voltage (V.sub.MIN) as the smaller of the common mode voltage (V.sub.CM) and the lower external voltage (V.sub.GND); and a floating supply circuit configured to receive V.sub.MAX and V.sub.MIN from the selector circuit, the floating supply circuit configured to generate a floating voltage range defined by an upper internal voltage (V.sub.INTP) and a lower internal voltage (V.sub.INTN), the floating voltage range is level-shifted according to V.sub.MAXX and V.sub.MIN.

2. The power supply according to claim 1, wherein V.sub.CM is in a range that includes positive and negative voltages.

3. The power supply according to claim 1, wherein the selector circuit includes: a first pair of diodes are configured to connect the larger of V.sub.CM and V.sub.DD to a maximum-voltage output; and a second pair of diodes configured to connect the smaller of V.sub.CM and V.sub.GND to a minimum-voltage output. cm 4. The power supply according to claim 3, wherein the first pair of diodes and the second pair of diodes are Schottky diodes.

5. The power supply according to claim 3, wherein: the first pair of diodes are cathode-coupled at the maximum-voltage output; and the second pair of diodes are anode-coupled at the minimum-voltage output.

6. The power supply according to claim 1, wherein the selector circuit includes: a first pair of transistors configured to switch the larger of V.sub.CM and V.sub.DD to a maximum-voltage output; and a second pair of transistors configured to switch the smaller of V.sub.CM and V.sub.GND to a minimum-voltage output.

7. The power supply according to claim 6, wherein the first pair of transistors include: a first PMOS transistor connected between V.sub.CM and the maximum-voltage output, the first PMOS transistor switched by V.sub.DD; and a second PMOS transistor connected between V.sub.DD and the maximum-voltage output, the second PMOS transistor switched by V.sub.CM.

8. The power supply according to claim 6, wherein the second pair of transistors include: a first NMOS transistor connected between V.sub.CM and the minimum-voltage output, the first NMOS transistor switched by V.sub.GND; and a second NMOS transistor connected between V.sub.GND and the minimum-voltage output, the second NMOS transistor switched by V.sub.CM.

9. The power supply according to claim 1, wherein the floating supply circuit includes a regulation device coupled between a first output of the floating supply circuit and a second output of the floating supply circuit, the first output configured to output V.sub.INTP and the second output configured to output V.sub.INTN.

10. The power supply according to claim 9, wherein the regulation device is Zener diode.

11. The power supply according to claim 9, wherein the floating supply circuit includes: an NMOS transistor configured to couple the first output to V.sub.MAX when V.sub.CM is greater than V.sub.DD; and a PMOS transistor configured to couple the second output to V.sub.MIN when V.sub.CM is less than V.sub.GND.

12. A method for generating a floating voltage range, the method comprising: receiving a common mode voltage (V.sub.CM), an upper external voltage (V.sub.DD), and a lower external voltage (V.sub.GND); generating a maximum voltage (V.sub.MAX) as the larger of the common mode voltage (V.sub.CM) and the upper external voltage (V.sub.DD); generating a minimum voltage (V.sub.MIN) as the smaller of the common mode voltage (V.sub.CM) and the lower external voltage (V.sub.GND); floating an upper internal voltage (V.sub.INTP) to V.sub.MAX or a lower internal voltage (V.sub.INTN) to V.sub.MIN based on V.sub.CM; and regulating a voltage range between V.sub.INTP and V.sub.INTN to generate the floating voltage range.

13. The method for generating a floating voltage range according to claim 12, wherein the V.sub.CM is in a range that includes positive and negative voltages.

14. The method for generating a floating voltage range according to claim 12, wherein: generating V.sub.MAX includes using a first pair of diodes to switch the larger of V.sub.CM and V.sub.DD to a first output of a selector circuit; and generating V.sub.MIN includes using a second pair of diodes to switch the smaller of V.sub.CM and V.sub.GND to a second output of the selector circuit.

15. The method for generating a floating voltage range according to claim 14, wherein: the first pair of diodes and the second pair of diodes are Schottky diodes.

16. The method for generating a floating voltage range according to claim 12, wherein: generating V.sub.MAX includes using a first pair of transistors to switch the larger of V.sub.CM and V.sub.DD to a first output of a selector circuit; and generating V.sub.MIN includes using a second pair of transistors to switch the smaller of V.sub.CM and V.sub.GND to a second output of the selector circuit.

17. The method for generating a floating voltage range according to claim 14, wherein: the first pair of transistors are PMOS transistors, and the second pair of transistors are NMOS transistors.

18. The method for generating a floating voltage range according to claim 12, wherein the floating V.sub.INTP to V.sub.MAX or V.sub.INTN to V.sub.MIN based on V.sub.CM includes: coupling V.sub.INTP to V.sub.MAX when V.sub.CM is greater than V.sub.DD; and coupling V.sub.INTN to V.sub.MIN when V.sub.CM is less than V.sub.GND.

19. The method for generating a floating voltage range according to claim 12, wherein the regulating a voltage range between V.sub.INTP and V.sub.INTN to generate the floating voltage range includes: biasing a regulation device between V.sub.INTP and V.sub.INTN to generate the voltage range between V.sub.INTP and V.sub.INTN.

20. A floating power supply comprising: a selector circuit configured to receive a common mode voltage (V.sub.CM), an upper external voltage (V.sub.DD), and a lower external voltage (V.sub.GND), the selector circuit including: a maximum voltage (V.sub.MAX) circuit configured to output the larger of V.sub.CM and V.sub.DD as V.sub.MAX; and a minimum voltage (V.sub.MIN) circuit configured to output the smaller of V.sub.CM and V.sub.GND as V.sub.MIN; and a floating supply circuit configured to receive V.sub.MAX and V.sub.MIN from the selector circuit and to output an upper internal voltage (V.sub.INTP) and a lower internal voltage (V.sub.INTN), the floating supply circuit including: a regulation device configured to maintain a voltage difference between V.sub.INTP and V.sub.INTN; a first transistor configured to pull-up V.sub.INTP to V.sub.MAX when V.sub.CM is larger than V.sub.DD; and a second transistor configured to pull-down V.sub.INTN to V.sub.MIN when V.sub.CM is smaller than V.sub.GND.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. 1 is a block diagram of a system for amplification according to an implementation of the present disclosure.

[0010] FIG. 2 is a block diagram of an internal power supply for an amplifier according to an implementation of the present disclosure.

[0011] FIG. 3A is a schematic of a first possible implementation of the selector circuit for the internal power supply shown in FIG. 2.

[0012] FIG. 3B is a schematic of a second possible implementation of the selector circuit for the internal power supply shown in FIG. 2.

[0013] FIG. 4 is a schematic of a possible implementation of the floating supply circuit for the internal power supply shown in FIG. 2.

[0014] FIG. 5A is a graph of a possible floating voltage range defined by an upper internal voltage (V.sub.INTP) and a lower internal voltage (V.sub.INTN), the floating voltage range level shifted according to a common mode voltage (V.sub.CM) and having a regulated range (V.sub.REG) that is less than or equal to the external supply range (V.sub.DD-V.sub.GND).

[0015] FIG. 5B is a graph of a possible floating voltage range defined by a upper internal voltage (V.sub.INTP) and a lower internal voltage (V.sub.INTN), the floating voltage range level shifted according to a common mode voltage (V.sub.CM) and having a regulated range (V.sub.REG) that is greater than the external supply range (V.sub.DD-V.sub.GND).

[0016] FIG. 6 is a schematic of an amplifier according to a possible implementation of the present disclosure.

[0017] FIG. 7 is a detailed schematic of a possible implementation of a portion of the amplifier shown in FIG. 6.

[0018] FIG. 8 is a schematic the amplifier shown in FIG. 6 configured as a current-sense amplifier (CSA) according to a possible implementation of the present disclosure.

[0019] FIG. 9 is a graph of possible floating voltage ranges that are associated with implementations of a current sense amplifier with different gains.

[0020] FIG. 10 is a flow chart of a method for operating an amplifier over a range of possible common mode voltages.

[0021] The components in the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding parts throughout the several views.

DETAILED DESCRIPTION

[0022] The present disclosure describes an amplifier having a floating internal power supply (i.e., internal power supply) for generating a regulated voltage in a low voltage range. The regulated voltage is used to supply an input stage (i.e., core amplifier) so that it may receive an input voltage in a high voltage range. The regulated voltage is level-shifted (i.e., floated) to a voltage (V.sub.IN) appearing at an input stage so that the core amplifier may operate using low voltage (LV) devices, which can offer an improved performance (e.g., relative to a core amplifier that uses high voltage (HV) devices).

[0023] The disclosed circuits and techniques can be used for general purpose amplifiers or current sense amplifiers and can be used with amplifiers that operate with a unidirectional (e.g., positive) or a bidirectional (e.g., positive and negative) power supply and/or common mode input voltages. The disclosed circuits and techniques can reduce the number of HV devices in the amplifier required for operation with HV input common mode voltages and/or a HV external power supply voltages.

[0024] A reduction of the HV devices in the amplifier can result in a performance improvement. The performance improvement of the amplifier may correspond to an improvement (e.g., reduction) of a voltage offset (V.sub.OS), an improvement (e.g., increase) of a common-mode rejection ratio (CMRR), and/or an improvement (e.g., reduction) of a die area for (e.g., required for) the amplifier. For example, the disclosed circuits and techniques may result in a V.sub.OS that is approximately constant over a range of input common mode voltages.

[0025] Variations in common mode voltage (V.sub.CM) can change a bias point of a differential pair in the input stage of a typical amplifier due of mismatches between the devices in the input differential pair. This change is pronounced when HV devices are used. The mismatch may affect the amplifier's performance. For example, a range of V.sub.CM at the input of an amplifier using HV devices in the input stage can result in an input offset voltage (V.sub.OS) that is above a level desirable for precision applications, such as current sensing. On the other hand, an input stage with a differential pair including LV devices can be better matched. The improved matching decreases the variability in performance with V.sub.CM. The LV devices, however, cannot handle a wide range of V.sub.CM. Thus, using HV devices in an input stage can accommodate a wide range of V.sub.CM but can reduce the performance of the amplifier and increase the overall size of the amplifier. Schemes, such as chopping architectures, have been devised to improve the performance of amplifiers using HV devices. These approaches, however, can significantly add complexity. The amplifiers described herein address these issues in that they handle wide variations in V.sub.CM with high performance (e.g., comparable to chopping architectures) but without significant added complexity.

[0026] FIG. 1 is a block diagram of a system for amplification (i.e., system). The system 100 includes an external power supply 110 that generates voltages in a fixed voltage range defined by an upper (i.e., relatively positive, positive) external voltage (V.sub.DD) and a lower (i.e., relatively negative, negative) external voltage (V.sub.GND). The lower external voltage is negative in relation with (i.e., less than) the positive external voltage and not necessarily negative in an absolute sense. For example, V.sub.GND may be zero volts, while V.sub.DD may be 5 volts. The voltages V.sub.DD and V.sub.GND area applied to an amplifier 120 to enable operation of certain circuits (e.g., an internal power supply, at least one output stage 150, etc.).

[0027] In a possible implementation, the amplifier 120 may be a general purpose amplifier (GPA), which can be configured for various functions (e.g., buffer amplifier, inverting amplifier, summing amplifier, etc.) through feedback. In another possible implementation, the amplifier 120 may be a current sense amplifier (CSA). In the CSA implementation, the amplifier 120 may include a current sense (CS) resistor network 130 to sense a current and to provide a gain.

[0028] The amplifier 120 includes various stages to provide functions to receive an input signal (i.e., input) and provide an output signal. The amplifier 120 may be configured to amplify an input signal defined as a voltage different between a relatively positive (i.e., positive) input terminal (INP) of the amplifier 120 and a relatively negative (i.e., negative) input terminal (INN) of the amplifier. In some cases, the input signal includes a common mode voltage (V.sub.CM), and in some applications, such current sensing, it is desirable to ignore, reduce, or eliminate the V.sub.CM. Accordingly, a differential amplifier that responds only to voltage differences may be included in the amplifier to effectively eliminate the V.sub.CM. As shown in FIG. 1 the amplifier 120 includes a core amplifier (i.e., input stage, first stage, etc.) 140 to perform this function. In some implementations, a common mode voltage (V.sub.CM) of the amplifier can be the average of the input voltages appearing at each of a pair of differential inputs to the amplifier, or: V.sub.CM=(INP_AMP+INN_AMP)/2.

[0029] The core amplifier 140 can amplify a voltage difference at its input (i.e., INP_AMP-INN_AMP) using a differential pair of transistors provided that the transistors are biased appropriately. For example, if the voltage difference at the input of the core amplifier is 5V but the common mode voltage is 20V then the core amplifier can (e.g., must) be powered by at least the common mode voltage in order to perform the voltage difference amplification. This condition implies that high power supply voltages and/or transistors with high voltage ratings (i.e., HV transistors) can (e.g., must) be used for the core amplifier if large V.sub.CM are possible. As discuss previously, however, high voltage transistors in the input stage (i.e., core amplifier140) can negatively affect the overall size and performance of the amplifier 120. For example, accommodating a range of V.sub.CM using HV devices and/or high power supplies may lead to amplifiers that have large (e.g., >5 millivolt (mV)) V.sub.OS variations or the range of V.sub.CM.

[0030] The disclosed circuits and techniques can accommodate for a range of V.sub.CM that includes high voltages with a low voltage (LV) core amplifier 140 that includes low voltage devices (e.g., transistors) to avoid the reduction in performance. To enable operation of the LV core amplifier 140 with low voltage devices, the amplifier 120 includes an internal power supply 200 capable of floating with V.sub.CM so that the LV core amplifier 140 is properly biased to amplify the difference signal (i.e., INP_AMP_INN_AMP) regardless of the V.sub.CM at the input.

[0031] The internal power supply 200 (i.e., internal floating power supply) is configured to generate a floating voltage range defined by an upper internal voltage (V.sub.INTP) and a lower internal voltage (V.sub.INTN), the floating voltage range is level-shifted to a voltage based on a V.sub.CM at the input of the amplifier 120 and based on an a voltage (V.sub.IN) at the input of the core amplifier 140 so that the output of the core amplifier is in a first voltage range that corresponds to (e.g., is equivalent to) the floating voltage range (i.e., V.sub.INTN to V.sub.INTP).

[0032] The amplifier 120 further includes at least one output stage 150 to convert the first voltage range at the output of the LV core amplifier 140 to a second (i.e., output) voltage range at the output of the amplifier 120. The second voltage range at the output of the amplifier corresponds to (e.g., is equivalent to) the voltage range provided by the external power supply 110 (i.e., the fixed voltage range, V.sub.GND to V.sub.DD). The one or more output stages may function to convert (e.g., level shift) high voltages to low voltages or convert low voltages to high voltages depending on the implementation. Accordingly, the output stage(s) may include HV devices to perform the conversion. The inclusion of HV devices after the input stage does not significantly affect the overall performance of the amplifier 120.

[0033] The use of the terms high voltage (HV) and low voltage (LV) are relative to the scenario of a particular fixed voltage range provided to an amplifier designed for a V.sub.CM of zero. Voltages outside this particular fixed range can be considered as high voltages while voltages within this particular fixed range can be considered as low voltages. In one possible implementation the particular fixed voltage range is 5V (i.e., VDD=+5V, VGND=0V). Based on this scenario, a V.sub.CM in the range of 0V to +5V can be considered as a low voltage, while a V.sub.CM that is less than 0V or greater than +5V can be considered as a high voltage. The disclosed circuits and techniques allow the LV core amplifier to operate over a range of common mode voltages that may include high and low voltages and that may include positive or negative voltages. For the scenario described above (i.e., VDD=+5V, V.sub.GND=0V), V.sub.CM may be in a range of −80V to +80V. One advantage of the disclosed circuits and techniques is that they can accommodate a range of V.sub.CM that may include both positive and negative voltages.

[0034] FIG. 2 is a block diagram of an implementation of the internal power supply 200 for the amplifier 120. The internal power supply 200 includes a selector circuit 210 that receives V.sub.DD and V.sub.GND from the external power supply 110 and that receives V.sub.CM from the input of the amplifier 120. The selector circuit 210 is configured to select a maximum voltage (V.sub.MAX) and a minimum voltage (V.sub.MINfrom the received V.sub.DD, V.sub.CM, and V.sub.GND and to provide (i.e., output) these voltages to a floating supply circuit 220.

[0035] The selector circuit 210 may be implemented in a variety of ways. FIG. 3A is a schematic of a first possible implementation of the selector circuit 210. To determine V.sub.MAX, a pair of drain-connected PMOS transistors are coupled between, and switched by, V.sub.CM and V.sub.DD. For example, when V.sub.DD is lower than V.sub.CM, then a first p-type metal oxide semiconductor (PMOS) transistor 211 turns ON (i.e., conducts) while a second PMOS transistor 212 turns OFF (i.e., opens) so that V.sub.CM is coupled to an output, V.sub.MAX. Alternatively, when V.sub.CM is lower than V.sub.DD, then the second PMOS transistor 212 turns ON (i.e., conducts) while the first PMOS transistor 211 turns OFF (i.e., opens) so that V.sub.DD is coupled to the output, V.sub.MAX. V.sub.GND need not be considered when determining V.sub.MAX because it is assumed that V.sub.GND is less than V.sub.DD.

[0036] To determine V.sub.MIN in the selector circuit of FIG. 3A, a pair of drain-connected n-type metal oxide semiconductor (NMOS) transistors is coupled between, and switched by, V.sub.CM and V.sub.GND. For example, when V.sub.GND is higher than V.sub.CM, a first NMOS transistor 213 turns ON (i.e., conducts) while a second NMOS transistor 214 turns OFF (i.e., opens) so that V.sub.CM is coupled to an output, V.sub.MIN. Alternatively, when V.sub.CM is higher than V.sub.GND, then the second NMOS transistor 214 turns ON (i.e., conducts) while the first NMOS transistor 213 turns OFF (i.e., opens) so that V.sub.GND is coupled to the output, V.sub.MIN. V.sub.DD need not be considered when determining V.sub.MIN because it is assumed that V.sub.DD is higher than V.sub.GND.

[0037] FIG. 3B is a schematic of a second possible implementation of the selector circuit 210 for the internal power supply shown in FIG. 2. The selector circuit includes a first pair of cathode connected Schottky diodes cathode connected between V.sub.CM and V.sub.DD to determine V.sub.MAX. For example, when V.sub.CM is greater than V.sub.DD then a first Schottky diode 215 may couple V.sub.CM to an output, V.sub.MAX, and when V.sub.DD is greater than V.sub.CM, then a second Schottky diode 216 may couple V.sub.DD to the output, V.sub.MAX. The selector circuit shown in FIG. 3B also includes a second pair of anode connected Schottky diodes cathode connected between V.sub.CM and V.sub.GND to determine V.sub.MIN. For example, when V.sub.CM is lower (i.e., less) than V.sub.GND, then a third Schottky diode 217 may couple V.sub.CM to the output, V.sub.MIN, and when V.sub.GND is lower than V.sub.CM, then a fourth Schottky diode 218 may couple V.sub.GND to the output, V.sub.MIN.

[0038] As mentioned previously, the internal power supply 200 also includes a floating supply circuit 220. The floating supply circuit 220 receives the selected V.sub.MAX and V.sub.MIN from the selector circuit 210. Additionally, the floating supply circuit 220 receives an input voltage (V.sub.IN) from the input to the LV core amplifier 140. In some implementations (e.g., the GPA), V.sub.IN is equivalent to V.sub.CM, while in other implementations (e.g., the CSA), V.sub.IN may differ from V.sub.CM due to the resistor network 130 for current sensing. Further, it should be noted that, in some implementations, V.sub.IN might be received at the floating supply circuit 220 from the positive input terminal (INP_AMP) of the core amplifier 140, while in other implementations V.sub.IN may be received at the floating supply circuit 220 from the negative input terminal (INN_AMP) of the core amplifier 140. Based on the received voltages, the floating supply circuit 220 is configured to generate a voltage range defined by an upper (i.e., relatively positive) internal voltage (V.sub.INTP) and a lower (i.e., relatively negative) internal voltage (V.sub.INTN), which are provided to the LV core amplifier 140 for operation.

[0039] FIG. 4 is a schematic of a possible implementation of a floating supply circuit 220 for the internal power supply 200. The circuit includes an NMOS transistor 221 and a PMOS transistor 223 that are controlled based on the input voltage (V.sub.IN) to the LV core amplifier to operate in a complementary fashion. For example, the PMOS transistor 223 and the NMOS transistor 221 are configured so that when the NMOS transistor 221 is controlled (e.g. by VIN) to pass (i.e., regulate) a voltage, the PMOS transistor 223 is controlled to not pass (i.e., regulate) a voltage, and vice versa. The complementary operation may be achieved through fabrication (e.g., channel dimensioning) or via a bias voltage that can applied to a gate of either the NMOS transistor 221 or the PMOS transistor 223 to compensate for differences, thereby insuring complementary operation.

[0040] The floating supply circuit effectively level shifts (i.e., floats) a regulated voltage range (VREG) that is determined by a regulation device 225 (e.g., a voltage regulation device). The regulation device 225 may be selected/adjusted to provide a LV voltage range, which in some implementations may be approximately the range generated by the external power supply. For example, if V.sub.DD-V.sub.GND=5V then V.sub.REG may be configured as approximately 5V (e.g., 6V). The regulation device 225 may be a Zener diode or other regulating device (e.g., a PN diode, a diode-connected transistor, etc.). When a Zener diode is used as the regulation device 225, the breakdown voltage of the Zener diode corresponds to V.sub.REG.

[0041] The floating supply circuit 220 may pull-up (i.e., float, regulate, set, etc.) the regulated voltage range to V.sub.MAX using the sourcing current source 222 and the NMOS transistor 221. For example, if V.sub.CM>V.sub.DD (i.e., V.sub.MAX=V.sub.CM) then the NMOS transistor 221 and the sourcing current source 222 will operate together (i.e., based on V.sub.MAX and V.sub.IN) to effectively pull (i.e., regulate, set, etc.) V.sub.INTP up to V.sub.MAX. After V.sub.INTP is set, then V.sub.INTN is regulated below V.sub.INTP. In other words, after V.sub.INTP is pulled up to V.sub.MAX, the regulation device 225 (e.g., biased by sinking current source 224) regulates V.sub.INTN relative to V.sub.INTP by a regulated voltage drop (V.sub.REG). For example, if V.sub.MAX=20V, V.sub.REG=6V, and V.sub.IN is equal (or close to) V.sub.MAX, then the floating voltage range will be defined by V.sub.INTP≈20V and V.sub.INTN≈14V.

[0042] Alternatively, the floating supply circuit 220 may pull-down (i.e., float, regulate, set, etc.) the regulated voltage range to V.sub.MIN using the sinking current source 224 and the PMOS transistor 223. For example, if V.sub.CM<V.sub.GND (i.e., V.sub.MIN=V.sub.CM) then the PMOS transistor 223 and the sinking current source 224 will operate together (i.e., based on V.sub.MIN and V.sub.IN) to effectively pull (i.e., regulate, set, etc.) V.sub.INTN down to V.sub.MIN. After V.sub.INTN is set, then V.sub.INTP is regulated above V.sub.INTN. In other words, after V.sub.INTN is pulled down to V.sub.MIN, the regulation device 225 (e.g., biased by sourcing current source 222) regulates VINTP relative to V.sub.INTN by a regulated voltage rise (V.sub.REG). For example, if V.sub.GND=−20V, V.sub.REG=6V, and V.sub.IN is equal (or close to) V.sub.MIN, then the floating voltage range will be defined as V.sub.INTN≈−20V and V.sub.INTN≈−14V.

[0043] The internal power supply 200 self-regulates according to the voltage level (e.g., V.sub.CM) at the input of the core amplifier. This self-regulation is useful in accommodating a large range of voltages that includes both positive and negative voltages. The range of voltages may extend to voltages that are much higher than the devices in the LV core amplifier are rated. For example, V.sub.CM may be in a range of voltages that correspond to the limits of a device technology (e.g., −80V to +80V for devices with a maximum (e.g., V.sub.DS) rating of 80V), while the devices in the LV core amplifier are rated to receive less than the limits of the device technology (e.g., less than 10 volts). In other words, the fixed voltage range of an external power supply is smaller than the range of common-mode voltages, and the range of common-mode voltages is limited by a device technology, which may be selected as required. The internal power supply provides a consistent voltage level to the LV core amplifier even when V.sub.CM changes. This constant power corresponds to a voltage offset V.sub.OS of the LV core amplifier and is nearly constant as V.sub.CM varies. For example, V.sub.OS of a CSA amplifier implementation may have a maximum value of 2 millivolts (mV) over a full V.sub.CM range from −80V to +80V. Additionally, a power supply rejection ratio (i.e., PSRR) of the LV core amplifier in the CSA amplifier implementation may have a minimum value of 90 dB over the same range. The values of these parameters are similar to those expected from CSA amplifiers that utilize offset compensation techniques.

[0044] FIG. 5A is a graph of a possible floating voltage range (i.e., V.sub.INTP-V.sub.INTN) appearing at the output of the internal power supply 200 for a first possible implementation. The floating voltage range is level shifted (i.e., floated) according to a common mode voltage (VC.sub.M). For this implementation, V.sub.REG (i.e., the floated voltage range) is less than the fixed voltage range (V.sub.DD-V.sub.GND) supplied by the external power supply 110. Accordingly, the voltage regulation device 225 operates for all V.sub.CM values. In other words, when V.sub.CM is in the range V.sub.GND<V.sub.CM<V.sub.DD, the voltage appearing at the terminals of the regulation device 225 in the floating supply circuit 220 remains large enough to maintain voltage regulation. For example, a Zener diode used as the regulation device 225 will remain in breakdown (i.e., will regulate) across the entire range of V.sub.CM when V.sub.REG≤(V.sub.DD-V.sub.GND). As a result, the graph shown in FIG. 5A shows no variation of V.sub.REG with V.sub.CM.

[0045] FIG. 5B is a graph of a possible floating voltage range (i.e., V.sub.INTP-V.sub.INTN) appearing at the output of the internal power supply 200 for a second possible implementation. The floating voltage range is level shifted according to a common mode voltage (VC.sub.M). For this implementation, V.sub.REG (i.e., the floated voltage range) is greater than the fixed voltage range (V.sub.DD-V.sub.GND) supplied by the external power supply 110. Accordingly, the regulating device does not regulate when V.sub.MAX=V.sub.DD and V.sub.MIN=V.sub.GND. In other words, when V.sub.CM is in a range 500 where V.sub.GND<V.sub.CM<V.sub.DD, the voltage appearing at the terminals of the regulation device 225 in the floating supply circuit 220 is not large enough to maintain voltage regulation. As a result, V.sub.DD and V.sub.GND appear at the output of the floating supply circuit 220 as V.sub.INTP and V.sub.INTN respectively. For example, a Zener diode used as the regulation device 225 will not remain in breakdown (i.e., will not regulate) in the range 500 where V.sub.GND<V.sub.CM<V.sub.DD. As a result, the graph shown in FIG. 5A shows a V.sub.REG that varies slightly with V.sub.CM. The variation is small, because V.sub.REG can be selected close (e.g., within a couple of volts) to V.sub.DD-V.sub.GND. Accordingly, the LV core amplifier 140 can still operate with LV devices and any V.sub.OS variation with V.sub.CM will remain small.

[0046] FIG. 6 is a schematic of an amplifier 120 according to a possible implementation of the present disclosure. FIG. 6 illustrates the details of the amplifier 120 of FIG. 1, including the connections between the internal power supply 200, the core amplifier140, and the at least one output stage 150.

[0047] The internal supply 200 shown in FIG. 6 produces a low voltage (V.sub.INTP-V.sub.INTN) based on V.sub.MAX, V.sub.MIN, and the input (INN_AMP) to the LV core amplifier 140. In the floating supply circuit 220, the sourcing current source 222 (i.e., CS1) can function when V.sub.CM is negative and the sinking current source 224 (i.e., CS2) can function when V.sub.CM is positive. In some implementations, the sourcing current source 222 and the sinking current source 224 are implemented as current mirror circuits. Also, in the floating supply circuit 220, the NMOS transistor 221 (i.e., M1) and the PMOS transistor 223 (i.e., M2) can be controlled by negative input, INN_AMP, but in alternative implementations the NMOS transistor 221 and the PMOS transistor 223 are controlled by the positive input, INP_AMP. In still other implementations, the gate voltage of the NMOS transistor 221 is at a voltage relative to the gate voltage off PMOS transistor 223. For example, for a current source amplifier INN_AMP and INP_AMP may be coupled to opposite sides of a current carrying resistor.

[0048] The LV core amplifier 140 shown in FIG. 6 can be a differential amplifier. The inputs to the amplifier (INP_AMP, INN_AMP) can accommodate high voltages but the differential amplifier is implemented with LV devices because it is powered by a low voltage difference (V.sub.INTP-V.sub.INTN).

[0049] A first output stage 151 shown in FIG. 6 can be configured to convert (i.e., level shifts) a high voltage to a low voltage, although in some implementations, the first output stage 151 can convert a low voltage to a high voltage. In either case, the first output stage 151 can include summing nodes and high voltage protection circuits that are implemented with one or more high voltage devices.

[0050] A second (i.e., final) output stage 152 shown in FIG. 6 can be a standard amplifier output stage to provide the output signal with sufficient output power in the form of voltage or current. For example, the final output stage 152 can be a class AB amplifier stage.

[0051] FIG. 7 is a detailed schematic of a possible implementation of a portion of the amplifier shown in FIG. 6. The portion shown includes the LV core amplifier 140, the first output stage 151, and the second (i.e., final) output stage 152. For the implementation shown, a differential pair 700 of the LV core amplifier 140 is supplied between V.sub.INTP and V.sub.INTN. The voltage range shift from the LV core amplifier 140 stage to the final output stage 152 can be accomplished using current mirrors, which have HV protection. These circuits are the circuits (e.g., only circuits) in which HV devices are used. One advantage of this implementation is the fact that the HV devices after the input stage do not negatively affect the performance (e.g., V.sub.OS) of the amplifier 120.

[0052] FIG. 8 is a schematic the amplifier shown in FIG. 6 configured as a current-sense amplifier (CSA) according to a possible implementation of the present disclosure. As shown, the amplifier 120 includes a current-sense (CS) resistor network 130 for sensing the current. The transistors M1 and M2 may be biased at different points along the CS resistor network 130. An advantage of this approach is that the various bias points can be used to adjust the gate to source voltages of the transistor M1 and M2 to ensure a correct voltage level for VINTP and/or VINTN. The disclosure circuits and techniques may offer similar performance as CSA amplifiers that utilize chopping to improve CMRR. For example, the CSA amplifier of the disclosure may have a minimum CMRR of 90 dB.

[0053] For the implementation shown in FIG. 8, the input of the LV core amplifier 140 (i.e., INN_AMP, INP_AMP) is coupled to the input of the amplifier 120 (I.e., INN, INP) through the CS resistor network. Accordingly, a voltage (e.g., V.sub.CM) at the input of the amplifier 120 may differ from a voltage (e.g., VIN) at the input of the LV core amplifier 140. The difference can depend on the implementation (e.g., resistor values) of the CS resistor network 130 and/or how it is coupled to the other stages in the amplifier 120. The LV core amplifier includes feedback through the CS resistor network 130. Accordingly, the CS resistor network 130 provides a gain (G). The gain of the CS resistor network 130 shown in FIG. 8 R3/(R1+R2). When the gain is high, V.sub.IN is approximately equal to V.sub.CM. However, as the gain is reduced, the difference between V.sub.IN and V.sub.CM becomes larger.

[0054] The effect of the CSA gain on the floating voltage range is shown in FIG. 9. FIG. 9 is a graph of possible floating voltage ranges for current sense amplifiers having different gains. As shown, the slope of the floating voltage range changes but floats as expected for any gain option. All gain values can be accommodated because the input voltage of the core amplifier (V.sub.IN) is used to control the floating supply circuit 220 rather than an input voltage of the amplifier (V.sub.CM). This means that for gains in which V.sub.CM and V.sub.IN deviate from one another, the voltage supplying the LV core amplifier will always be floated by the appropriate amount. Thus, an advantage of the disclosed circuits and techniques is the CSA architecture is not limited to any particular gains or resistance values of the CS resistor network 130.

[0055] FIG. 10 is a flow chart of a method for operating an amplifier over a range of possible common mode voltages without an input stage of the amplifier using (i.e., including) devices rated for the entire range of possible common mode voltage (i.e., the input stage of the amplifier uses only LV devices). The method 1000 includes receiving 1010 a fixed voltage range (V.sub.DD-V.sub.GND) and an input voltage (V.sub.CM) at the amplifier. A maximum (V.sub.MAX) and a minimum (V.sub.MIN) of V.sub.DD, V.sub.GND and V.sub.CM are the selected 1020 and used to generate 1020 a floating voltage range. The floating voltage range is a regulated voltage range that is level shifted to VMAX or VMIN according got an input voltage (V.sub.IN) at a first (i.e., input) stage of the amplifier. The floated voltage range allows the amplifier to include (e.g., only include) device rated for the regulated voltage range (i.e., not the common mode voltage at the input to the first stage).

[0056] In the specification and/or figures, typical embodiments have been disclosed. The present disclosure is not limited to such exemplary embodiments. The use of the term “and/or” includes any and all combinations of one or more of the associated listed items. Unless otherwise noted, specific terms have been used in a generic and descriptive sense and not for purposes of limitation. As used in this specification, a singular form may, unless definitely indicating a particular case in terms of the context, include a plural form.

[0057] It will be understood that, in the foregoing description, when an element, such as a component is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it may be directly on, connected or coupled to the other element, or one or more intervening elements may be present. It will also be understood that, in the foregoing description, when a pair of voltages has constituent voltages described as positive or negative, this description is in reference to the relationship between the voltages in the pair and not necessarily in reference to the absolute value of each voltage. Likewise, when a terminal (i.e., connector, input) of a pair of terminals is described as positive or negative, this description is in reference to a voltage/current expected at the terminal in relation to the other terminal and not necessarily in reference to the absolute value of the voltage/current at the terminal.

[0058] Some implementations may be implemented using various semiconductor processing and/or packaging techniques. Some implementations may be implemented using various types of semiconductor processing techniques associated with semiconductor substrates including, but not limited to, for example, Silicon (Si), Gallium Arsenide (GaAs), Gallium Nitride (GaN), Silicon Carbide (SiC) and/or so forth.

[0059] While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the implementations. It should be understood that they have been presented by way of example only, not limitation, and various changes in form and details may be made. Any portion of the apparatus and/or methods described herein may be combined in any combination, except mutually exclusive combinations. The implementations described herein can include various combinations and/or sub-combinations of the functions, components, and/or features of the different implementations described.