DEVICE AND METHOD FOR ASCERTAINING A MECHANICAL STRESS COMPONENT BY MEANS OF A HALL SENSOR CIRCUIT

Abstract

The subject matter described herein relates to a semiconductor circuit arrangement with a semiconductor substrate with an integrated Hall sensor circuit. During a first clock phase PH.sub.spin1 a first electrical voltage signal ±V.sub.Hallout(PH.sub.spin1) or ±V.sub.Hallbias(PH.sub.spin1) can be generated in the Hall effect region that has a first dependency on a mechanical stress of the semiconductor substrate. During a second clock phase PH.sub.spin2 a second electrical voltage signal ±V.sub.Hallout(PH.sub.spin2) or ±V.sub.Hallbias(PH.sub.spin2) can be generated in the Hall effect region that has a second dependency on a mechanical stress of the semiconductor substrate. The semiconductor circuit arrangement is designed to ascertain a specific mechanical stress component based on a combination of the first electrical voltage signal +V.sub.Hallout(PH.sub.spin1) or ±V.sub.Hallbias(PH.sub.spin1) and of the second electrical voltage signal ±V.sub.Hallout(PH.sub.spin2) or ±V.sub.Hallbias(PH.sub.spin2).

Claims

1. A semiconductor circuit arrangement with a semiconductor substrate, wherein the semiconductor substrate comprises an integrated Hall sensor circuit with a first terminal and a second terminal positioned opposite the first terminal, and a third terminal and a fourth terminal positioned opposite the third terminal, wherein the integrated Hall sensor circuit is configured to: guide a Hall supply current between the first terminal and the second terminal at a first angle to a normal to a primary flat plane of the semiconductor substrate, laterally through a Hall effect region during a first clock phase and to generate a first electrical voltage signal in the Hall effect region, wherein the first electrical voltage signal has a first dependency on a mechanical stress of the semiconductor substrate, and guide a Hall supply current between the third terminal and the fourth terminal at a second angle that is orthogonal to the first angle laterally through the Hall effect region during a second clock phase, and to generate a second electrical voltage signal in the Hall effect region, wherein the second electrical voltage signal has a second dependency on a mechanical stress of the semiconductor substrate, and wherein the semiconductor circuit arrangement is configured to ascertain a specific mechanical stress component based on a combination of the first electrical voltage signal and of the second electrical voltage signal.

2. The semiconductor circuit arrangement as claimed in claim 1, wherein the semiconductor circuit arrangement is further configured to use the mechanical stress component ascertained using the integrated Hall sensor circuit to compensate for a negative influence of the mechanical stress component on at least one of a parametric accuracy or parametric stability of a component that is arranged on the semiconductor substrate but is separate from the integrated Hall sensor circuit or of a further circuit arrangement integrated into the semiconductor substrate.

3. The semiconductor circuit arrangement as claimed in claim 1, wherein the first angle has a value of +45° to the normal to the primary flat plane of the semiconductor substrate, and wherein the second angle has a value of −45° to the normal to the primary flat plane of the semiconductor substrate.

4. The semiconductor circuit arrangement as claimed in claim 1, wherein the semiconductor substrate is a semiconductor substrate, and wherein the integrated Hall sensor circuit is configured to guide the Hall supply current during the first clock phase PH.sub.spin1 in a [100], [100] or [010] direction laterally through the Hall effect region, and during the second clock phase to guide the Hall supply current in a [100], [010], [100] or [010] direction that is respectively orthogonal to the first clock phase laterally through the Hall effect region.

5. The semiconductor circuit arrangement as claimed in claim 3, wherein the integrated Hall sensor circuit is configured to use a voltage drop between the first terminal and the second terminal during the first clock phase as a first voltage signal and to use a voltage drop between the third terminal and the fourth terminal as a second voltage signal during the second clock phase, and wherein the semiconductor circuit arrangement is configured to form a difference between the first and second electrical voltage signals and to ascertain a mechanical shear stress component in the semiconductor substrate on that basis.

6. The semiconductor circuit arrangement as claimed in claim 3, wherein the integrated Hall sensor circuit is configured to use a voltage drop between the first terminal and the second terminal during the first clock phase as a first voltage signal, and to use a voltage drop between the third terminal and the fourth terminal as a second voltage signal during the second clock phase, and wherein the semiconductor circuit arrangement is configured to form a sum of the first and second electrical voltage signals and to ascertain a mechanical normal stress component in the semiconductor substrate on that basis.

7. The semiconductor circuit arrangement as claimed in claim 3, wherein the integrated Hall sensor circuit is configured to use a voltage drop between the third terminal and the fourth terminal during the first clock phase PH.sub.spin1 as a first voltage signal, and to use a voltage drop between the first terminal and the second terminal as a second voltage signal during the second clock phase, and wherein the semiconductor circuit arrangement is configured to form a difference between the first and second electrical voltage signals and to ascertain a mechanical normal stress component the semiconductor substrate on that basis.

8. The semiconductor circuit arrangement as claimed in claim 1, wherein the first angle has a value of 0° to the normal to the primary flat plane of the semiconductor substrate, and wherein the second angle has a value of 90° to the normal to the primary flat plane of the semiconductor substrate.

9. A semiconductor circuit arrangement as claimed in claim 1, wherein the semiconductor substrate is a semiconductor substrate, and wherein the integrated Hall sensor circuit is configured to guide the Hall supply current during the first clock phase in a [110], [110], [110] or [110] direction laterally through the Hall effect region, and during the second clock phase to guide the Hall supply current in a [110], [110], [110] or [110] direction that is respectively orthogonal to the first clock phase laterally through the Hall effect region.

10. The semiconductor circuit arrangement as claimed in claim 8, wherein the integrated Hall sensor circuit is configured to use a voltage drop between the first terminal and the second terminal during the first clock phase PH.sub.spin1 as a first voltage signal, and to use a voltage drop between the third terminal and the fourth terminal as a second voltage signal during the second clock phase, and wherein the semiconductor circuit arrangement is configured to form a difference between the first and second electrical voltage signals and to ascertain a mechanical normal stress component in the semiconductor substrate on that basis

11. The semiconductor circuit arrangement as claimed in claim 8, wherein the integrated Hall sensor circuit is configured to use a voltage drop between the third terminal and the fourth terminal as a first voltage signal during the first clock phase, and to use a voltage drop between the first terminal and the second terminal as a second voltage signal during the second clock phase, and wherein the semiconductor circuit arrangement is configured to form a difference between the first and second electrical voltage signals and to ascertain a mechanical shear stress component in the semiconductor substrate on that basis.

12. The semiconductor circuit arrangement as claimed in claim 8, wherein the integrated Hall sensor circuit is configured to use a voltage drop between the first terminal and the second terminal as a first voltage signal during the first clock phase, and to use a voltage drop between the third terminal and the fourth terminal as a second voltage signal during the second clock phase, and wherein the semiconductor circuit arrangement is configured to form a sum of the first and second electrical voltage signal and to ascertain a mechanical normal stress component in the semiconductor substrate on that basis.

13. The semiconductor circuit arrangement as claimed in claim 5, wherein the semiconductor circuit arrangement is configured to compensate an orthogonality error of a Hall effect-based angle sensor, separate from the integrated Hall sensor circuit, with a horizontal Hall plate and a vertical Hall device based on the ascertained mechanical shear stress component.

14. The semiconductor circuit arrangement as claimed in claim 6, wherein the semiconductor circuit arrangement is configured to increase a sensitivity, that depends on the normal stress, of a horizontal Hall plate separate from the integrated Hall sensor circuit based on the ascertained mechanical normal stress component.

15. The semiconductor circuit arrangement as claimed in wherein the semiconductor circuit arrangement is configured to compensate a frequency deviation, that depends on the normal stress, of an oscillator mounted on the semiconductor substrate together with the integrated Hall sensor circuit, or to increase a sensitivity, that depends on the normal stress, of a magnetic current sensor separate from the integrated Hall sensor circuit based on the ascertained mechanical normal stress component.

16. A method for ascertaining a mechanical stress component using a semiconductor circuit arrangement with a semiconductor substrate and a Hall sensor circuit integrated therein, wherein the Hall sensor circuit comprises a first terminal and a second terminal positioned opposite the first terminal, and as well as a third terminal and a fourth terminal positioned opposite the third terminal, and wherein the method comprises: applying a Hall supply current during a first clock phase between the first terminal and the second terminal in order to guide the Hall supply current at a first angle to a normal to a primary flat plane of the semiconductor substrate, laterally through a Hall effect region of the Hall sensor circuit, wherein the Hall supply current generates a first electrical voltage signal in the Hall effect region, wherein the first electrical voltage signal has a first dependency on a mechanical stress of the semiconductor substrate, and applying a Hall supply current during a second clock phase between the third terminal and the, fourth terminal to guide the Hall supply current at a second angle that is orthogonal to the first angle, laterally through the Hall effect region of the Hall sensor circuit, wherein the Hall supply current generates a second electrical voltage signal in the Hall effect region, and wherein the second electrical voltage signal has a second dependency on a mechanical stress of the semiconductor substrate, and ascertaining a specific mechanical stress component based on a combination of the first electrical voltage signal and of the second electrical voltage signal.

17. A computer program with program code for carrying out the method as claimed in claim 16 when the computer program is executed on a computer

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Some example implementations are illustrated, by way of example, in the drawing and are explained below. Here:

[0025] FIGS. 1A-1C show general definitions of crystallographic directions in the plane (wafer plane) of a semiconductor material,

[0026] FIG. 2 shows a schematic illustration of a semiconductor circuit arrangement for compensating a mechanical stress of a Hall sensor circuit integrated into a semiconductor substrate,

[0027] FIG. 3 shows an L-resistor arrangement,

[0028] FIGS. 4A-4B show a schematic overview of a circuit diagram to illustrate the semiconductor circuit arrangement with the integrated Hall sensor circuit according to one example implementation,

[0029] FIGS. 5A-5B show a schematic view of two example implementations of Hall sensor circuits that are configured to ascertain a difference stress,

[0030] FIG. 5C shows a schematic view to illustrate a component separate from the Hall sensor circuit, whose stress-dependent parameter deviations can be compensated for through the application of the ascertained difference stress,

[0031] FIGS. 6A-6B show a schematic view of two example implementations of Hall sensor circuits that are configured to ascertain a shear stress,

[0032] FIG. 6C shows a schematic view to illustrate a component separate from the Hall sensor circuit, whose stress-dependent parameter deviations can be compensated for through the application of the ascertained shear stress,

[0033] FIGS. 7A-7B show a schematic view of two example implementations of Hall sensor circuits that are configured to ascertain an aggregate stress,

[0034] FIG. 7C shows a schematic view to illustrate a component separate from the Hall sensor circuit, whose stress-dependent parameter deviations can be compensated for through the application of the ascertained aggregate stress,

[0035] FIG. 8A shows a schematic view of an example implementation of a Hall sensor circuit that is configured to measure a magnetic field and to ascertain an aggregate stress,

[0036] FIG. 8B shows a schematic view of an example implementation of a Hall sensor circuit that is configured to measure a magnetic field and to ascertain a shear stress,

[0037] FIG. 8C shows a schematic view to illustrate the Hall sensor circuit that is configured to measure a magnetic field with the compensation of an initial offset error, and

[0038] FIG. 9 shows a schematic view to illustrate a method according to one example implementation.

DETAILED DESCRIPTION

[0039] Example implementations are described with reference to the figures in more detail below, wherein elements with the same or similar functions are given the same reference signs.

[0040] Method steps that are illustrated in one block diagram and explained in that context can also be carried out in a sequence other than that illustrated or described. In addition, method steps that relate to a specific feature of a device can be exchanged with this very feature of the device, and the opposite is equally true.

[0041] Integrated Hall sensor circuits are treated below. This can in particular involve lateral Hall plates. The term “lateral” is to be understood here in the sense of “parallel to the chip surface”. The lateral Hall plates can also be referred to as horizontal Hall plates or planar Hall plates.

[0042] A semiconductor substrate with an integrated Hall sensor circuit is described in example implementations. This integrated Hall sensor circuit can comprise a first terminal and a second terminal positioned opposite the first terminal, as well as additionally a third terminal and a fourth terminal positioned opposite the third terminal. In some example implementations, the integrated Hall sensor circuit can comprise precisely or exclusively these four terminals just mentioned. In further example implementations, in precisely four spinning phases, all the stresses for calculation of the stress components s.sub.xx+s.sub.yy, s.sub.xx−s.sub.yy and s.sub.xy and a Hall voltage are ascertained, and each individual component obtained by forming the sum and/or difference of at least two spinning phases.

[0043] In order to simplify the understanding of the following detailed description of a semiconductor circuit arrangement for compensating various piezo effects, the definitions used below relating to the semiconductor material used and the specified directions on the same crystal alignment of the semiconductor material are now first illustrated based on FIGS. 1A to 1C.

[0044] To manufacture integrated circuits, the semiconductor wafers such as, for example, silicon wafers or silicon disks, are sawn off a monocrystalline bar in such a way that the wafer surface is associated with one crystallographic plane. What are known as the “Miller indices” are used in order to specify the respective plane in a cubic crystal. FIG. 1A shows, for example, a plan view of a semiconductor wafer that is cut in the (100) plane.

[0045] In FIGS. 1A to 1C the primary crystallographic directions are furthermore indicated in the wafer plane, wherein the manufacturers of silicon wafers often provide what is known as a “primary flat” at the silicon disk. Notches or the like can equally well be used for identification. Notches of this type should thus be understood as equivalent to a primary flat in the context of this disclosure. The edges of the rectangular geometries of the circuit structures on the semiconductor chip usually run parallel to or perpendicular to the primary flats. In particular, in FIG. 1A the crystallographic directions or axes in the plane of the semiconductor wafer are illustrated, wherein these are represented below in square brackets. The coordinate system is usually used in such a way that the [110] direction extends perpendicular to, or normal to, the primary flat, while the [110] direction extends parallel to the primary flat. The directions [010] and [100] extend at an angle of ±45° to the [110] direction, which defines a normal to the primary flat plane. The directions [010] and [100] extend at an angle of ±45° to the [110] direction, that also defines a normal (in the direction opposite to [110]) to the primary flat plane.

[0046] An angle Φ with respect to the [110] direction is also defined, wherein the angle Φ is counted counterclockwise in a plan view on the top face of the wafer, starting from the direction. The individual chips are usually positioned on the wafer in such a way that the directions Φ=0° and Φ=90° correspond to the vertical and horizontal directions respectively of the IC, wherein these directions can be interchanged, depending on whether the IC is positioned upright or lying down. In what follows, furthermore, the direction Φ=90° is referred to as the x-axis [110] direction, and the direction Φ=0° as the negative y-axis ([110] direction).

[0047] On the assumption that the x-axis is identical to the crystal direction [110], and the y-axis is identical to the [110] crystal direction, this in particular means that the semiconductor circuit chip is manufactured from a {100} semiconductor material ({100} silicon, for example). The primary flat is then usually parallel to the x-axis, so that the edges of the semiconductor circuit chip are parallel to the x-axis and the y-axis. The crystal directions [100] and [010] are then identical to the diagonals of the semiconductor circuit chip (cf. FIG. 1B).

[0048] Since a {100} silicon material is used in the majority of applications for integrated semiconductor circuit arrangements, the following explanations refer, for the sake of simplifying the explanations, and due to their particular practical significance, above all to the numerical values for {100} silicon material that are relevant for this material. It should, however, be obvious to the person skilled in the art that other semiconductor materials, or other silicon materials, can accordingly also be used.

[0049] This mechanical stress is a tensor magnitude, and refers to the force per unit area that acts within a rigid body under the influence of a mechanical load. This force can be represented by cutting the rigid body. This force must theoretically be applied to the cut planes for the body to receive the same load.

[0050] FIG. 1C shows a small block that has been cut out of a rigid body. As can be seen, such a cut through the body can have various orientations, which in turn influences the forces at the cut surfaces. This means that the force (which is a vector) also depends on the orientation of the cut. This force (e.g. the mechanical stress) accordingly also has more than three degrees of freedom. The illustrated block has cut surfaces that are respectively parallel to the x, y and z axes. The forces at each of the cut surfaces can be decomposed into individual components, each of which point in the x, y and z directions. At each cut surface there is a component that is perpendicular to the surface: this is the normal stress component σ.sub.XX. Two adjacent components are found at each cut surface, extending parallel to the surface: these are the shear stress components σ.sub.XY, σ.sub.XZ. The first index identifies the direction of the surface, and the second index identifies the direction of the force.

[0051] The normal stress can be a compressive stress or a tensile stress, depending on the arithmetic sign. Normal stresses act perpendicularly to the coordinate surface, meaning that the normal direction and the direction of action are the same. The shear stress acts tangentially to the surface, and represents a shear loading.

[0052] There are altogether nine components, there being three cut surfaces, each of which has a normal stress component and two shear stress components. The forces at the opposite regions (e.g. the negative planes with normal vectors in the negative x, y and z directions) are of the same magnitude, but have negative arithmetic signs. If the forces, or the moment equilibria, are applied to the block illustrated in FIG. 1C, it can be seen that the shear stresses are equal when their indices are interchanged: σ.sub.YZ=σ.sub.ZY, σ.sub.XZ=σ.sub.ZX, σ.sub.XY=σ.sub.YX. Finally, we thus finish with six independent components of the stress tensor, e.g. three normal stress components, σ.sub.XX, σ.sub.YY, σ.sub.ZZ and three shear stress components OTZ, CPCZ, am

[0053] Usually not all six stress components have to be considered at the same time, since in the case of microelectronic packages what are known as laminates are usually used, whose lateral extension in the x, y directions is significantly larger than its thickness in the z direction (see also FIG. 1B).

[0054] A semiconductor circuit arrangement 20 for the compensation of a mechanical stress of a Hall sensor circuit integrated into a semiconductor substrate will now be described in the following with reference to FIG. 2. This schematically illustrated semiconductor circuit arrangement 20 comprises a Hall sensor circuit 21 integrated into the semiconductor substrate. The Hall sensor circuit 21 is configured to guide a Hall supply current between a first terminal 22 and a second terminal 23 of a Hall effect region or Hall plate 24 at a 90° angle to a normal to a primary flat plane of the semiconductor substrate laterally through the Hall effect region 24 (for example thus in the [110] direction) during a first clock interval PH1. During the first clock interval PH1 a first voltage Vph1 is, for example, measured at the first terminal 22 of the Hall effect region 24, and digitized by an analog-to-digital converter (ADC) 27. For the [110] direction shown here by way of example as the first current direction, a stress-direction-dependent change in resistance of

δR[110]=−31.2 δ.sub.xx−17.68 δ.sub.yy+53.4 δ.sub.zz

[0055] results by way of example for n-diffusion resistors from mechanical stress.

[0056] This means that in the case of a current direction in the [110] direction, the total resistance undergoes a change of −31.2% per GPa caused by the mechanical normal stress component σ.sub.XX and a change of −17.6% per GPa caused by the mechanical normal stress component σ.sub.YY, and a change of +53.4% per GPa caused by the mechanical normal stress component σ.sub.ZZ.

[0057] The Hall sensor circuit 21 is configured to guide the Hall supply current between a third terminal 25 and a fourth terminal 26 of the Hall effect region 24 at a 0° angle to the normal to the primary flat plane of the semiconductor substrate laterally through the Hall effect region 24 (thus for example in the [110] direction) during a second clock interval PH2. During the second clock interval PH2 a second Hall voltage Vph2 is, for example, measured at the first terminal 22 of the Hall effect region 24, and digitized by the ADC 27. For the [110] direction shown here by way of example as the second current direction, a stress-direction-dependent change in resistance of

δR[110]=−17.6 δ.sub.xx−31.2 δ.sub.yy+53.4 δ.sub.zz

[0058] results by way of example for n-diffusion resistors from mechanical stress.

[0059] The current directions of the two clock phases PH1 and PH2 can, of course, also be interchanged. With the semiconductor circuit arrangement 20 the directional dependency of piezo-resistive effects can be eliminated in that current flows through the Hall effect region 24 during the first clock interval PH1 at an angle of 90° (or an angle of 0°) to the normal to the primary flat plane and flows in a direction orthogonal to that during the second clock interval PH2, and wherein a time average of the two clock intervals can be made. As a result of the two averaged clock intervals, the Hall effect region 24 behaves like two laterally orthogonal resistors in what is known as the L layout (see FIG. 3) which behaves independently with respect to mechanical stress compared to a rotation of the whole arrangement through ±45°. In an example {100} silicon semiconductor material, the piezo-resistive coefficients π.sub.11 and π.sub.12, along with the normal stress components σ.sub.XX and σ.sub.YY in the plane of the chip surface, are above all relevant for the piezo-resistive effect. For n-doped resistors in a lateral L layout according to FIG. 3, the equation that applies is: δR.sup.a.sub.L=−24.4%/GPa (σ.sub.XX, σ.sub.YY). This means that the total resistance undergoes a change of -24.4% per GPa under the influence of the normal stress components σ.sub.XX, σ.sub.YY. The change in the resistance can in this case thus be essentially or exclusively dependent on the two normal stress components σ.sub.XX, σ.sub.YY.

[0060] As just explained, with the semiconductor circuit arrangement 20 illustrated here, the directional dependency of piezo-resistive effects can be eliminated in that current flows through the Hall effect region 24 during the first clock interval PH1 at an angle of 90° (or an angle of 0°) to the normal to the primary flat plane and flows in a direction orthogonal to that during the second clock interval PH2, wherein a time average of the two clock intervals can be made.

[0061] It is recognized in accordance with the concept described here, that the stress components ascertained using the Hall sensor circuit can not only be used to compensate for negative effects on the Hall sensor circuit caused by stress, but also to compensate for negative effects on other components and/or circuits, e.g. that are separate from the Hall sensor circuit, caused by stress, in particular in the case in which these separate components and/or circuits are integrated onto the same semiconductor substrate as the Hall sensor circuit.

[0062] FIGS. 4A and 4B show a device for ascertaining mechanical stress components. The device can be a semiconductor circuit arrangement 100 with a semiconductor substrate, wherein the semiconductor substrate comprises an integrated Hall sensor circuit 101. The semiconductor substrate can, for example, be a {100} silicon substrate. It should be explained that here we only have a purely schematic illustration of the Hall sensor circuit 101 in a first clock phase PHI or PH.sub.spin1 and a second clock phase PH2 or PH.sub.spin2. This means that although two Hall sensor circuits 101 are shown here, these are in fact one and the same Hall sensor circuit that is simply illustrated once in the first clock phase PH1 and once in the second clock phase PH2.

[0063] An enlarged illustration of the Hall sensor circuit 101 in the two clock phases PH1 and PH2 is shown to the top left of the image in FIGS. 4A and 4B. On the left-hand side, e.g. in the first clock phase PH1, a Hall supply current 102 is guided between a first terminal 111 and a second terminal 112 laterally through the Hall sensor circuit 101. In the case of the {100} silicon described here purely by way of example, the Hall supply current 102 flows in the [010] direction through the Hall sensor circuit 101. On the right-hand side, e.g. in the second clock phase PH2, a Hall supply current 102 is guided between a third terminal 113 and a fourth terminal 114 laterally through the Hall sensor circuit 101. In the case of the {100} silicon described here purely by way of example, the Hall supply current 102 flows in the [100] direction through the Hall sensor circuit 101. The term “lateral” is to be understood here in the sense of “parallel to the chip surface”.

[0064] We refer now to the two illustrated Hall sensor circuits 101 that are drawn in FIGS. 4A and 4B in the lower part of the circuit. Here again, the Hall sensor circuit 101 on the left is shown in a first clock phase PH1, and the Hall sensor circuit 101 on the right is shown in a second clock phase PH2. A switch 120 is drawn here purely schematically in order to symbolize the switching between the two clock phases PH1, PH2.

[0065] It can additionally be seen that in a first clock phase PH1, the Hall supply current 102 is guided between the first terminal 111 and the second terminal 112 positioned (here diagonally) opposite the Hall effect region at a 45° angle to a normal to the primary flat plane, drawn above to the right, of the semiconductor substrate, laterally through the Hall effect region. As can also be seen from the diagram shown in FIG. 1A, for an example {100} silicon semiconductor material such 45° angles correspond to the directions [100], [010], [100] or [010]. The Hall effect region, and thereby the Hall supply current 102 here have a first dependency on a mechanical stress of the semiconductor substrate.

[0066] The resistor arranged on the left to the outside in the Hall effect region, e.g. the resistor that extends in the [110] direction, exhibits a resistance change of:

δR[110]=−17.6 σ.sub.xx−31.2 σ.sub.yy+53.4 σ.sub.zz

[0067] The resistor arranged at the bottom in the Hall effect region, e.g. the resistor that extends in the [110] direction, exhibits a resistance change of:

δR[110]=−31.2 σ.sub.xx−17.6 σ.sub.yy+53.4 σ.sub.zz

[0068] The resistor arranged diagonally in the Hall effect region, e.g. the resistor that extends in the [010] direction, exhibits a resistance change of:

δR[010]=−24.4 σ.sub.xx24.4 σ.sub.yy+155.6 σ.sub.xy+53.4 σ.sub.zz

[0069] It can thus be seen that the diagonal resistor, e.g. the resistor extending in the [010] direction has the respective mean value of the normal stress components σ.sub.xx, σ.sub.yy and σ.sub.zz of the left-hand resistor and of the bottom resistor, plus an additional shear stress component σ.sub.xy in the diagonal direction, e.g. in the [010] direction.

[0070] The same applies to the second clock phase PH2, wherein here the arithmetic sign of the additional shear stress component σ.sub.xy is reversed in the diagonal direction. From this it follows that the diagonal resistance here is rotated in comparison with the first clock phase PH1 through 90°, so that the Hall supply current runs in the opposite direction, e.g. in the [100] direction.

[0071] For the first clock phase PH1, during which the Hall supply current flows in the [010] direction (which is specified here by definition as)+45° the following effective sum thus results for the total resistance change:

R.sup.n.sub.Hall+45°˜24.4%/GPa×(σ.sub.xx+σ.sub.yy)+k×155%/GPa×(σ.sub.xy)+53%/GPa×(σ.sub.zz)

[0072] or, for the second clock phase PH2, with a negative arithmetic sign:

R.sup.n.sub.Hall−45°˜24.4%/GPa×(σ.sub.xx+σ.sub.yy)−k×155%/GPa×(σ.sub.xy)+53%/GPa×(σ.sub.zz)

[0073] The factor k is a weighting factor resulting from the proportional contributions of resistance components that are vertical and horizontal to the diagonal in the Hall plate model.

[0074] This Hall sensor circuit 101 is also illustrated again in FIG. 5A. FIG. 5B on the other hand shows a semiconductor circuit arrangement with a Hall sensor circuit 101, or a horizontal

[0075] Hall plate 101, that is rotated through 45° with respect to the horizontal Hall plate 101 shown in FIG. 5A.

[0076] In FIG. 5A the Hall supply current 102 is guided laterally through the Hall effect region during a first clock phase PH1 in a direction at +45° with respect to a normal to the primary flat plane, e.g., in the case of a {100} silicon substrate in the [010] direction. In a second clock phase PH2, the Hall supply current 102 is then guided laterally through the Hall effect region in a direction at −45° with respect to a normal to the primary flat plane, e.g., in the case of a {100} silicon substrate in the [100] direction.

[0077] FIG. 5B shows a Hall sensor circuit 101, or a horizontal Hall plate 101, that is rotated through 45° with respect to the horizontal Hall plate 101 shown in FIG. 5A. In FIG. 6B the Hall supply current 102 is guided laterally through the Hall effect region during a first clock phase PHI in a direction at 0° with respect to a normal to the primary flat plane, e.g., in the case of a {100} silicon substrate in the [110] direction. In a second clock phase PH2, the Hall supply current 102 is then guided laterally through the Hall effect region in a direction at 90° with respect to a normal to the primary flat plane, e.g., in the case of a {100} silicon substrate in the [110] direction.

[0078] The flow of the Hall supply current 102 generates an electrical voltage in the Hall effect region of the integrated Hall sensor circuit 101. This electrical voltage can be accessed in the form of an electrical voltage signal at, for example, two of the total of four terminals 111, 112, 113, 114. An electrical voltage signal in the form of a Hall output voltage V.sub.Hallout can, for example, be accessed at the two terminals at which the Hall supply current 102 is not fed in. On the other hand, an electrical voltage signal in the form of a Hall bias voltage V.sub.Hallbias can be accessed at the terminals at which the Hall supply current 102 is fed in.

[0079] A first voltage signal V.sub.Hallout(PH.sub.spin1) or V.sub.Hallbias(PH.sub.spin1) can accordingly be accessed in the first clock phase PH1, and a second voltage signal V.sub.Hallout(PH.sub.spin2) or V.sub.Hallbias(PH.sub.spin2) can accordingly be accessed in the second clock phase PH2. The first voltage signal V.sub.Hallout(PH.sub.spin1) or V.sub.Hallbias(PH.sub.spin1) has a first dependency on a mechanical stress of the semiconductor substrate, and the second voltage signal V.sub.Hallout(PH.sub.spin2) or V.sub.Hallbias(PH.sub.spin2) has a different, second dependency on a mechanical stress of the semiconductor substrate.

[0080] Expressed more generally, the Hall sensor circuit 101 according to the subject matter described herein, is configured in order, during a first clock phase PH.sub.spin1 to guide a Hall supply current 102 between the first terminal 111 and the opposite, second terminal 112 at a first angle (Di to a normal to a primary flat plane of the semiconductor substrate, laterally through a Hall effect region, and to generate a first electrical voltage signal V.sub.Hallout(PH.sub.spin1) or V.sub.Hallbias(PH.sub.spin1) in the Hall effect region, wherein the first electrical voltage signal V.sub.Hallout(PH.sub.spin1) or V.sub.Hallbias(PH.sub.spin1) has a first dependency on a mechanical stress of the semiconductor substrate. In the case of FIG. 5A, the first angle is Φ.sub.1=+45°, and in the case of FIG. 5B the first angle is Φ.sub.1=0°.

[0081] The Hall sensor circuit 101 is furthermore configured to guide a Hall supply current 102 between the third terminal 113 and the opposite, fourth terminal 114 at a second angle Φ.sub.2 that is orthogonal to the first angle Φ.sub.1, laterally through the Hall effect region during a second clock phase PH.sub.spin2, and to generate a second electrical voltage signal V.sub.Hallout(PH.sub.spin2) or V.sub.Hallbias(PH.sub.spin2) in the Hall effect region, wherein the second electrical voltage signal V.sub.Hallout(PH.sub.spin2) or V.sub.Hallbias(PH.sub.spin2) has a second dependency on a mechanical stress of the semiconductor substrate. In the case of FIG. 5A, the second angle is Φ.sub.2=−45°, and in the case of FIG. 5B the second angle is Φ.sub.2=90°.

[0082] According to the concept described herein the semiconductor circuit arrangement 100 is furthermore configured to ascertain a specific mechanical stress component, for example a normal stress component and/or a shear stress component, and to do so based on a combination of the first electrical voltage signal V.sub.Hallout(PH.sub.spin1) or V.sub.Hallbias(PH.sub.spin1) and of the second electrical voltage signal V.sub.Hallout(PH.sub.spin2) or V.sub.Hallbias(PH.sub.spin2).

[0083] This will be explained below in more detail with reference to the FIGS. 5A and 5B. In FIG. 5A a Hall output voltage V.sub.Hallout(PH.sub.spin1) or V.sub.Hallout(PH.sub.spin2) is accessed during both the first clock phase PH1 and the second clock phase PH2 at whichever terminals the Hall supply current 102 is not being fed in. This means that a first electrical voltage signal is accessed in the form of a first Hall output voltage V.sub.Hallout(PH.sub.spin1) at the third and fourth terminals 113, 114 during the first clock phase PH1, and a second electrical voltage signal in the form of a second Hall output voltage V.sub.Hallout(PH.sub.spin2) is accessed at the first and second terminals 111, 112 during the second clock phase PH2.

[0084] The first electrical voltage signal V.sub.Hallout(PH.sub.spin1) accessed during the first clock phase PH1 depends on the magnetic field component B.sub.z, as well as on what is known as the aggregate mechanical stress, e.g. on the sum of the normal stress components in the x and y directions (σ.sub.xx+σ.sub.yy), and on what is known as the difference mechanical stress, e.g. on the difference between the normal stress components in the x and y directions (σ.sub.xx−σ.sub.yy). The first electrical voltage signal V.sub.Hallout(PH.sub.spin1) is, however, independent of a shear stress component. The dependency on the normal stress component in the z direction σ.sub.zz is also negligible. The difference stress (σ.sub.xx−σ.sub.yy) here has a negative arithmetic sign during the first clock phase PH1, which means:

V.sub.Hallout(PH.sub.spin1)=f(B.sub.z, (σ.sub.xx+σ.sub.yy), −(σ.sub.xx−σ.sub.yy)).

[0085] The first voltage signal V.sub.Hallout(PH.sub.spin1) thus accordingly has a first dependency on a mechanical stress of the semiconductor substrate.

[0086] The second electrical voltage signal V.sub.Hallout(PH.sub.spin2) accessed during the second clock phase PH2 also depends on the magnetic field component B.sub.z as well as on the aggregate mechanical stress, e.g. on the sum of the normal stress components in the x and y directions (σ.sub.xx+σ.sub.yy), and on the difference mechanical stress, e.g. on the difference between the normal stress components in the x and y directions (σ.sub.xx−σ.sub.yy). The second electrical voltage signal V.sub.Hallout(PH.sub.spin2) is also independent of a shear stress component, while the dependency on the normal stress component in the z direction σ.sub.zz is also negligible. The mechanical difference stress (σ.sub.xx−σ.sub.yy) here however has a positive arithmetic sign during the second clock phase PH2, meaning that:

V.sub.Hallout(PH.sub.spin2)=f(B.sub.z, (σ.sub.xx+σ.sub.yy), +(σ.sub.xx−σ.sub.yy)).

[0087] The second voltage signal V.sub.Hallout(PH.sub.spin2) thus accordingly has a second dependency on a mechanical stress of the semiconductor substrate.

[0088] According to the example implementation shown here in FIG. 5A, the combination of the two electrical voltage signals V.sub.Hallout(PH.sub.spin1) and V.sub.Hallout(PH.sub.spin2) explained previously can now be made by forming a difference. This means that the semiconductor circuit arrangement 100 can be configured to form a difference between the first voltage signal V.sub.Hallout(PH.sub.spin1) and the second voltage signal V.sub.Hallout(PH.sub.spin2), meaning that:

V.sub.Hallout(PH.sub.spin1)−V.sub.Hallout(PH.sub.spin2)=+×f(σ.sub.xx−σ.sub.yy).

[0089] It can be seen that both the normal stress component σ.sup.xy and the dependency on the magnetic field component B.sub.z cancel each other out here. What remains is the dependency on the difference mechanical stress σ.sub.xx−σ.sub.yy explained previously. A mechanical normal stress component, namely the difference mechanical stress σ.sup.xx−σ.sub.yy, can thus be ascertained in this form of implementation using forming the difference.

[0090] This also applies to the alternative shown in FIG. 5B, which means that using the variant shown in FIG. 5B a difference mechanical stress σ.sub.xx−σ.sub.yy can also be ascertained using forming a difference. The form of implementation shown in FIG. 5B however uses the Hall bias voltage V.sub.Hallbias for this purpose in place of the Hall output voltage V.sub.Hallout discussed previously. This means that in FIG. 5B the first voltage signal is accessed between the terminals in the form of the Hall bias voltage V.sub.Hallbias(PH.sub.spin1) during the first clock phase PH.sub.spin1, during which the Hall supply current 102 is also fed in, e.g. between the first terminal 111 and the second terminal 112. The second voltage signal is accessed between the terminals in the form of the Hall bias voltage V.sub.Hallbias(PH.sub.spin2) during the second clock phase Plispin2, during which the Hall supply current 102 is also fed in, e.g. between the third terminal 113 and the fourth terminal 114.

[0091] The first electrical voltage signal V.sub.Hallbias(PH.sub.spin1) accessed during the first clock phase PH1 depends on the magnetic field component B.sub.z as well as on the aggregate mechanical stress, e.g. on the sum of the normal stress components in the x and y directions (σ.sub.xx+σ.sub.yy), and on the difference mechanical stress, e.g. on the difference between the normal stress components in the x and y directions (σ.sub.xx−σ.sub.yy). There is, however, no dependency on a shear stress component. The dependency on a normal stress component in the z direction σ.sub.zz is also negligible. The difference stress (σ.sub.xx−σ.sub.yy) here has a positive arithmetic sign during the first clock phase PH1, which means:

V.sub.Hallbias(PH.sub.spin1)=f(B.sub.z, (σ.sub.xx+σ.sub.yy), +(σ.sub.xx−σ.sub.yy)).

[0092] The first voltage signal V.sub.Hallbias(PH.sub.spin1) thus accordingly has a first dependency on a mechanical stress of the semiconductor substrate.

[0093] The second electrical voltage signal V.sub.Hallbias(PH.sub.spin2) accessed during the second clock phase PH2 also depends on the magnetic field component B.sub.z as well as on the aggregate mechanical stress σ.sub.xx+σ.sub.yy and on the difference mechanical stress σ.sub.xx−σ.sub.yy. The mechanical difference stress σ.sub.xx−σ.sub.yy here however has a negative arithmetic sign during the second clock phase PH2, meaning that:

V.sub.Hallbias(PH.sub.spin2)=f(B.sub.z, (σ.sub.xx+σ.sub.yy), −(σ.sub.xx−σ.sub.yy)).

[0094] The second voltage signal V.sub.Hallbias(PH.sub.spin2) thus accordingly has a second dependency on a mechanical stress of the semiconductor substrate. The normal stress component in the z direction σ.sub.zz is, also here in this arrangement, again negligible both in the first clock phase PHI as well as in the second clock phase PH2.

[0095] According to the example implementation shown here in FIG. 5B, the combination of the two electrical voltage signals V.sub.Hallbias(PH.sub.spin1) and V.sub.Hallbias(PH.sub.spin2) explained previously can now also again be made by forming a difference. This means that the semiconductor circuit arrangement 100 can be configured to form a difference between the first voltage signal V.sub.Hallbias(PH.sub.spin1) and the second voltage signal V.sub.Hallbias(PH.sub.spin2), meaning that:

V.sub.Hallbias(PH.sub.spin1) V.sub.Hallbias(PH.sub.spin2)=+2×f(σ.sub.xx−σ.sub.yy).

[0096] Here again, both the normal stress component Ch.sub.y and the dependency on the magnetic field component B.sub.z cancel each other out. What remains is the dependency on the difference mechanical stress σ.sub.xx−σ.sub.yy explained previously. A mechanical normal stress component, namely the difference mechanical stress σ.sub.xx−σ.sub.yy, can thus be ascertained in this variant implementation, alternative to FIG. 5A, using forming the difference.

[0097] It has been recognized that the mechanical stress components ascertained using the Hall sensor circuit 101 can be used to compensate for a negative influence of the respective mechanical stress component on the parametric accuracy and/or parametric stability of a component that is arranged on the semiconductor substrate but is separate from the Hall sensor circuit 101 or of a further circuit arrangement integrated into the semiconductor substrate. This means that although the mechanical stress of the semiconductor substrate is measured using the Hall sensor circuit 101, the stress components ascertained can be used for the compensation of other components.

[0098] In the example implementations described with reference to FIGS. 5A and 5B, the difference stress σ.sub.xx−σ.sub.yy ascertained using the Hall sensor circuit 101 can be used to compensate for the parametric accuracy and/or parametric stability of other components, elements or integrated circuits that have a marked dependency on a difference stress.

[0099] As is shown in FIG. 5C, an analog or digital compensation of a frequency deviation of an on-chip oscillator 130 can, for example, be carried out. Alternatively or in addition, the sensitivity of a separate magnetic flux sensor 140 separate from the Hall sensor circuit 101 can, for example, be increased.

[0100] Two further forms of implementation of integrated Hall sensor circuits 101 are shown in FIGS. 6A and 6B. These forms of implementation can be employed in order to ascertain a shear stress component σ.sub.xy.

[0101] In FIG. 6A the Hall supply current 102 is guided laterally through the Hall effect region during a first clock phase PH1 in a direction at +45° with respect to a normal to the primary flat plane, e.g., in the case of a {100} silicon substrate in the [010] direction. In a second clock phase PH2, the Hall supply current 102 is then guided laterally through the Hall effect region in a direction at −45° with respect to a normal to the primary flat plane, e.g., in the case of a {100} silicon substrate in the [100] direction.

[0102] FIG. 6B shows a Hall sensor circuit 101, or a horizontal Hall plate 101, that is rotated through 45° with respect to the horizontal Hall plate 101 shown in FIG. 6A. In FIG. 6B the Hall supply current 102 is guided laterally through the Hall effect region during a first clock phase PH1 in a direction at 0° with respect to a normal to the primary flat plane, e.g., in the case of a {100} silicon substrate in the [110] direction. In a second clock phase PH2, the Hall supply current 102 is then guided laterally through the Hall effect region in a direction at 90° with respect to a normal to the primary flat plane, e.g., in the case of a {100} silicon substrate in the [110] direction.

[0103] The flow of the Hall supply current 102 here again also generates an electrical voltage in the Hall effect region of the integrated Hall sensor circuit 101. This electrical voltage can be accessed in the form of an electrical voltage signal at, for example, two of the total of four terminals 111, 112, 113, 114. An electrical voltage signal in the form of a Hall output voltage V.sub.Hallout can, for example, be accessed at the two terminals at which the Hall supply current 102 is not fed in. On the other hand, an electrical voltage signal in the form of a Hall bias voltage V.sub.Hallbias can be accessed at the terminals at which the Hall supply current 102 is fed in.

[0104] A first voltage signal V.sub.Hallout(PH.sub.spin1) or V.sub.Hallbias(PH.sub.spin1) can accordingly be accessed in the first clock phase PH1, and a second voltage signal V.sub.Hallout(PH.sub.spin2) or V.sub.Hallbias(PH.sub.spin2) can accordingly be accessed in the second clock phase PH2. The first voltage signal V.sub.Hallout(PH.sub.spin1) or V.sub.Hallbias(PH.sub.spin1) has a first dependency on a mechanical stress of the semiconductor substrate, and the second voltage signal V.sub.Hallout(PH.sub.spin2) or VHanms(PH.sub.spin2) has a different, second dependency on a mechanical stress of the semiconductor substrate.

[0105] Expressed more generally, the Hall sensor circuit 101 according to the subject matter described herein, is configured to guide a Hall supply current 102 between the first terminal 111 and the opposite, second terminal 112 at a first angle Φ.sub.1 to a normal to a primary flat plane of the semiconductor substrate, laterally through a Hall effect region during a first clock phase PH.sub.spin1, and to generate a first electrical voltage signal V.sub.Hallout(PH.sub.spin1) or V.sub.Hallbias(PH.sub.spin1) in the Hall effect region, wherein the first electrical voltage signal V.sub.Hallout(PH.sub.spin1) or V.sub.Hallbias(PH.sub.spin1) has a first dependency on a mechanical stress of the semiconductor substrate. In the case of FIG. 6A, the first angle is Φ.sub.1=+45°, and in the case of FIG. 6B the first angle is Φ.sub.1=0°.

[0106] The Hall sensor circuit 101 is furthermore configured to guide a Hall supply current 102 between the third terminal 113 and the opposite, fourth terminal 114 at a second angle Φ.sub.2 that is orthogonal to the first angle Φ.sub.1, laterally through the Hall effect region during a second clock phase PH.sub.spin2, and to generate a second electrical voltage signal V.sub.Hallout(PH.sub.spin2) or V.sub.Hallbias(PH.sub.spin2) in the Hall effect region, wherein the second electrical voltage signal V.sub.Hallout(PH.sub.spin2) or V.sub.Hallbias(PH.sub.spin2) has a second dependency on a mechanical stress of the semiconductor substrate. In the case of FIG. 6A, the second angle is Φ.sub.2=−45°, and in the case of FIG. 6B the second angle is Φ.sub.2=90°.

[0107] According to the example implementation illustrated in FIGS. 6A and 6B, the semiconductor circuit arrangement 100 is furthermore configured to ascertain a specific mechanical stress component, in this case a shear stress component, and to do so based on a combination of the first electrical voltage signal V.sub.Hallout(PH.sub.spin1) or VHalltnas(PH.sub.spin1) and of the second electrical voltage signal V.sub.Hallout(PH.sub.spin2) or VHaublas(PH.sub.spin2).

[0108] In FIG. 6A a Hall bias voltage V.sub.Hallbias(PH.sub.spin2) or V.sub.Hallbias(PH.sub.spin2) is accessed during both the first clock phase PHI and the second clock phase PH2 at whichever terminals the Hall supply current 102 is also being fed in. This means that a first electrical voltage signal is accessed in the form of a first Hall bias voltage V.sub.Hallbias(PH.sub.spin1) at the first terminal 111 and at the second terminal 112 during the first clock phase PH1, and a second electrical voltage signal in the form of a second Hall bias voltage V.sub.Hallbias(PH.sub.spin2) is accessed at the third terminal 113 and at the fourth terminal 114 during the second clock phase PH2.

[0109] The first electrical voltage signal V.sub.Hallbias(PH.sub.spin1) accessed during the first clock phase PH1 depends neither on the magnetic field component B.sub.z nor on the difference stress (σ.sub.xx−σ.sub.yy). It does, however, depend on the aggregate mechanical stress, e.g. on a sum of the normal stress components in the x and y directions (σ.sub.xx+σ.sub.yy) and on a normal mechanical stress component in the z direction, e.g. on the normal stress σ.sub.zz as well as on a mechanical shear stress σ.sub.xy. The mechanical shear stress component σ.sub.xy here has a positive arithmetic sign during the first clock phase PH1, which means:

V.sub.Hallbias(PH.sub.spin1)=f((σ.sub.xx+σ.sub.yy), +σ.sub.xy, σ.sub.zz).

[0110] The first voltage signal V.sub.Hallbias(PH.sub.spin1) thus accordingly has a first dependency on a mechanical stress of the semiconductor substrate.

[0111] The second electrical voltage signal V.sub.Hallbias(PH.sub.spin2) accessed during the second clock phase PH2 again depends neither on the magnetic field component B.sub.z nor on the difference stress (σ.sub.xx−σ.sub.yy). It does, however, once again depend on the aggregate mechanical stress, e.g. on a sum of the normal stress components in the x and y directions (σ.sub.xx+σ.sub.yy) and on a normal mechanical stress component in the z direction, e.g. on the normal stress σ.sup.zz as well as on a mechanical shear stress σ.sub.xy. The mechanical shear stress component σ.sub.xy here however has a negative arithmetic sign during the second clock phase PH2, which means:

V.sub.Hallbias(PH.sub.spin2)=f((σ.sub.xx+σ.sub.yy), −σ.sub.xy, σ.sub.zz).

[0112] The second voltage signal V.sub.Hallbias(PH.sub.spin2) thus accordingly has a second dependency on a mechanical stress of the semiconductor substrate.

[0113] According to the example implementation shown here in FIG. 6A, the combination of the two electrical voltage signals V.sub.Hallbias(PH.sub.spin1) and V.sub.Hallbias(PH.sub.spin2) explained previously can now be made by forming a difference. This means that the semiconductor circuit arrangement 100 can be configured to form a difference between the first voltage signal V.sub.Hallbias(PH.sub.spin1) and the second voltage signal V.sub.Hallbias(PH.sub.spin2), meaning that:

V.sub.Hallbias(PH.sub.spin1)−V.sub.Hallbias(PH.sub.spin2)=+2×f(σ.sub.xy).

[0114] It can be seen that both the normal stress component in the z direction σ.sub.zz as well as the dependency on the magnetic field component B.sub.z and the aggregate mechanical stress (σ.sub.xx+σ.sub.yy) cancel each other out. What remains is the dependency on the mechanical shear stress component σ.sub.xy explained previously. A mechanical shear stress component σ.sub.xy can thus be ascertained in this form of implementation using forming the difference.

[0115] This also applies to the alternative shown in FIG. 6B, which means that using the variant shown in FIG. 6B a mechanical shear stress component σ.sub.xy can also be ascertained using forming a difference. The form of implementation shown in FIG. 6B however uses the Hall output voltage V.sub.Hallout for this purpose in place of the Hall bias voltage V.sub.Hallbias discussed previously. This means that in FIG. 6B the first voltage signal is accessed between the terminals in the form of the Hall output voltage V.sub.Hallout(PH.sub.spin1) during the first clock phase PH.sub.spin1, during which the Hall supply current 102 is not being fed in, e.g. between the third terminal 113 and the fourth terminal 114. The second voltage signal is accessed between the terminals in the form of the Hall output voltage V.sub.Hallout(PH.sub.spin2) during the second clock phase PH.sub.spin2, during which the Hall supply current 102 is not being fed in, e.g. between the first terminal 111 and the second terminal 112.

[0116] The first electrical voltage signal V.sub.Hallout(PH.sub.spin1) accessed during the first clock phase PH1 depends neither on the magnetic field component B.sub.z nor on the difference stress σ.sub.xx−σ.sub.yy. It does, however, depend on the aggregate mechanical stress, e.g. on a sum of the normal stress components σ.sub.xx+σ.sub.yy and on a normal mechanical stress component in the z direction, e.g. on the normal stress σ.sub.zz as well as on a mechanical shear stress σ.sub.xy. The mechanical shear stress component σ.sub.xy here has a positive arithmetic sign during the first clock phase PH1, which means:

V.sub.Hallout(PH.sub.spin1)=f((σ.sub.xx+σ.sub.yy), +σ.sub.xy, σ.sub.zz).

[0117] The first voltage signal V.sub.Hallout(PH.sub.spin1) thus accordingly has a first dependency on a mechanical stress of the semiconductor substrate.

[0118] The second electrical voltage signal V.sub.Hallout(PH.sub.spin2) accessed during the second clock phase PH2 again depends neither on the magnetic field component B.sub.z nor on the difference stress σ.sub.xx−σ.sub.yy. It does, however, again also depend on the aggregate mechanical stress, e.g. on a sum of the normal stress components σ.sub.xx+σ.sub.yy and on a normal mechanical stress component in the z direction, e.g. on the normal stress azz as well as on a mechanical shear stress σ.sub.xy. The mechanical shear stress component σ.sub.xy here however has a negative arithmetic sign during the second clock phase PH2, which means:

V.sub.Hallout(PH.sub.spin2)=f((σ.sub.xx+σ.sub.yy), −σ.sub.xy, σ.sub.zz).

[0119] The second voltage signal V.sub.Hallout(PH.sub.spin2) thus accordingly has a second dependency on a mechanical stress of the semiconductor substrate.

[0120] According to the example implementation shown here in FIG. 6B, the combination of the two electrical voltage signals V.sub.Hallout(PH.sub.spin1) and V.sub.Hallout(PH.sub.spin2) explained previously can now also again be made by forming a difference. This means that the semiconductor circuit arrangement 100 can be configured to form a difference between the first voltage signal V.sub.Hallout(PH.sub.spin1) and the second voltage signal V.sub.Hallout(PH.sub.spin2), meaning that:

V.sub.Hallout(PH.sub.spin1)−V.sub.Hallout(PH.sub.spin2)=+2×f(σ.sub.xy).

[0121] Here again, both the normal stress component in the z direction σ.sub.zz as well as the dependency on the magnetic field component B.sub.z and the aggregate mechanical stress (σ.sub.xx+Σ.sub.yy) cancel each other out. What remains is the dependency on the mechanical shear stress component σ.sub.xy explained previously. In this variant implementation, which is alternative to that of FIG. 6A, a mechanical shear stress component σ.sub.xy can thus be ascertained using forming the difference.

[0122] It has been recognized that the mechanical stress components ascertained using the Hall sensor circuit 101 can be used to compensate for a negative influence of the respective mechanical stress component on the parametric accuracy and/or parametric stability of a component that is arranged on the semiconductor substrate but is separate from the Hall sensor circuit 101 or of a further circuit arrangement integrated into the semiconductor substrate. This means that although the mechanical stress of the semiconductor substrate is measured using the Hall sensor circuit 101, the stress component ascertained (here: shear stress σ.sub.xy) can be used for the compensation of other components.

[0123] In the example implementations described with reference to FIGS. 6A and 6B, the shear stress σ.sub.xy ascertained using the Hall sensor circuit 101 can be used to compensate for the parametric accuracy and/or parametric stability of other components, elements or integrated circuits that have a marked dependency on a shear stress σ.sub.xy.

[0124] As is shown in FIG. 6C, an analog or digital compensation for an orthogonality error of an angle sensor 150 based on the Hall effect with a horizontal Hall plate 151 and a vertical

[0125] Hall device 152, and separate from the Hall sensor circuit 101, can, for example, be carried out.

[0126] Two further forms of implementation of integrated Hall sensor circuits 101 are shown in FIGS. 7A and 7B. These forms of implementation can be employed to ascertain a normal stress component, and in particular what is known as an aggregate mechanical stress (σ.sub.xx+σ.sub.yy).

[0127] In FIG. 7A the Hall supply current 102 is guided laterally through the Hall effect region during a first clock phase PH1 in a direction at +45° with respect to a normal to the primary flat plane, e.g., in the case of a {100} silicon substrate in the [010] direction. In a second clock phase PH2, the Hall supply current 102 is then guided laterally through the Hall effect region in a direction at −45° with respect to a normal to the primary flat plane, e.g., in the case of a {100} silicon substrate in the [100] direction.

[0128] FIG. 7B shows a Hall sensor circuit 101, or a horizontal Hall plate 101, that is rotated through 45° with respect to the horizontal Hall plate 101 shown in FIG. 7A. In FIG. 7B the Hall supply current 102 is guided laterally through the Hall effect region during a first clock phase PHI in a direction at 0° with respect to a normal to the primary flat plane, e.g., in the case of a {100} silicon substrate in the [110] direction. In a second clock phase PH2, the Hall supply current 102 is then guided laterally through the Hall effect region in a direction at 90° with respect to a normal to the primary flat plane, e.g., in the case of a {100} silicon substrate in the [110] direction.

[0129] The flow of the Hall supply current 102 here again also generates an electrical voltage in the Hall effect region of the integrated Hall sensor circuit 101. This electrical voltage can be accessed in the form of an electrical voltage signal at, for example, two of the total of four terminals 111, 112, 113, 114. An electrical voltage signal in the form of a Hall output voltage V.sub.Hallout can, for example, be accessed at the two terminals at which the Hall supply current 102 is not fed in. On the other hand, an electrical voltage signal in the form of a Hall bias voltage V.sub.Hallbias can be accessed at the terminals at which the Hall supply current 102 is fed in.

[0130] A first voltage signal V.sub.Hallout(PH.sub.spin1) or V.sub.Hallbias(PH.sub.spin1) can accordingly be accessed in the first clock phase PH1, and a second voltage signal V.sub.Hallout(PH.sub.spin2) or V.sub.Hallbias(PH.sub.spin2) can accordingly be accessed in the second clock phase PH2. The first voltage signal V.sub.Hallout(PH.sub.spin1) or V.sub.Hallbias(PH.sub.spin1) has a first dependency on a mechanical stress of the semiconductor substrate, and the second voltage signal V.sub.Hallout(PH.sub.spin2) or VHanias(PH.sub.spin2) has a different, second dependency on a mechanical stress of the semiconductor substrate.

[0131] Expressed more generally, the Hall sensor circuit 101 according to the subject matter described herein, is configured to guide a Hall supply current 102 between the first terminal 111 and the opposite, second terminal 112 at a first angle Φ.sub.1 to a normal to a primary flat plane of the semiconductor substrate, laterally through a Hall effect region during a first clock phase PH.sub.spin1, and to generate a first electrical voltage signal V.sub.Hallout(PH.sub.spin1) or V.sub.Hallbias(PH.sub.spin1) in the Hall effect region, wherein the first electrical voltage signal V.sub.Hallout(PH.sub.spin1) or VHanbias(PHspird) has a first dependency on a mechanical stress of the semiconductor substrate. In the case of FIG. 7A, the first angle is Φ.sub.1=+45°, and in the case of FIG. 7B the first angle is Φ.sub.1=0°.

[0132] The Hall sensor circuit 101 is furthermore configured to guide a Hall supply current 102 between the third terminal 113 and the opposite, fourth terminal 114 at a second angle Φ.sub.2 that is orthogonal to the first angle Φ.sub.1, laterally through the Hall effect region during a second clock phase PH.sub.spin2, and to generate a second electrical voltage signal V.sub.Hallout(PH.sub.spin2) or V.sub.Hallbias(PH.sub.spin2) in the Hall effect region, wherein the second electrical voltage signal V.sub.Hallout(PH.sub.spin2) or V.sub.Hallbias(PH.sub.spin2) has a second dependency on a mechanical stress of the semiconductor substrate. In the case of FIG. 7A, the second angle is Φ.sub.2=−45°, and in the case of FIG. 7B the second angle is Φ.sub.2=90°.

[0133] According to the example implementation illustrated in FIGS. 7A and 7B, the semiconductor circuit arrangement 100 is furthermore configured to ascertain a specific mechanical stress component, in this case an aggregate mechanical stress, e.g. the sum of the normal stress components in the x and y directions (σ.sub.xx+σ.sub.yy), and to do so based on a combination of the first electrical voltage signal V.sub.Hallout(PH.sub.spin1) or V.sub.Hallbias(PH.sub.spin1) and of the second electrical voltage signal V.sub.Hallout(PH.sub.spin2) or V.sub.Hallbias(PH.sub.spin2).

[0134] In FIG. 7A a Hall bias voltage V.sub.Hallbias(PH.sub.spin1) or V.sub.Hallbias(PH.sub.spin2) is accessed during both the first clock phase PHI and the second clock phase PH2 at whichever terminals the Hall supply current 102 is also being fed in. This means that a first electrical voltage signal is accessed in the form of a first Hall bias voltage V.sub.Hallbias(PH.sub.spin1) at the first terminal 111 and at the second terminal 112 during the first clock phase PH1, and a second electrical voltage signal in the form of a second Hall bias voltage V.sub.Hallbias(PH.sub.spin2) is accessed at the third terminal 113 and at the fourth terminal 114 during the second clock phase PH2.

[0135] The first electrical voltage signal V.sub.Hallbias(PH.sub.spin1) accessed during the first clock phase PH1 depends neither on the magnetic field component B.sub.z nor on the difference stress (σ.sub.xx−σ.sub.yy). It does, however, depend on the aggregate mechanical stress, e.g. on a sum of the normal stress components in the x and y directions (σ.sub.xx+σ.sub.yy) and on a normal mechanical stress component in the z direction, e.g. on the normal stress Σ.sub.zz as well as on a mechanical shear stress σ.sub.xy. The mechanical shear stress component σ.sub.xy here has a positive arithmetic sign during the first clock phase PH1, which means:

V.sub.Hallbias(PH.sub.spin1)=f((σ.sub.xx+σ.sub.yy), +σ.sub.xy, σ.sub.zz).

[0136] The first voltage signal V.sub.Hallbias(PH.sub.spin1) thus accordingly has a first dependency on a mechanical stress of the semiconductor substrate.

[0137] The second electrical voltage signal V.sub.Hallbias(PH.sub.spin2) accessed during the second clock phase PH2 again depends neither on the magnetic field component B.sub.z nor on the difference stress (σ.sub.xx−σ.sub.yy). It does, however, once again depend on the aggregate mechanical stress, e.g. on a sum of the normal stress components in the x and y directions (σ.sub.xx+σ.sub.yy) and on a normal mechanical stress component in the z direction, e.g. on the normal stress σ.sub.zz as well as on a mechanical shear stress σ.sub.xy. The mechanical shear stress component σ.sub.xy here however has a negative arithmetic sign during the second clock phase PH2, which means:

V.sub.Hallbias(PH.sub.spin2)=f((σ.sub.xx+σ.sub.yy), −σ.sub.xy, σ.sub.zz).

[0138] The second voltage signal V.sub.Hallbias(PH.sub.spin2) thus accordingly has a second dependency on a mechanical stress of the semiconductor substrate.

[0139] According to the example implementation shown here in FIG. 7A, the combination of the two electrical voltage signals V.sub.Hallbias(PH.sub.spin1) and V.sub.Hallbias(PH.sub.spin2) explained previously can now be made by forming a sum or an average. This means that the semiconductor circuit arrangement 100 can be configured to form a sum or an average of the first voltage signal V.sub.Hallbias(PH.sub.spin1) and the second voltage signal V.sub.Hallbias(PH.sub.spin2), meaning that:

(V.sub.Hallbias(PH.sub.spin1)+V.sub.Hallbias(PH.sub.spin2))/2=f(σ.sub.xx+σ.sub.yy).

[0140] It can be seen that both the normal stress component in the z direction σ.sub.zz as well as the dependency on the magnetic field component B.sub.z and on the difference mechanical stress (σ.sub.xx−σ.sub.yy) cancel each other out. The dependency on the previously explained aggregate mechanical stress, e.g. the sum of the normal stress components in the x and y directions (σ.sub.xx+σ.sub.yy) remains. A mechanical normal stress component (σ.sub.xx+σ.sub.yy) can thus be ascertained in this form of implementation using forming the sum or average.

[0141] This also applies to the alternative shown in FIG. 7B, which means that using the variant shown in FIG. 7B a normal mechanical stress component, and in particular the aggregate stress (σ.sub.xx+σ.sub.yy), can also be ascertained using forming a sum or an average. A Hall bias voltage V.sub.Hallbias can likewise be used for this purpose in the form of implementation shown in FIG. 7B. This means that in FIG. 7B the first voltage signal is accessed between the terminals in the form of the Hall bias voltage V.sub.Hallbias(PH.sub.spin1) during the first clock phase PH.sub.spin1, during which the Hall supply current 102 is fed in, e.g. between the first terminal 111 and the second terminal 112. The second voltage signal is also accessed between the terminals in the form of the Hall bias voltage V.sub.Hallbias(PH.sub.spin2) during the second clock phase PH.sub.spin2, during which the Hall supply current 102 is fed in, e.g. between the third terminal 113 and the fourth terminal 114.

[0142] The first electrical voltage signal V.sub.Hallbias(PH.sub.spin1) accessed during the first clock phase PHI depends neither on the magnetic field component B.sub.z nor on the mechanical shear stress component σ.sub.xy. It does, however, depend on the aggregate mechanical stress, e.g. on a sum of the normal stress components in the x and y directions (σ.sub.xx+σ.sub.yy), on the difference mechanical stress, e.g. on a difference between the normal stress components in the x and y directions (σ.sub.xx−σ.sub.yy), as well as on a mechanical normal stress component in the z direction, e.g. on the normal stress σ.sub.zz. The difference mechanical stress (σ.sub.xx−σ.sub.yy) here has a positive arithmetic sign during the first clock phase PH1, which means:

V.sub.Hallbias(PH.sub.spin1)=f((σ.sub.xx+σ.sub.yy), +(σ.sub.xx−σ.sub.yy), σ.sub.zz).

[0143] The first voltage signal V.sub.Hallbias(PH.sub.spin1) thus accordingly has a first dependency on a mechanical stress of the semiconductor substrate.

[0144] The second electrical voltage signal V.sub.Hallbias(PH.sub.spin2) accessed during the second clock phase PH2 likewise depends neither on the magnetic field component B.sub.z nor on the mechanical shear stress component σ.sub.xy. It does, however, depend on the aggregate mechanical stress, e.g. on a sum of the normal stress components in the x and y directions (σ.sub.xx+σ.sub.yy), on the difference mechanical stress, e.g. on a difference between the normal stress components in the x and y directions (σ.sub.xx−σ.sub.yy), as well as on a mechanical normal stress component in the z direction, e.g. on the normal stress azz. The difference mechanical stress (σ.sub.xx−σ.sub.yy) here however has a negative arithmetic sign during the second clock phase PH2, which means:

V.sub.Hallbias(PH.sub.spin2)=f((σ.sub.xx+σ.sub.yy), −(σ.sub.xx−σ.sub.yy), σ.sub.zz).

[0145] The second voltage signal V.sub.Hallbias(PH.sub.spin2) thus accordingly has a second dependency on a mechanical stress of the semiconductor substrate.

[0146] According to the example implementation shown here in FIG. 7B, the combination of the two electrical voltage signals V.sub.Hallbias(PH.sub.spin1) and V.sub.Hallbias(PH.sub.spin2) explained previously can now once again be made by forming a sum or an average. This means that the semiconductor circuit arrangement 100 can be configured to form a sum or an average of the first voltage signal V.sub.Hallbias(PH.sub.spin1) and the second voltage signal V.sub.Hallbias(PH.sub.spin2), meaning that:

(V.sub.Hallbias(PH.sub.spin1) V.sub.Hallbias(PH.sub.spin2))/2=f(σ.sub.xx+σ.sub.yy).

[0147] Here again, both the normal stress component in the z direction σ.sub.zz as well as the dependency on the magnetic field component B.sub.z and on the difference mechanical stress (σ.sub.xx−σ.sub.yy) cancel each other out. The dependency on the previously explained aggregate mechanical stress, e.g. the sum of the normal stress components in the x and y directions (σ.sub.xx+σ.sub.yy) remains. A mechanical normal stress component (σ.sub.xx+σ.sub.yy) can thus be ascertained in this form of implementation using forming the sum or average.

[0148] It has been recognized that the mechanical stress component ascertained using the Hall sensor circuit 101 can be used to compensate for a negative influence of the respective mechanical stress component on the parametric accuracy and/or parametric stability of a component that is arranged on the semiconductor substrate but is separate from the Hall sensor circuit 101 or of a further circuit arrangement integrated into the semiconductor substrate. This means that although the mechanical stress of the semiconductor substrate is measured using the Hall sensor circuit 101, the stress component ascertained (here: aggregate stress (σ.sub.xx+σ.sub.yy))can be used for the compensation of other components.

[0149] In the example implementations described with reference to FIGS. 7A and 7B, the aggregate stress (σ.sub.xx+σ.sub.yy) ascertained using the Hall sensor circuit 101 can be used to compensate for the parametric accuracy and/or parametric stability of other components, elements or integrated circuits that have a marked dependency on an aggregate stress (axx +Ciyy)

[0150] As is shown in FIG. 7C, an analog or digital compensation of a sensitivity deviation of a separate horizontal Hall plate 160 can, for example, be carried out, e.g. the sensitivity, that is dependent on the aggregate stress, of the separate Hall plate 160 can be increased.

[0151] Two further forms of implementation of integrated Hall sensor circuits 101 are shown in FIGS. 8A and 8B. These forms of implementation can be employed to measure a magnetic field component B.sub.z and, in addition, to ascertain a mechanical stress component. In the form of implementation shown in FIG. 8A, a normal stress component and, in particular, what is known as an aggregate mechanical stress, e.g. the sum of the normal stress components in the x and y directions (σ.sub.xx+σ.sub.yy) can, for example, be ascertained. In the form of implementation shown in FIG. 8B, a shear stress component σ.sub.xy can, for example, be ascertained.

[0152] In FIG. 8A the Hall supply current 102 is guided laterally through the Hall effect region during a first clock phase PH1 in a direction at +45° with respect to a normal to the primary flat plane, e.g., in the case of a {100} silicon substrate in the [010] direction. In a second clock phase PH2, the Hall supply current 102 is then guided laterally through the Hall effect region in a direction at −45° with respect to a normal to the primary flat plane, e.g., in the case of a {100} silicon substrate in the [100] direction.

[0153] FIG. 8B shows a Hall sensor circuit 101, or a horizontal Hall plate 101, that is rotated through 45° with respect to the horizontal Hall plate 101 shown in FIG. 8A. In FIG. 8B the Hall supply current 102 is guided laterally through the Hall effect region during a first clock phase PH1 in a direction at 0° with respect to a normal to the primary flat plane, e.g., in the case of a {100} silicon substrate in the [110] direction. In a second clock phase PH2, the Hall supply current 102 is then guided laterally through the Hall effect region in a direction at 90° with respect to a normal to the primary flat plane, e.g., in the case of a {100} silicon substrate in the [110] direction.

[0154] The flow of the Hall supply current 102 here again also generates an electrical voltage in the Hall effect region of the integrated Hall sensor circuit 101. This electrical voltage can be accessed in the form of an electrical voltage signal at, for example, two of the total of four terminals 111, 112, 113, 114. An electrical voltage signal in the form of a Hall output voltage V.sub.Hallout can, for example, be accessed at the two terminals at which the Hall supply current 102 is not fed in. On the other hand, an electrical voltage signal in the form of a Hall bias voltage V.sub.Hallbias can be accessed at the terminals at which the Hall supply current 102 is fed in.

[0155] A first voltage signal V.sub.Hallout(PH.sub.spin1) or V.sub.Hallbias(PH.sub.spin1) can accordingly be accessed in the first clock phase PH1, and a second voltage signal V.sub.Hallout(PH.sub.spin2) or V.sub.Hallbias(PH.sub.spin2) can accordingly be accessed in the second clock phase PH2. The first voltage signal V.sub.Hallout(PH.sub.spin1) or V.sub.Hallbias(PH.sub.spin1) has a first dependency on a mechanical stress of the semiconductor substrate, and the second voltage signal V.sub.Hallout(PH.sub.spin2) or V.sub.Hallbias(PH.sub.spin2) has a different, second dependency on a mechanical stress of the semiconductor substrate.

[0156] Expressed more generally, the Hall sensor circuit 101 according to the subject matter described herein, is configured to guide a Hall supply current 102 between the first terminal 111 and the opposite, second terminal 112 at a first angle Φ.sub.1 to a normal to a primary flat plane of the semiconductor substrate, laterally through a Hall effect region during a first clock phase PH.sub.spin1, and to generate a first electrical voltage signal V.sub.Hallout(PH.sub.spin1) or V.sub.Hallbias(PH.sub.spin1) in the Hall effect region, wherein the first electrical voltage signal V.sub.Hallout(PH.sub.spin1) or V.sub.Hallbias(PH.sub.spin1) has a first dependency on a mechanical stress of the semiconductor substrate. In the case of FIG. 8A, the first angle is Φ.sub.1=+45°, and in the case of FIG. 8B the first angle is Φ.sub.1=0°.

[0157] The Hall sensor circuit 101 is furthermore configured to guide a Hall supply current 102 between the third terminal 113 and the opposite, fourth terminal 114 at a second angle Φ.sub.2 that is orthogonal to the first angle Φ.sub.1, laterally through the Hall effect region during a second clock phase PH.sub.spin2, and to generate a second electrical voltage signal V.sub.Hallout(PH.sub.spin2) or V.sub.Hallbias(PH.sub.spin2) in the Hall effect region, wherein the second electrical voltage signal V.sub.Hallout(PH.sub.spin2) or V.sub.Hallbias(PH.sub.spin2) has a second dependency on a mechanical stress of the semiconductor substrate. In the case of FIG. 8A, the second angle is Φ.sub.2=−45°, and in the case of FIG. 8B the second angle is Φ.sub.2=90°.

[0158] According to the example implementation illustrated in FIG. 8A, the semiconductor circuit arrangement 100 is furthermore configured to ascertain a specific mechanical stress component, in this case an aggregate mechanical stress, (σ.sub.xx+σ.sub.yy), and to do so based on a combination of the first electrical voltage signal V.sub.Hallout(PH.sub.spin1) or V.sub.Hallbias(PH.sub.spin1) and of the second electrical voltage signal V.sub.Hallout(PH.sub.spin2) or V.sub.Hallbias(PH.sub.spin2). According to the example implementation illustrated in FIG. 8B, the semiconductor circuit arrangement 100 is configured to ascertain a specific mechanical stress component, in this case a mechanical shear stress σ.sub.xy, and to do so based on a combination of the first electrical voltage signal V.sub.Hallout(PH.sub.spin1) or V.sub.Hallbias(PH.sub.spin1) and of the second electrical voltage signal V.sub.Hallout(PH.sub.spin2) or V.sub.Hallbias(PH.sub.spin2).

[0159] In FIGS. 8A and 8B a Hall output voltage V.sub.Hallout(PH.sub.spin1) or V.sub.Hallout(PH.sub.spin2) is accessed in each case during both the first clock phase PH1 and the second clock phase PH2 at whichever terminals the Hall supply current 102 is not being fed in. This means that a first electrical voltage signal is accessed in the form of a first Hall output voltage V.sub.Hallout(PH.sub.spin1) at the third terminal 113 and at the fourth terminal 114 during the first clock phase PH1, and a second electrical voltage signal in the form of a second Hall output voltage V.sub.Hallout(PH.sub.spin2) is accessed at the first terminal 111 and at the second terminal 112 during the second clock phase PH2.

[0160] The first electrical voltage signal V.sub.Hallout(PH.sub.spin1) accessed during the first clock phase PH1 depends on the magnetic field component B.sub.z as well as on what is known as the aggregate mechanical stress, e.g. on the sum of the normal stress components in the x and y directions (crxx +cr.sub.yy), and on what is known as the difference mechanical stress, e.g. on the difference between the normal stress components in the x and y directions (σ.sub.xx−σ.sub.yy). The first electrical voltage signal V.sub.Hallout(PH.sub.spin1) is, however, independent of a shear stress component. The dependency on the normal stress component in the z direction σ.sub.zz is also negligible. The difference stress (σ.sub.xx−σ.sub.yy) here has a negative arithmetic sign during the first clock phase PH1, which means:

V.sub.Hallout(PH.sub.spin1)=f(B.sub.z, (σ.sub.xx+σ.sub.yy), −(σ.sub.xx−σ.sub.yy)).

[0161] The first voltage signal V.sub.Hallout(PH.sub.spin1) thus accordingly has a first dependency on a mechanical stress of the semiconductor substrate.

[0162] The second electrical voltage signal V.sub.Hallout(PH.sub.spin2) accessed during the second clock phase PH2 likewise depends on the magnetic field component B.sub.z as well as on the aggregate mechanical stress, e.g. on the sum of the normal stress components in the x and y directions (σ.sub.xx+σ.sub.yy), and on the difference mechanical stress, e.g. on the difference between the normal stress components in the x and y directions (σ.sub.xx−σ.sub.yy). The second electrical voltage signal V.sub.Hallout(PH.sub.spin2) is also independent of a shear stress component, while the dependency on the normal stress component in the z direction σ.sub.zz is also negligible. The mechanical difference stress (σ.sub.xx−σ.sub.yy) here however has a positive arithmetic sign during the second clock phase PH2, meaning that:

V.sub.Hallout(PH.sub.spin2)=f (B.sub.z, (σ.sub.xx+σ.sub.yy), +(σ.sub.xx−σ.sub.yy)).

[0163] The second voltage signal V.sub.Hallout(PH.sub.spin2) thus accordingly has a second dependency on a mechanical stress of the semiconductor substrate.

[0164] According to the example implementation shown here in FIG. 8A, the combination of the two electrical voltage signals V.sub.Hallout(PH.sub.spin1) and V.sub.Hallout(PH.sub.spin2) explained previously can now be made by forming a sum or an average. This means that the semiconductor circuit arrangement 100 can be configured to form a sum or an average of the first voltage signal V.sub.Hallout(PH.sub.spin1) and the second voltage signal V.sub.Hallout(PH.sub.spin2), meaning that:

(V.sub.Hallout(PH.sub.spin1) V.sub.Hallout(PH.sub.spin2))/2=f(B.sub.z, (σ.sub.xx+σ.sub.yy).

[0165] It can be seen that the difference stress (σ.sub.xx−σ.sub.yy) is canceled out. What remains is the dependency on the aggregate mechanical stress (σ.sub.xx+σ.sub.yy)) explained previously and on the magnetic field component B.sub.z. A mechanical normal stress component, namely the aggregate mechanical stress (σ.sub.xx+σ.sub.yy)), can thus be ascertained in this form of implementation using forming the sum or average.

[0166] Using the variant shown in FIG. 8B, a mechanical shear stress component σ.sub.xy can be ascertained using forming a sum or average. The Hall output voltage V.sub.Hallout can likewise be used for this purpose in the form of implementation shown in FIG. 8B. This means that in FIG. 8B again the first voltage signal is accessed between the terminals in the form of the Hall output voltage V.sub.Hallout(PH.sub.spin1) during the first clock phase PH.sub.spin1, during which the Hall supply current 102 is not being fed in, e.g. between the third terminal 113 and the fourth terminal 114. The second voltage signal is accessed between the terminals in the form of the Hall output voltage V.sub.Hallout(PH.sub.spin2) during the second clock phase PH.sub.spin2, during which the Hall supply current 102 is not being fed in, e.g. between the first terminal 111 and the second terminal 112.

[0167] The first electrical voltage signal V.sub.Hallout(PH.sub.spin1) accessed in the first clock phase PHI depends on the magnetic field component B.sub.z, on the aggregate stress, e.g. on a sum of the normal stress components (σ.sub.xx+σ.sub.yy), and on a shear stress component σ.sub.xy. It is, however, independent of the difference mechanical stress, e.g. on a difference of the normal stress components (σ.sub.xx−σ.sub.yy) and of a normal mechanical stress component in the z direction, e.g. of the normal stress σ.sub.zz. The mechanical shear stress component σ.sub.xy here has a negative arithmetic sign during the first clock phase PH1, which means:

V.sub.Hallout(PH.sub.spin1)=f(B.sub.z, (σ.sub.xx+σ.sub.yy), −σ.sub.xy).

[0168] The first voltage signal V.sub.Hallout(PH.sub.spin1) thus accordingly has a first dependency on a mechanical stress of the semiconductor substrate.

[0169] The second electrical voltage signal V.sub.Hallout(PH.sub.spin2) accessed in the second clock phase PH2 likewise depends on the magnetic field component Bz, on the aggregate stress, e.g. on a sum of the normal stress components (σ.sub.xx+σ.sub.yy), and on a shear stress component σ.sub.xy. It is, however, independent of the difference mechanical stress, e.g. on a difference of the normal stress components (σ.sub.xx−σ.sub.yy) and of a normal mechanical stress component in the z direction, e.g. of the normal stress σ.sub.zz. The mechanical shear stress component σ.sub.xy here however has a positive arithmetic sign during the first clock phase PH1, which means:

V.sub.Hallout(PH.sub.spin1)=f (B.sub.z, (σ.sub.xx+σ.sub.yy), +σ.sub.yy).

[0170] The second voltage signal V.sub.Hallout(PH.sub.spin2) thus accordingly has a second dependency on a mechanical stress of the semiconductor substrate.

[0171] According to the example implementation shown here in FIG. 8B, the combination of the two electrical voltage signals V.sub.Hallout(PH.sub.spin1) and V.sub.Hallout(PH.sub.spin2) explained previously can now once again be made by forming a sum or an average. This means that the semiconductor circuit arrangement 100 can be configured to form a sum or an average of the first voltage signal V.sub.Hallout(PH.sub.spin1) and the second voltage signal V.sub.Hallout(PH.sub.spin2), meaning that:

V.sub.Hallout(PH.sub.spin1) V.sub.Hallout(PH.sub.spin2)=f(B.sub.z, σ.sub.xy).

[0172] The difference stress (σ.sub.xx−σ.sub.yy) here again cancels out. What remains is the dependency on the mechanical shear stress component σ.sub.xy explained previously and on the magnetic field component B.sub.z. A mechanical shear stress component σ.sub.xy can thus be ascertained in this form of implementation using forming the sum or average.

[0173] As is shown in FIG. 8C, this can be used to measure a magnetic field component B.sub.z using the Hall sensor circuit 101, and to compensate for an initial offset error.

[0174] FIG. 9 shows a schematic block diagram of a method according to the subject matter described herein.

[0175] In block 901 a Hall supply current 102 is applied during a first clock phase PH.sub.spin1, this being done between the first terminal 111 and the opposite, second terminal 112 in order to guide the Hall supply current 102 at a first angle Φ.sub.1 (e.g. Φ.sub.1=+45° or Φ.sub.1=0°) to a normal to a primary flat plane of the semiconductor substrate, laterally through a Hall effect region of the Hall sensor circuit 101, wherein the Hall supply current 102 generates a first electrical voltage signal V.sub.Hallout(PH.sub.spin1) or V.sub.Hallbias(PH.sub.spin1) in the Hall effect region, wherein the first electrical voltage signal V.sub.Hallout(PH.sub.spin1) or V.sub.Hallbias(PH.sub.spin1) has a first dependency on a mechanical stress of the semiconductor substrate.

[0176] In block 902 a Hall supply current 102 is applied during a second clock phase PH.sub.spin2, this being done between the third terminal 113 and the opposite, fourth terminal 114 in order to guide the Hall supply current 102 at a second angle .sup.41)2 (e.g. T2 =-45° or .sup.41)2 =)90° that is orthogonal to the first angle Φ.sub.1 (e.g. Φ.sub.1=+45° or Φ.sub.1=0°, laterally through the Hall effect region of the Hall sensor circuit 101, wherein the Hall supply current 102 generates a second electrical voltage signal V.sub.Hallout(PH.sub.spin2) or V.sub.Hallbias(PH.sub.spin2) in the Hall effect region, wherein the second electrical voltage signal V.sub.Hallout(PH.sub.spin2) or V.sub.Hallbias(PH.sub.spin2) has a second dependency on a mechanical stress of the semiconductor substrate.

[0177] In block 903 a specific mechanical stress component is ascertained, this being done based on a combination of the first electrical voltage signal (V.sub.Hallout(PH.sub.spin1) or V.sub.Hallbias(PH.sub.spin1)) and of the second electrical voltage signal (V.sub.Hallout(PH.sub.spin2) or V.sub.Hallbias(PH.sub.spin2)).

[0178] According to the subject matter described herein, the lateral Hall plate 101 or the integrated Hall sensor circuit 101 can thus be employed both for the measurement of a magnetic field as well as for the measurement of stress. The results of the stress measurement can be used for the compensation of parametric inaccuracies of other components or circuits.

[0179] Angle sensors based on the Hall effect can, for example, have an orthogonality error resulting from shear stress, which can be compensated for by compensating the shear stress. Additional on-chip oscillators can have frequency deviations or frequency inaccuracies that can be traced back to difference mechanical stresses of in-plane stress components, e.g. to a difference between mechanical normal stress components in the x and y directions. A magnetic 3D sensor can have measurement inaccuracies that can be traced back to aggregate mechanical stresses of in-plane stress components, e.g. to a sum of mechanical normal stress components in the x and y directions.

[0180] The concept described herein can be summarized as follows: [0181] Multiple use of a horizontal Hall plate for the measurement of: [0182] a magnetic signal [0183] and additional mechanical stress components [0184] aggregate stress (σ.sub.xx+σ.sub.yy) [0185] difference stress (σ.sub.xx−σ.sub.yy) [0186] shear stress σ.sub.xy [0187] for compensation of the sensitivity of a horizontal Hall plate [0188] and/or for compensating the vertical Hall devices of an angle sensor or magnetic 3D sensor, [0189] and/or compensating for aggregate stress dependent, difference stress dependent or shear stress dependent [0190] on-chip oscillators [0191] magnetic current sensors [0192] other circuits (e.g. bandgaps) and sensors [0193] Carrying out measurements in one or a plurality of spinning phases of a horizontal Hall plate: [0194] in order to ascertain the difference [0195] in order to ascertain the sum (or mean value) of the measurements from different spinning phases [0196] Primary advantages: [0197] multiple use of one sensor for self-correction or for the correction of other sensors and/or circuits [0198] less chip area [0199] lower energy consumption [0200] increased precision of all on-chip circuits

[0201] The concept described herein can be used in particular for the purposes of a system calibration.

[0202] The example implementations described above only represent an exemplification of the principles of the subject matter described herein. It is obvious that modifications and variations of the arrangements and details described herein will be clear to other specialists. It is therefore intended that the concept described herein will only be restricted by the scope of protection of the following patent claims, and not by the specific details that have been presented here with reference to the description and the explanation of the example implementations.

[0203] Although some aspects have been described in connection with a device, it is clear that these aspects also represent a description of the corresponding method, so that a block or a component of a device is also to be understood as a corresponding method step or as a feature of a method step. Aspects that have been described in connection with a method step or as such a step analogously also represent a description of a corresponding block or detail or feature of a corresponding device.

[0204] Some or all of the method steps can be carried out by a hardware apparatus (or making use of a hardware apparatus), such as for example a microprocessor, a programmable computer, or an electronic circuit. In some example implementations, some or a plurality of the most important method steps can be carried out by such an apparatus.

[0205] Depending on specific implementations, example implementations can be implemented in hardware or in software or at least partially in hardware or at least partially in software. The implementation can be carried out making use of a digital storage medium, for example a floppy disk, a DVD, a Blu-ray disk, a CD, a ROM, a PROM, an EPROM, an EEPROM or a FLASH memory, a hard disk or another magnetic or optical store on which electronically readable control signals are stored that can or do interact together with a programmable computer system in such a way that the respective method is carried out. The digital storage medium can therefore be computer-readable.

[0206] Some example implementations thus comprise a data carrier that comprises electronically readable control signals that are capable of interacting with a programmable computer system in such a way that one of the methods described herein is carried out.

[0207] Example implementations can in general be implemented as a computer program product with program code, wherein the program code is effective in carrying out one of the methods when the computer program product is executed on a computer.

[0208] The program code can for example also be stored on a machine-readable carrier.

[0209] Other example implementations comprise the computer program for carrying out one of the methods described here, wherein the computer program is stored on a machine-readable carrier. In other words, an example implementation of the method described herein is thus a computer program that comprises program code for carrying out one of the methods described herein when the computer program is executed on a computer.

[0210] A further example implementation of the method described herein is thus a data carrier (or a digital storage medium or a computer-readable medium) on which the computer program for carrying out one of the methods described here is recorded. The data carrier or the digital storage medium or the computer-readable medium are typically tangible and/or not volatile.

[0211] A further example implementation of the method described herein is thus a data stream or a sequence of signals that represents or represent the computer program for carrying out one of the methods described herein. The data stream or the sequence of signals can for example be configured to be transferred over a data communication connection, for example over the Internet.

[0212] A further example implementation comprises a processing device, for example a computer or a programmable logic component, that is configured or adapted to carry out one of the methods described herein.

[0213] A further example implementation comprises a computer on which the computer program for carrying out one of the methods described herein is installed.

[0214] A further example implementation comprises a device or system that is configured to transmit a computer program for carrying out at least one of the methods described herein to a receiver. The transmission can for example take place electronically or optically. The receiver can for example be a computer, a mobile device, a storage device or a similar apparatus. The device or the system can for example comprise a data server for transmitting the computer program to the receiver.

[0215] In some example implementations, a programmable logic component (for example a field programmable gate array, an FPGA), can be used to carry out some or all of the functionalities of the methods described herein. In some example implementations, a field programmable gate array can interact with a microprocessor in order to carry out one of the methods described herein. In general, in some example implementations, the methods are carried out by an arbitrary hardware device. This can be a universally usable hardware such as a computer processor (CPU), or hardware specifically for the method, such as for example an ASIC.