Method of manufacturing array substrate, array substrate, and LCD panel

Abstract

The disclosure provides a method of manufacturing an array substrate, an array substrate, and a liquid crystal display (LCD) panel. A non-display area of the array substrate includes a substrate, an alignment mark, an insulating layer, a hydrophobic layer, and a black photo spacer (BSP) pattern. The hydrophobic layer is disposed on the insulating layer corresponding to the alignment mark. When a BSP material is coated, a thickness of a BSP layer on the hydrophobic layer is reduced, thereby effectively fixing a problem that it is difficult to recognize an alignment mark.

Claims

1. A method of manufacturing an array substrate, comprising following steps: Step 10: providing a substrate, and forming an alignment mark on the substrate; Step 20: forming an insulating layer on the substrate where the alignment mark is formed, coating a hydrophobic layer on the insulating layer corresponding to the alignment mark, and drying the hydrophobic layer; and Step 30: coating a black photo spacer (BSP) material on the insulating layer and the hydrophobic layer, and exposing, developing, and etching the BSP material to form a BSP pattern.

2. The method of claim 1, wherein the Step 10 further comprises: forming an active layer on the substrate, wherein the active layer comprises a first metal layer and a second metal layer, the alignment mark is formed from at least one of the first metal layer or the second metal layer, and the alignment mark is located in a non-display area of the substrate.

3. The method of claim 2, wherein the alignment mark is formed from the first metal layer.

4. The method of claim 2, wherein the alignment mark is formed from the second metal layer.

5. The method of claim 1, wherein in the Step 20, a material of the hydrophobic layer comprises polyethylene terephthalate.

6. The method of claim 5, wherein the process of coating the hydrophobic layer comprises an inkjet printing process, a spray coating process, a slit coating process, or a spin coating process.

7. The method of claim 5, wherein the hydrophobic layer is dried at a temperature ranging from 80° C. to 150° C.

8. The method of claim 1, wherein the Step 20 further comprises: forming a color filter layer before the insulating layer is formed, and forming a pixel electrode layer on the insulating layer after the insulating layer is formed, wherein the color filter layer and the pixel electrode layer are located in a display area of the substrate.

9. The method of claim 8, wherein a material of the pixel electrode layer comprises indium tin oxide.

10. The method of claim 8, wherein a material of the insulating layer comprises a composite comprising one or more of SiOx, SiNx, and SiON.

11. The method of claim 1, wherein in the Step 30, a film thickness of a BSP on the hydrophobic layer is less than a film thickness of a BSP on the insulating layer after the BSP material is coated so that an accurate alignment process is performed by recognizing the alignment mark during an exposure process.

12. The method of claim 11, wherein the BSP on the hydrophobic layer and the BSP on the insulating layer are connected.

13. The method of claim 11, wherein the BSP on the hydrophobic layer and the BSP on the insulating layer are disconnected.

14. The method of claim 1, wherein in the Step 30, a BSP is not located on the hydrophobic layer after the BSP material is coated so that an accurate alignment process is performed by recognizing the alignment mark during an exposure process.

15. An array substrate, comprising a display area and a non-display area, wherein the non-display area comprises: a substrate; an alignment mark disposed on the substrate; an insulating layer disposed on the alignment mark; a hydrophobic layer disposed on the insulating layer corresponding to the alignment mark; and a black photo spacer (BSP) pattern disposed on the insulating layer; wherein the BSP pattern comprises a black matrix and a support post.

16. The array substrate of claim 15, wherein the display area comprises: an active layer disposed on the substrate, wherein the active layer comprises a first metal layer and a second metal layer; a color filter layer disposed on the active layer; the insulating layer disposed on the color filter layer, wherein the insulating layer extends from the display area to the non-display area; and a pixel electrode layer disposed on the insulating layer; wherein the alignment mark is formed from at least one of the first metal layer or the second metal layer.

17. The array substrate of claim 15, wherein a material of the hydrophobic layer comprises polyethylene terephthalate.

18. A liquid crystal display (LCD) panel, comprising: a first substrate; a second substrate disposed opposite to the first substrate; and a plurality of liquid crystal molecules disposed between the first substrate and the second substrate; wherein the second substrate comprises a display area and a non-display area, and the non-display area comprises: a substrate; an alignment mark disposed on the substrate; an insulating layer disposed on the alignment mark; a hydrophobic layer disposed on the insulating layer corresponding to the alignment mark; and a black photo spacer (BSP) pattern disposed on the insulating layer; wherein the BSP pattern comprises a black matrix and a support post.

19. The LCD panel of claim 18, wherein the display area comprises: an active layer disposed on the substrate, wherein the active layer comprises a first metal layer and a second metal layer; a color filter layer disposed on the active layer; the insulating layer disposed on the color filter layer, wherein the insulating layer extends from the display area to the non-display area; and a pixel electrode layer disposed on the insulating layer; wherein the alignment mark is formed from at least one of the first metal layer or the second metal layer.

20. The LCD panel of claim 18, wherein a material of the hydrophobic layer comprises polyethylene terephthalate.

Description

DESCRIPTION OF DRAWINGS

(1) The accompanying figures to be used in the description of embodiments of the present disclosure or prior art will be described in brief to more clearly illustrate the technical solutions of the embodiments or the prior art. The accompanying figures described below are only part of the embodiments of the present disclosure, from which those skilled in the art can derive further figures without making any inventive efforts.

(2) FIG. 1 is a schematic front view showing a structure of layers in a non-display area of an array substrate provided by an embodiment of the present disclosure.

(3) FIG. 2 is a schematic front view showing a structure of layers in a display area of an array substrate provided by an embodiment of the present disclosure.

(4) FIG. 3 is a schematic flowchart showing a method of manufacturing an array substrate provided by an embodiment of the present disclosure.

(5) FIG. 4 to FIG. 10 are schematic views showing layers of the array substrate in each step of the manufacturing method for the array substrate provided by an embodiment of the present disclosure.

(6) FIG. 11 is a schematic front view showing a structure of a liquid crystal display panel provided by an embodiment of the present disclosure.

DETAILED DESCRIPTION

(7) The following description of the various embodiments is provided with reference to the accompanying drawings to demonstrate that the embodiments of the present disclosure may be implemented. It should be understood that terms such as “upper,” “lower,” “front,” “rear,” “left,” “right,” “inside,” “outside,” “lateral” as well as derivative thereof should be construed to refer to the orientation as then described or as shown in the drawings under discussion. These relative terms are for convenience of description, do not require that the present disclosure be constructed or operated in a particular orientation, and shall not be construed as causing limitations to the present disclosure. In the drawings, the identical or similar reference numerals constantly denote the identical or similar elements or elements having the identical or similar functions.

(8) In one embodiment, as shown in FIG. 1 and FIG. 2, an array substrate 100 is provided, including a display area and a non-display area (FIG. 1 shows the non-display area of the array substrate 100, and FIG. 2 shows the display area of the array substrate 100). The non-display area includes an alignment mark 23, an insulating layer 40, a hydrophobic layer 60, and a black photo spacer (BSP) pattern 70 stacked on a substrate 10. The alignment mark 23 is disposed on the substrate 10. The insulating layer 40 is disposed on the alignment mark 23. The hydrophobic layer 60 is disposed on the insulating layer 40 corresponding to the alignment mark 23. The BSP pattern 70 is disposed on the insulating layer 60, wherein the BSP pattern 70 includes a black matrix 71 and a support post 72.

(9) Specifically, the display area of the array substrate 100 includes an active layer 20, a color filter layer 30, an insulating layer 40, and a pixel electrode layer 50, which are as shown in FIG. 2.

(10) Specifically, the active layer 20 includes a first metal layer 21, an interlayer insulating layer 22, and a second metal layer 24. The alignment mark 23 is formed from the first metal layer 21 or the second metal layer 24 and is formed on the non-display area of the array substrate 100. As shown in FIG. 1 and FIG. 2, the alignment mark 23 is formed from the first metal layer 21 and is formed on the non-display area of the array substrate 100.

(11) It should be noted that the array substrate 100 of the present disclosure further includes other common layers, such as a buffer layer and an active layer, which are not described in the embodiments and in figures of the present disclosure.

(12) Furthermore, materials of the first metal layer 21 and the second metal layer 24 may be one selected from the group consisting of Cu, Al, Ti, Mo, or combinations thereof. In addition to the first metal layer 21 or the second metal layer 24, the alignment mark 23 may also be a layer made of a single metal material such as Cu, Al, Ti, or Mo.

(13) Specifically, the color filter layer 30 is formed on the active layer 20. The color filter layer 30 includes three types of color resist pattern (red, green, and blue), which are not shown in FIG. 2. By forming the color filter layer 30 on the array substrate 100 (a color filter on array technology), difficulty in aligning a top substrate with a bottom substrate is reduced.

(14) Furthermore, the insulating layer 40 is formed on the color filter layer 30 and extends from the display area of the array substrate 100 to the non-display area of the array substrate 100.

(15) Furthermore, the pixel electrode layer 50 is formed on the insulating layer 40 and does not extend to the non-display area of the array substrate 100. A material of the pixel electrode 50 is a transparent electrode material such as indium tin oxide.

(16) Furthermore, as shown in FIG. 1, the hydrophobic layer 60 is formed on the insulating layer 40. Specifically, the hydrophobic layer 60 is disposed on the insulating layer 40 corresponding to the alignment mark 23, thereby making a hydrophilicity difference between an alignment mark area and a non-alignment mark area.

(17) Furthermore, a material of the hydrophobic layer 60 includes a hydrophobic material such as polyethylene terephthalate.

(18) Furthermore, the BSP pattern 70 is formed on the non-display area of the array substrate 100, and the BSP pattern 70 includes a black matrix 71 and a support post 72. The black matrix 71 is used to block light, and the support post 72 is used to support the top substrate and the bottom substrate to control a thickness of a cell. A shape of the support post 72 is cuboid-shaped, and a sectional shape of the support post is rectangular, which is shown in FIG. 1.

(19) Specifically, a BSP material is coated on the insulating layer 40 and the hydrophobic layer 60. Because of the hydrophobic layer 60, film thicknesses of a BSP wet film in different positions are affected. A film thickness of the alignment mark area where the BSP covers is reduced, and a light shading effect of the alignment mark area is reduced, thereby solving a problem that it is difficult to recognize an alignment mark and improving accuracy of an alignment process.

(20) Specifically, a material of the BSP is a photoresist.

(21) In one embodiment, a method of manufacturing an array substrate is provided as shown in FIG. 3, including following steps:

(22) Step 10: providing a substrate 10, and forming an alignment mark 23 on the substrate 10, as shown in FIG. 4.

(23) Specifically, an active layer 20 is formed on the substrate 10, wherein the active layer 20 includes the first metal layer 21 and the second metal layer 24, as shown in FIG. 2. The alignment mark 23 is formed from at least one of the first metal layer 21 or the second metal layer 24. The alignment mark 23 as shown in FIG. 1 is formed from the first metal layer 21. Furthermore, the alignment mark 23 is located in a non-display area of the substrate 10. FIG. 5 is a schematic bottom view showing the alignment mark 23 on the substrate 10, and FIG. 4 is a schematic front view showing the alignment mark 23 on the substrate 10.

(24) Furthermore, before the active layer is formed, a buffer layer needs to be formed on the substrate. The active layer further includes other common layers such as an active layer and other insulating layers, and the active layer is thin film transistors on the array substrate.

(25) Step 20: forming an insulating layer 40 on the substrate 10 where the alignment mark 23 is formed, coating a hydrophobic layer 60 on the insulating layer 40 corresponding to the alignment mark 23, and drying the hydrophobic layer 60, as shown in FIG. 6.

(26) Specifically, sequentially forming a color filter layer 30, an insulating layer 40, and a pixel electrode layer 50 on the substrate 10 with the alignment mark 23. The color filter layer 40 and the pixel electrode layer 50 are disposed in the display area of the substrate 10, as shown in FIG. 2.

(27) Specifically, the color filter layer 40 includes three types of color resist pattern (red, green, and blue). By forming the color filter layer 40 on an array substrate (a color filter on array technology), difficulty in aligning a top substrate with a bottom substrate is reduced.

(28) Specifically, coating a red color resist on the substrate with the alignment mark, and then exposing, developing, and etching the red color resist to form the red color resist pattern, wherein the green color resist pattern and the blue color resist pattern can be manufactured by the same method.

(29) Specifically, the insulating layer extends from the display area of the substrate to the non-display area. A material of the insulating layer includes a composite including one or more of non-organic materials such as SiOX, SiNx, and SiNO.

(30) Furthermore, a non-organic material, such as silicon oxide, is deposited on the color filter layer by a chemical vapor deposition process to form the insulating layer.

(31) Specifically, a material of the pixel electrode is a transparent electrode material such as indium tin oxide.

(32) Specifically, after layers in the display area of the substrate are formed, the hydrophobic layer is formed in the non-display area of the substrate. Specifically, the hydrophobic layer is formed on the insulating layer corresponding to the alignment mark.

(33) Specifically, a hydrophobic material, such as the polyethylene terephthalate, is coated on the insulating layer with the alignment mark by an inkjet printing process, a spray coating process, a slit coating process, or a spin coating process. In the inkjet printing process, ink may be shot out at a stationary position, which is the most economical method and has the slightest influence on the display area.

(34) Furthermore, the hydrophobic layer which is coated on the insulating layer is dried. Conditions of a drying process may be decided according to a hydrophobic solvent. In the present embodiment, a drying temperature ranges from 80° C. to 150° C.

(35) Furthermore, the hydrophobic layer is disposed on the insulating layer corresponding to the alignment mark to make a difference of hydrophilicity between an alignment mark area and a non-alignment mark area.

(36) Step 30: coating a BSP material on the insulating layer 40 and the hydrophobic layer 60, and exposing, developing, and etching the BSP material to form a BSP pattern 70, as shown in FIG. 7.

(37) Specifically, the coating process in the Step 30 is same as the coating process in the step of forming the hydrophobic layer. The BSP material is coated on the insulating layer 40 and the hydrophobic layer 60, and then the BSP material is vacuum dried and pre-heated. Because of the hydrophobic layer 60, it is not easy for the BSP material to accumulate in an area where the hydrophobic layer is disposed. Distribution of the BSP material is shown in FIG. 8 to FIG. 10. In FIG. 8, a film thickness of a BSP material 73′ on the hydrophobic layer is less than a film thickness of a BSP material 73 not on the hydrophobic layer (on the insulating layer), and the BSP material 73′ on the hydrophobic layer and the BSP material 73 not on the hydrophobic layer are connectedly disposed. In FIG. 9, the BSP material 73″ on the hydrophobic layer is disconnected, and the BSP material 73″ is disposed only on a portion of the hydrophobic layer. In FIG. 10, none of the BSP material is disposed on the hydrophobic layer.

(38) Furthermore, a BSP layer, which had been preliminarily processed, is exposed, developed, heated, and etched to form a BSP pattern as shown in FIG. 7.

(39) Specifically, in the exposure process, because the film thickness of the BSP material on the hydrophobic layer is less than the film thickness of the BSP material not on the hydrophobic layer or because none of the BSP material is disposed on the hydrophobic layer, light transmittance increases. Therefore, it is easy to recognize the alignment mark, and accuracy of the alignment process increases.

(40) In one embodiment, a liquid display panel (LCD) 1000 is provided, as shown in FIG. 11, including a first substrate 200, a second substrate 400, and a plurality of liquid crystal molecules 300. The second substrate 400 is disposed opposite to the first substrate 200 and includes one of the array substrates 100 mentioned in the above embodiments. The liquid crystal molecules 300 are disposed between the first substrate 200 and the second substrate 400.

(41) Specifically, the first substrate 200 is a color filter substrate, and the second substrate 400 is a color filter on array (COA) substrate.

(42) According to the above embodiments, the present disclosure provides a method of manufacturing an array substrate, an array substrate, and an LCD panel. A non-display area of the array substrate includes a substrate, an alignment mark, an insulating layer, a hydrophobic layer, and a BSP pattern. The hydrophobic layer is disposed on the insulating layer corresponding to the alignment mark to make a difference of hydrophilicity between an alignment mark area and a non-alignment mark area. When a BSP wet film is coated in a sequent process, because of the hydrophobic layer, film thicknesses of the BSP wet film in different positions are affected. A film thickness of the alignment mark area where the BSP covers is reduced, and a light shading effect of the alignment mark area is reduced, thereby solving a problem that it is difficult to recognize an alignment mark and improving accuracy of an alignment process. At the same time, problems of long alignment time and long tack time due to the difficulty in recognizing an alignment mark are solved, thereby reducing production costs.

(43) To sum up, the present disclosure has been described with preferred embodiments thereof. The preferred embodiments are not intended to limit the present disclosure, and it is understood that many changes and modifications to the described embodiment can be carried out without departing from the scope and the spirit of the disclosure that is intended to be limited only by the appended claims.