ADAPTIVE SWITCH SPEED CONTROL OF POWER SEMICONDUCTORS

Abstract

A semiconductor switch device includes a switchable power semiconductor and a control circuit. The semiconductor switch device has a current sink and a current amplifier designed to amplify during a switching process a partial current of the total current flowing across the control capacitor that is not discharged by the current sink up to an adjustable maximum current and to apply the amplified partial current to the control electrode of the power semiconductor so as to counteract the change in the voltage across the collector-emitter path or the drain-source path of the power semiconductor during the switching process. An additional circuit provides an adapted switch-on transition by smoothing the collector voltage and/or the drain voltage of the switchable power semiconductor when switching over the collector-emitter path or the drain-source path of the power semiconductor from a blocked state into a conductive state.

Claims

1.-8. (canceled)

9. A semiconductor switch device, comprising: a power semiconductor having a collector or a drain, an emitter or a source, and a control electrode embodied as a gate or a gate electrode, and configured to be switchable along a collector-emitter path or a drain-source path via the control electrode, at least one control circuit comprising a current sink capacitively coupled to the collector via a regulating capacitor configured to divert, up to an adjustable maximum current, a partial current of a total current flowing via the regulating capacitor during a switching process, wherein the adjustable maximum current is adjustable via an adjustable current source, and a current amplifier having an input side connected to an end of the current sink that is capacitively coupled to the regulating capacitor and to a positive or a negative supply voltage, and an output side connected to the control electrode of the power semiconductor, with the current amplifier configured to amplify by a predetermined amplification factor the partial current flowing via the regulating capacitor and not being diverted by the current sink during the switching process and to apply the amplified partial current to the control electrode so as to counteract a change in a voltage across the collector-emitter path or across the drain-source path during the switching process, and the semiconductor switch device further comprising an additional circuit connected to the control electrode and configured to provide a smooth switch-on transition of a collector voltage or a drain voltage, or both, when switching over the collector-emitter path or drain-source path from a blocked state to a conductive state.

10. The semiconductor switch device of claim 9, wherein a first control circuit of the at least one control circuit comprises a first current amplifier connected to a negative supply voltage and configured to supply a negative current to the control electrode, and a second control circuit of the at least one control circuit comprises a second current amplifier connected to a positive supply voltage and configured to supply a positive current to the control electrode.

11. The semiconductor switch device of claim 9, wherein the current sink comprises a metal oxide semiconductor field effect transistor (MOSFET) connected in a current feedback arrangement, a current feedback resistor and the adjustable voltage source, wherein a drain electrode of the MOSFET is connected to the regulating capacitor and a source electrode of the MOSFET is connected via the current feedback resistor to ground and a gate electrode of the MOSFET Is supplied by the adjustable voltage source with a voltage referenced against ground.

12. The semiconductor switch device of claim 9, wherein the current amplifier comprises a follower semiconductor connected as a source/emitter follower, a gate resistor, a source resistor and a diode, wherein the diode is disposed between the regulating capacitor and a control electrode of the follower semiconductor in a forward-conducting direction toward the control electrode, wherein the gate resistor is disposed between the control electrode of the follower semiconductor and the control electrode of the power semiconductor, and wherein the source resistor is disposed between a source electrode of the follower semiconductor and the control electrode of the power semiconductor.

13. The semiconductor switch device of claim 12, wherein the follower semiconductor is configured as a MOSFET connected as a source-follower.

14. The semiconductor switch device of claim 12, wherein the follower semiconductor is configured as a bipolar transistor connected as an emitter follower.

15. The semiconductor switch device of claim 9, wherein the power semiconductor is configured as an insulated-gate bipolar transistor (IGBT), as a metal oxide semiconductor field-effect transistor (MOSFET), as a silicon carbide metal oxide semiconductor field-effect transistor (SiC MOSFET) or as a bipolar transistor.

16. A frequency converter comprising a semiconductor switch device according to claim 9, wherein the power semiconductor is constructed as an Insulated-gate bipolar transistor (IGBT).

Description

[0042] The above-described properties, features and advantages of this invention and the manner in which these are achieved will now be described more clearly and Intelligibly in relation to exemplary embodiments, and illustrated in detail by reference to the drawings. In the drawings:

[0043] FIG. 1 schematically shows the dependence of switching energy and the rate of rise of the voltage on the collector current at switch-on of a power semiconductor,

[0044] FIG. 2 schematically shows the relationship between switching energy and the rate of rise of the voltage at switch-off of a power semiconductor,

[0045] FIG. 3 schematically shows a circuit for controlling the rate of rise of the voltage at switch-on,

[0046] FIG. 4 schematically shows a circuit for controlling the rate of rise of the voltage at switch-off,

[0047] FIG. 5 schematically shows an embodiment of a current sink,

[0048] FIG. 6 schematically shows an embodiment of a current amplifier,

[0049] FIG. 7 schematically shows a simulation circuit, and

[0050] FIGS. 8 to 11 show simulation results for the simulated progression over time of the collector voltage, the collector current and the control voltage/gate voltage of a simulated switching transistor for different predetermined highest rates of rise of the voltage by means of an adjustable voltage source.

[0051] Parts which correspond to one another are provided with the same reference characters in all the drawings.

[0052] FIG. 1 schematically shows the dependence of the rate of rise of the voltage

[00001]$\frac{{\mathrm{du}}_{\mathrm{CE}}}{\mathrm{dt}}$

and the switch-on energy E.sub.ON at switch-on of a power semiconductor which can be configured, for example, as a bipolar transistor with an insulated gate electrode (IGBT), on the strength of the collector current I.sub.C. At switch-on, the rate of rise of the voltage

[00002]$\frac{{\mathrm{du}}_{\mathrm{CE}}}{\mathrm{dt}}$

and the switch-on energy E.sub.ON change contradirectionally dependent upon the switched collector current I.sub.C. As the collector current I.sub.C Increases, the switch-on energy E.sub.ON increases while the rate of rise of the voltage

[00003]$\frac{{\mathrm{du}}_{\mathrm{CE}}}{\mathrm{dt}}$

decreases.

[0053] As shown in FIG. 2, however, at switch-off the rate of rise of the voltage

[00004]$\frac{{\mathrm{du}}_{\mathrm{CE}}}{\mathrm{dt}}$

and the switch-off energy E.sub.OFF change codirectionally: both values increase with increasing switched collector current I.sub.C.

[0054] Apart from the collector current I.sub.C, the switching energies E.sub.ON, E.sub.OFF and the rate of rise of the voltage

[00005]$\frac{{\mathrm{du}}_{\mathrm{CE}}}{\mathrm{dt}}$

are also dependent upon further parameters, for example, on the temperature and the intermediate circuit voltage. Thus, for example, a power semiconductor will switch faster at a low temperature and a high intermediate circuit voltage than at a high temperature and low intermediate circuit voltage.

[0055] FIG. 3 schematically shows a first control circuit RS1 for controlling the gradient of a collector voltage

[00006]$\frac{\mathrm{du}}{\mathrm{dt}}$

at switch-on of a switching transistor T.sub.2 which is configured as an IGBT, by means of a first current sink S.sub.1 and a first current amplifier V.sub.1. The switching transistor T.sub.2 is switched by means of a first and second switch SW1, SW2 via a switching transistor gate resistor R.sub.G. The two switches SW1, SW2 switch alternatingly and are thus at least never closed simultaneously.

[0056] According to the invention, the collector of the switching transistor T.sub.2 is capacitively coupled to the first current sink S.sub.1 via a regulating capacitor C.sub.1. The first current sink S.sub.1 is configured so that it absorbs a current from the regulating capacitor C.sub.1 up to a current threshold I≤I.sub.target and conducts it away to 0V. The first current sink S.sub.1 does not absorb the current max(I.sub.C1−I.sub.target,0) above the current threshold I.sub.target fed in by the regulating capacitor C.sub.1. The current difference ΔI.sub.C1=max(I.sub.C1−I.sub.target,0) not absorbed by the first current sink S.sub.1 is fed to the first current amplifier V.sub.1 and Is thereby amplified by an amplification factor v. The amplified difference current v.Math.ΔI.sub.C1 is fed into the gate of the switching transistor T.sub.2.

[0057] In a similar way, FIG. 4 schematically shows a circuit for controlling the rate of rise of the voltage

[00007]$\frac{{\mathrm{du}}_{\mathrm{CE}}}{\mathrm{dt}}$

at switch-off of the switching transistor T.sub.2 by means of a second control circuit RS2 which is formed by a second current sink S.sub.2 and a second current amplifier V.sub.2.

[0058] The functioning of the two circuits according to FIG. 3 and FIG. 4 is equivalent in principle and will now be described by reference to the circuit of FIG. 4.

[0059] For this purpose, it is assumed that the switching transistor T.sub.2 was switched on at the start of the switching process. If the first switch SW1 switches off and the second switch SW2 switches on, the gate of the switching transistor T.sub.2 Is discharged. The switching transistor T.sub.2 switches off and the voltage u at the collector of the switching transistor T.sub.2 rises. The regulating capacitor C.sub.1 conducts the increased collector voltage away, wherein a regulating capacitor current

[00008]$I_{C1}=C_1.Math.\frac{\mathrm{du}}{\mathrm{dt}}$

flows via the regulating capacitor C.sub.1.

[0060] The second current sink S.sub.2 draws from this current via the regulating capacitor C.sub.1 a partial current I.sub.sink of not more than I.sub.target. The remaining portion of the current of

[00009]$\Delta I_{C1}=I_{C1}-I_{\mathrm{sink}}=C_1.Math.\frac{\mathrm{du}}{\mathrm{dt}}-I_{\mathrm{sink}}$

is fed into the second current amplifier V.sub.2 and Is amplified thereby by the amplification factor v. The output current of the second current amplifier V.sub.2 therefore amounts to I.sub.A=v.Math.ΔI.sub.C1.

[0061] This output current I.sub.A is fed to the gate of the switching transistor T.sub.2. By this means, the gate voltage of the switching transistor T.sub.2 is increased and thus the gradient of the collector current I.sub.C of the now less strongly blocked switching resistor T.sub.2 is reduced. This causes a reduction in the rate of rise of the collector voltage

[00010]$\frac{\mathrm{du}}{\mathrm{dt}}$

and thereby, a reduction in the regulating capacitor current I.sub.C1 via the regulating capacitor C.sub.1.

[0062] By this means, the rate of rise of the collector voltage of the switching transistor T.sub.2 declines.

[0063] For a second current amplifier V.sub.2 assumed to be functioning ideally with an amplification factor v.fwdarw.∞, a rate of rise of the voltage of

[00011]$\frac{\mathrm{du}}{\mathrm{dt}}=\frac{1}{C}.Math.I_{\mathrm{sink}}$

comes about.

[0064] Since the greatest partial current absorbable by the second current sink S.sub.2 is limited according to I.sub.sink≤I.sub.target, the current threshold I.sub.target acts as an adjustment variable for the rate of rise of the voltage

[00012]$\frac{\mathrm{du}}{\mathrm{dt}}.$

[0065] If the rate of rise of the voltage on switching exceeds the limit value defined by the current threshold I.sub.target, so that

[00013]$\frac{\mathrm{du}}{\mathrm{dt}}>\frac{1}{C_1}.Math.I_{\mathrm{target}},$

then the rate of rise of the voltage is controlled by the closed circuit from the collector of the switching transistor T.sub.2 via the regulating capacitor C.sub.1 and the second current amplifier V.sub.2 to the gate of the switching transistor T.sub.2 and via the transfer characteristic of the switching transistor T.sub.2 back again to the collector thereof.

[0066] If the change in the collector voltage at switch-off does not reach the maximum value specified by means of the current threshold so that

[00014]$\frac{\mathrm{du}}{\mathrm{dt}}\le \frac{1}{C_1}.Math.I_{\mathrm{target}}$

applies throughout the whole switch-off process, then the second control circuit RS2 formed by the second current sink S.sub.2 and the second current amplifier V.sub.2 has no effect.

[0067] FIG. 5 schematically shows an embodiment for the second current sink S.sub.2 of the second control circuit RS2 for limiting the rate of rise of the collector voltage

[00015]$\frac{\mathrm{du}}{\mathrm{dt}}$

of the switching transistor T.sub.2 at switch-off. The second current sink S.sub.2 comprises a metal oxide semiconductor field-effect transistor (MOSFET) T.sub.3, a current feedback resistor R.sub.1 which is connected to ground on the source side of the MOSFET T.sub.3, and an adjustable voltage source U.sub.adapt which specifies the gate voltage of the MOSFET T.sub.3. With a positive gate voltage of the adjustable voltage source U.sub.adapt, the current threshold I.sub.target can be set, above which the MOSFET T.sub.3 transfers into linear operation.

[0068] The current I.sub.sink absorbed by the second current sink S.sub.2 can be calculated dependent upon the voltage of the adjustable voltage source U.sub.adapt, dependent upon the gate-source threshold voltage U.sub.GS(th),3 of the MOSFET T.sub.3 and dependent upon the current feedback resistor R.sub.1, as follows:

[00016]$U_{\mathrm{GS}\left(\mathrm{th}\right),3}+I_{\mathrm{sink}}.Math.R_1=U_{\mathrm{adapt}}$$I_{\mathrm{sink}}=\frac{U_{\mathrm{adapt}}-U_{\mathrm{GS}\left(\mathrm{th}\right),3}}{R_1}$

[0069] FIG. 6 schematically shows an embodiment for the second current amplifier V.sub.2, which comprises a MOSFET T.sub.1, a source resistor R.sub.2, a gate resistor R.sub.3 and a diode D.sub.1. The MOSFET T.sub.1, the source resistor R.sub.2 and the gate resistor R.sub.3 are connected in the manner of a source follower V.sub.2. The diode D.sub.1 connected upstream on the input side at the gate decides the current direction so that the source follower V.sub.2 is effective only for a positive, i.e. flowing in the direction of the gate, difference current ΔI.sub.C1=I.sub.C1−I.sub.sink.

[0070] In an exemplary embodiment (not shown in detail), the MOSFET T.sub.1 can be replaced by a bipolar transistor. Then the second current amplifier V.sub.2 is operated as an emitter follower.

[0071] By means of the resistors R.sub.2, R.sub.3, taking account of the gate-source-threshold voltage U.sub.GS(th),1 of the MOSFET T.sub.1, the amplification factor v of the second current amplifier V.sub.2 can be determined as follows:

[00017]$v=\frac{R_3-\frac{U_{\mathrm{GS}\left(\mathrm{th}\right),1}}{I_{C1}-I_{\mathrm{sink}}}}{R_2}$

[0072] For the operation of the switching transistor T.sub.2 in the Miller plateau and Ignoring the parasitic Miller capacitance between the gate electrode and the collector electrode,

U.sub.GS(th),1+I.sub.R.sub.G.Math.R.sub.2=(I.sub.C1−I.sub.sink).Math.R.sub.3

where I.sub.R.sub.G is the current flowing along the switching transistor gate resistor R.sub.G which results from the negative supply voltage U.sub.− which is assumed in FIG. 6, by way of example, to be minus 8 Volt, and from the Miller plateau voltage U.sub.Millerplateau,2 of the switching transistor T.sub.2, there results as follows:

[00018]$I_{R_G}=\frac{(|U_{-}.Math.+U_{\mathrm{Millerplateau},2})}{R_G}$

[0073] Using the current-voltage relationship at the switching transistor T.sub.2

[00019]$I_{C1}=C_1.Math.\frac{\mathrm{du}}{\mathrm{dt}}=I_{\mathrm{Senke}}+\frac{U_{\mathrm{GS}\left(\mathrm{th}\right),1}+\frac{R_2}{R_G}(.Math.U_{-}.Math.+U_{\mathrm{Millerplateau},2})}{R_3}$

and taking account of the relationship described by reference to FIG. 5 for the current

[00020]$I_{\mathrm{sink}}=\frac{U_{\mathrm{adapt}}-U_{\mathrm{GS}\left(\mathrm{th}\right),3}}{R_1},$

therefore for the rise rate of the collector voltage of the switching transistor T.sub.2, the following voltage rise rate determining equation results:

[00021]$\frac{\mathrm{du}}{\mathrm{dt}}=\frac{1}{C_1}.Math.\left(\frac{U_{\mathrm{GS}\left(\mathrm{th}\right),1}+\frac{R_2}{R_G}(.Math.U_{-}.Math.+U_{\mathrm{Millerplateau},2})}{R_3}+\frac{U_{\mathrm{adapt}}-U_{\mathrm{GS}\left(\mathrm{th}\right),3}}{R_1}\right)$

[0074] As is apparent therefrom, the rate of rise of the voltage

[00022]$\frac{\mathrm{du}}{\mathrm{dt}}$

can be controlled directly via the adjustable voltage source U.sub.adapt.

[0075] In the use of this voltage rise rate determining equation, it is to be taken into account that for the gate-source threshold voltages U.sub.GS(th),1, U.sub.GS(th),3 and for the Miller plateau voltage U.sub.Millerplateau,2 it is not the datasheet values that are to be used, but that these values are to be taken from the diagrams of the respective components for the respectively adjustable drain current and/or collector current I.sub.C.

[0076] If the second current amplifier V.sub.2 is configured, by means of a bipolar transistor in place of a MOSFET T.sub.1, as an emitter follower, then in place of the gate-source threshold voltage U.sub.GS(th),1, the base-emitter voltage U.sub.BE of the bipolar transistor must be Inserted into the voltage rise rate determining equation.

[0077] The functioning of the first control circuit RS1 for the control of the rate of rise of the voltage during the switching-on process according to FIG. 3 is provided in a similar way to the description regarding the second control circuit RS2, wherein the components according to the circuit of FIG. 3 are to be used in place of the components according to the circuit of FIG. 4.

[0078] FIG. 7 shows a circuit for a simulation circuit 1 of the first and second control circuit RS1, RS2 simulated by means of the simulation tool LTSpice. The simulation circuit 1 comprises an additional circuit 1.1 for an adapted switch-on transition, said addition circuit being arranged on the gate side of the switching transistor T.sub.2. In addition, the simulation circuit 1 has a first leakage inductance L2 on the cathode side of the freewheeling diode U.sub.1 and a second leakage inductance L3 arranged on the gate side of the switching transistor T.sub.2, in order to enable an application-related simulation of the switching behavior.

[0079] For the simulation of an IGBT nominal current of 200 ampere, the switching transistor T.sub.2 is emulated by a parallel connection of five individual transistors which are simulated as a level-2 model of a 40 ampere IGBT3 trench-IGBT according to information from the manufacturer Infineon.

[0080] The simulation circuit 1 further comprises voltage controlled switches as the switches SW1, SW2 and is supplied with a bipolar driver supply with a positive supply voltage U.sub.+=15 Volt and a negative supply voltage U.sub.−=−8 Volt.

[0081] The additional circuit 1.1 for an adapted switch-on transition enables a sliding transition of the collector voltage u from the blocking to the conducting state and prevents or reduces a delay of the desired reduction in the rates of rise of the voltage

[00023]$\frac{\mathrm{du}}{\mathrm{dt}},$

which otherwise would be caused due to the reaction time of the power amplifier V.sub.1 and the leakage inductance L3 on sudden switch-on of the collector current I.sub.C. In one embodiment in which the maintenance of a maximum rate of rise of the voltage

[00024]$\frac{\mathrm{du}}{\mathrm{dt}}\le \frac{\mathrm{du}}{\mathrm{dt}}{|}_{\max }$

is not required, the additional circuit 1.1 can be dispensed with. For the switch-off process, the simulation circuit 1.1 is not required since the rate of rise of the voltage

[00025]$\frac{\mathrm{du}}{\mathrm{dt}}$

slowly rises at switch-off and thus a sufficiently rapid control intervention of the current amplifier V.sub.2 is possible.

[0082] In the embodiment according to FIG. 7, the second amplifier V.sub.2 has a resistor R7. In an advantageous manner, this resistor R7 and the gate resistor R.sub.G of the driver offer a damping for the oscillator circuit that is formed from the gate capacitance of the switching transistor T.sub.2 and the leakage inductance L3 of the gate circuit. In contrast to the good dynamic response of the circuit according to the invention, operational amplifier circuits known from the prior art lose switching time and can only deliver a low gate current. Drivers known from the prior art with a push-pull output stage also offer only a smaller dynamic response due to the hysteresis resulting from the principle involved. A switching output stage known from the prior art with an inductance in the gate circuit also offers only a reduced dynamic response as compared with the Invention and is complex and expensive in the implementation.

[0083] FIGS. 8 to 11 show results of a simulation of the simulation circuit 1 with the simulation tool LTSpice, wherein changes in the collector voltage u, the switching current i switched by the switching transistor T.sub.2 and in the gate voltage u.sub.G at the gate of the switching transistor T.sub.2 as a function of time t measured from the switching time point. Each of FIGS. 8 to 11 shows collector voltage variations u.sup.(k)(t), k=1 . . . 4, switching current variations i.sup.(k)(t), k=1 . . . 4 and gate voltage variations u.sub.G.sup.(k)(t), k=1 . . . 4 for four different settings of the adjustable voltage source U.sub.adapt, whereby the influence thereof on the rate of rise of the voltage

[00026]$\frac{\mathrm{du}}{\mathrm{dt}}.$

during the switching process is made clear. The index k Increases, in each case, with the voltage value of the adjustable voltage source U.sub.adapt, and thus also with the rate of rise of the voltage

[00027]$\frac{\mathrm{du}}{\mathrm{dt}}$

[0084] FIG. 8 shows simulation progressions u.sup.(k)(t),u.sub.G.sup.(k)(t),i.sup.(k)(t), k=1 . . . 4 for the simulation of switch-on processes of the almost current-free switching transistor T.sub.2. The higher the voltage of the adjustable voltage source U.sub.adapt is selected to be, that is, with increasing Index k, the higher is the rate of rise of the voltage

[00028]$\frac{\mathrm{du}}{\mathrm{dt}}$

of the collector voltage progression u.sup.(k)(t), k=1 . . . 4. The plateau of the gate voltage progressions u.sup.(k)(t), k=1 . . . 4 differs accordingly. With this embodiment, the rate of rise of the voltage

[00029]$\frac{\mathrm{du}}{\mathrm{dt}}$

of the collector voltage progression u.sup.(k)(t), k=1 . . . 4 can be reduced to a quarter of the value that is achievable without the control circuits RS1, RS2.

[0085] FIG. 9 shows simulation progressions u.sup.(k)(t),u.sub.G.sup.(k)(t),i.sup.(k)(t), k=1 . . . 4 for the simulation of switch-on processes of the switching transistor T.sub.2 with half the nominal current strength, i.e. at a switched current strength of 200 ampere.

[0086] FIG. 10 shows simulation progressions u.sup.(k)(t),u.sub.G.sup.(k)(t),i.sup.(k)(t), k=1 . . . 4 for the simulation of switch-on processes of the switching transistor T.sub.2 at the nominal current strength, i.e. at a switched current strength of 400 ampere.

[0087] It can be seen from FIGS. 9 and 10 that the rate of rise of the voltage

[00030]$\frac{\mathrm{du}}{\mathrm{dt}}$

decreases with increasing switched current strength. At the same time, the influence of the voltage of the adjustable voltage source U.sub.adapt decreases, in particular, at lower voltage values so that the rate of rise

[00031]$\frac{\mathrm{du}}{\mathrm{dt}}$

of the collector voltage progressions u.sup.(k)(t), k=1 . . . 4 differs less strongly at higher switched current strengths than at lower switched current strengths.

[0088] FIG. 11 shows simulation progressions u.sup.(k)(t),u.sub.G.sup.(k)(t),i.sup.(k)(t), k=1 . . . 4 for the simulation of switch-off processes of the switching transistor T.sub.2 at the nominal current strength, i.e. at a switched current strength of 400 ampere. Here also, with increasing voltage of the adjustable voltage source U.sub.adapt the rate of rise of the voltage

[00032]$\frac{\mathrm{du}}{\mathrm{dt}}$

rises to follow the value. In addition, a different plateau height is reached in the gate voltage progressions u.sub.G.sup.(k)(t), k=1 . . . 4 as the collector voltage u increases.

[0089] Although the invention has been illustrated and described in detail on the basis of exemplary embodiments, the Invention is not restricted by the examples given and other variations can readily be derived therefrom by a person skilled in the art, without departing from the protective scope of the invention.