DEADTIME OPTIMIZATION FOR GaN HALF-BRIDGE AND FULL-BRIDGE SWITCH TOPOLOGIES

Abstract

Disclosed is a method for deadtime optimization in a half-bridge switch or full-bridge switch wherein high-side and low-side switches comprise GaN transistors; a circuit for implementing the method; and a power switching system comprising a GaN half-bridge or a GaN full-bridge and a deadtime optimization system. The circuit comprises a drain current bump filter for generating a current charge output; and circuit elements for comparing the current charge output to a reference current charge C.sub.oss and generating a deadtime adjust signal. The deadtime adjust signal may be used to adjust deadtime to reduce or minimize deadtime, and deadtime losses, while avoiding cross-conduction.

Claims

1. A method of controlling deadtime for a half-bridge or full-bridge switch topology comprising a driver, wherein high side and low side switches comprise GaN transistors, comprising: receiving a first input comprising a low-side drain current signal I.sub.D; receiving a second input indicative of a bulk voltage V.sub.dc; generating a current difference signal I.sub.D-I.sub.LOAD, where I.sub.LOAD is a load current; integrating the current difference signal I.sub.D-I.sub.LOAD over a time interval of t.sub.2-t.sub.1 during voltage commutation to generate a current charge output
∫.sub.t.sub.1.sup.t.sup.2(I.sub.D(t)-I.sub.LOAD)dt; based on the voltage V.sub.dc obtaining a reference current charge C.sub.oss for the high side switch
∫.sub.0.sup.V.sup.dcC.sub.oss(V.sub.DS)dV.sub.DS 0<V.sub.DS<V.sub.dc; t.sub.1<t<t.sub.2; comparing the current charge output and the reference current charge C.sub.oss, and generating a deadtime adjust output signal; outputting the deadtime adjust signal to the driver.

2. The method of claim 1, wherein, the deadtime adjust signal is used to reduce or optimize deadtime to reduce deadtime losses, while avoiding cross-conduction.

3. A circuit for controlling deadtime for a half-bridge or full-bridge switch topology comprising a driver, wherein high-side and low-side switches comprise GaN transistors, the circuit comprising a drain current bump filter for generating a current charge output; and circuit elements for comparing the current charge output to a reference current charge C.sub.oss and generating a deadtime adjust signal.

4. A circuit for controlling deadtime for a half-bridge or full-bridge switch topology wherein high-side and low-side switches comprise GaN transistors, comprising: an input for receiving a low-side drain current I.sub.D; an input for sensing a bulk voltage V.sub.dc; a unit for generating a current difference signal I.sub.D-I.sub.LOAD, where I.sub.LOAD is a load current; a timer for recording and counting the deadtime; an integrator for integrating the current difference signal I.sub.D-I.sub.LOAD over a time interval of t.sub.2-t.sub.1 during voltage commutation to generate a current charge output
∫.sub.t.sub.1.sup.t.sup.2(I.sub.D(t)-I.sub.LOAD)dt; a reference source for obtaining a reference current charge C.sub.oss based on V.sub.dc; deadtime adjustment circuitry for receiving the current charge output from the integrator, comparing the current charge output with the reference current charge C.sub.oss, and generating a deadtime adjust signal; an output for outputting the deadtime adjust signal to the driver.

5. The circuit of claim 4, wherein the unit for generating a current difference signal I.sub.D−I.sub.LOAD is a DC blocking unit or a subtractor.

6. The circuit of claim 4, wherein the integrator is an analog integrator or a digital integrator.

7. The circuit of claim 4 wherein, based on the sensed bulk voltage V.sub.dc, the reference source provides any one of: real-time calculation of the reference current charge C.sub.oss; real-time adjustment of a stored reference current charge C.sub.oss; an offline look-up from a table of reference current charge values.

8. The circuit of claim 4, wherein: the unit for generating a current difference signal I.sub.D−I.sub.LOAD is a DC blocking unit or a subtractor; the integrator is an analog integrator or a digital integrator; and based on the sensed bulk voltage V.sub.dc the reference source provides any one of: real-time calculation of the reference current charge C.sub.oss; real-time adjustment of a stored reference current charge C.sub.oss; and an offline look-up from a table of reference current charge values.

9. A power switching system comprising a GaN half-bridge or a GaN full-bridge and a deadtime optimization system comprising a drain current bump filter for generating a current charge output during voltage commutation; and circuit elements for comparing the current charge output to a reference current charge C.sub.oss, and generating a deadtime adjust signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG. 1 shows a comparison of typical reverse conduction (Quadrant 3) characteristics for an example GaN E-HEMT vs. an example Si MOSFET;

[0027] FIG. 2A shows a plot of Deadtime Loss (W) vs. Deadtime (ns) for an example 3 kW Totem Pole PFC and FIG. 2B shows a plot of Deadtime Loss contribution (%) vs. Deadtime (ns) for the example 3 kW Totem Pole PFC;

[0028] FIG. 3 shows schematic diagrams to illustrate hard-switching transitions for a half-bridge for: (a) S.sub.1 conducting; (b) deadtime; (c) current commutation; (d) voltage commutation; (e) S.sub.2 conducting;

[0029] FIG. 4 shows hard-switching turn-on waveforms for an example GaN E-HEMT;

[0030] FIG. 5 shows an equation to be satisfied if there is no cross-conduction;

[0031] FIG. 6 shows a plot of parasitic capacitance C.sub.oss (pF) vs. drain-source voltage V.sub.DS(V) for an example GaN HEMT (GS66516T);

[0032] FIG. 7 shows schematic example waveforms for Case 1: cross-conduction occurs during voltage commutation; Case 2: cross-conduction occurs after voltage commutation; Case 3: cross-conduction occurs during and after voltage commutation;

[0033] FIGS. 8 and 9 show double pulse test waveforms for examples with cross-conduction conditions;

[0034] FIG. 10 shows double pulse test waveforms for an example with a normal (no cross-conduction) condition;

[0035] FIG. 11 shows a table listing some parameters for the examples shown in FIGS. 8, 9 and 10; and

[0036] FIG. 12 shows a functional block diagram of a circuit for implementing a method of deadtime optimization of an example embodiment;

[0037] FIG. 13 shows a flow chart to illustrate steps in a method of deadtime optimization of an example embodiment.

DETAILED DESCRIPTION

[0038] FIG. 1 shows a comparison of typical reverse conduction (Quadrant 3) characteristics for an example GaN E-HEMT vs. an example Si MOSFET. The reverse conduction of a GaN E-HEMT has a “diode” like characteristic and its reverse conduction voltage drop is higher than for a Si MOSFET, so complementary driving signals are required for driving GaN transistors for half-bridge and full-bridge applications, such as, synchronous rectifiers, buck converters, LLC, ACF and motor drives. A method for deadtime optimization is required for GaN half-bridge and full-bridge switch topologies to avoid cross-conduction while minimising deadtime loss, i.e. minimizing the time of operation in Quadrant 3.

[0039] FIG. 2A shows a plot of Deadtime Loss (W) vs. Deadtime (ns) for an example 3 kW Totem Pole PFC, for a switching frequency fsw=130 kHz. FIG. 2B shows a plot of Deadtime Loss contribution (%) vs. Deadtime (ns) for the example 3 kW Totem Pole PFC.

[0040] The deadtime loss is calculated as:

P.sub.deadtime=fsw.sup.*E.sub.deadtime=fsw.sup.*(—Vgsoff+Vth+Rdson_GaN(Tj).sup.*Id).sup.*Id.sup.*T.sub.deadtime

[0041] These results illustrate how the deadtime T.sub.deadtime contributes to deadtime losses and that deadtime losses are a significant loss contribution.

[0042] FIG. 3 shows hard-switching transitions for (a) S.sub.1 conducting; (b) deadtime; (c) current commutation; (d) voltage commutation; (e) S.sub.2 conducting. The resulting low-side drain current I.sub.D is shown in FIG. 4, which shows hard-switching turn-on waveforms for an example GaN HEMT. During the voltage commutation period, from t.sub.1 to t.sub.2, as illustrated in FIG. 3(d) the voltage across the high-side switch S.sub.1 increases and the voltage across the low-side switch S2 decreases. Accordingly, the parasitic capacitances C.sub.1 and C.sub.2 will be charged and discharged, respectively. As the two-dimensional electron gas (2DEG) of S.sub.2 is conducting and the 2DEG of S.sub.1 is turned off, a charging current flows from C.sub.1 through S.sub.2 to generate a current bump as illustrated in FIG. 4. GaN HEMTs do not have inherent body diodes, therefore exhibit no reverse recovery loss during voltage commutation (t.sub.1-t.sub.2). The bump area of the low-side drain current I.sub.D results exclusively from the capacitance C.sub.1 charging current I.sub.qoss from the opposite switch device S.sub.1:

I.sub.D(t)=I.sub.qoss(t)+I.sub.LOAD, t.sub.1<t<t.sub.2

[0043] This behavior is fundamentally different from Si MOSFETs and SiC MOSFETs. The charging current I.sub.quoss for the GaN capacitance (C.sub.oss) during voltage commutation, i.e. between t.sub.1 and t.sub.2, can be calculated as:

[00001]$I_{\mathrm{qoss}}\left(t\right)=C_{\mathrm{oss}}\left(V_{\mathrm{DS}}\right)\frac{{\mathrm{dV}}_{\mathrm{DS}}}{\mathrm{dt}},0<V_{\mathrm{DS}}<V_{\mathrm{dc}};t_1<t<t_2$

[0044] If there is no cross-conduction, then the equation shown in FIG. 5 should always be satisfied:

∫.sub.t.sub.1.sup.t.sup.2(I.sub.D(t)-I.sub.LOAD)dt=∫.sub.0.sup.V.sup.dcC.sub.OSS(V.sub.DS)dV.sub.DS 0<V.sub.DS<V.sub.dc; t.sub.1<t<t.sub.2

[0045] In contrast, if there is cross-conduction, the current bump will be greater than C.sub.OSS charge:

∫.sub.t.sub.1.sup.t.sup.2(I.sub.D(t)-I.sub.LOAD)dt∫.sub.0.sup.V.sup.dcC.sub.OSS(V.sub.DS)dV.sub.DS 0<V.sub.DS<V.sub.dc; t.sub.1<t<t.sub.2

which can happen 1) during voltage commutation, 2) after voltage commutation or 3) both during and after voltage commutation.

[0046] Examples for three cases are illustrated in FIG. 7, which shows example waveforms for Case 1: cross-conduction occurs during the voltage commutation; Case 2: cross-conduction occurs after the voltage commutation; Case 3: cross-conduction occurs during and after the voltage commutation. As illustrated, there may be multiple pulses after the voltage commutation caused by cross-conduction. The parasitic capacitance C.sub.oss of a GaN transistor is independent from the load current, the junction temperature and the switching speed. The parasitic capacitance C.sub.oss of a GaN transistor is provided in the datasheet for different V.sub.DS. For example, FIG. 6 shows a parasitic capacitance C.sub.oss curve, i.e. a plot of parasitic capacitance C.sub.oss (pF) vs. drain-source voltage V.sub.DS for an example 650 V, 25 mΩ, GaN E-HEMT (GaN Systems GS66516T).

[0047] FIGS. 8 and 9 show example double pulse test waveforms for two examples with cross-conduction conditions, and FIG. 10 shows double pulse test waveforms for an example of a normal condition, with no cross-conduction. As shown in the example waveforms in FIG. 8, cross-conduction occurs during voltage commutation with R.sub.g_on=16Ω, V.sub.GS_off=0 V when V.sub.DS=286 V and I.sub.LOAD=2A. For the same R.sub.g_on=16Ω, and V.sub.=0 V, by increasing V.sub.DS to 296 V, cross-conduction occurs during and after the voltage commutations, as shown in the example waveforms in FIG. 9. For comparison, an example with no cross-conduction is shown in FIG. 10, using the same R.sub.g_on=16Ω, and I.sub.LOAD=2A, but V.sub.GS_off=−3 V.

[0048] For this example, the theoretical values of charge from C.sub.1 during the voltage commutation period are calculated in the equations shown in FIG. 11 for V.sub.DS=286 V and V.sub.DS=296 V. FIG. 11 shows a table listing parameters comprising the current bump area (charge in nC) for the examples shown in FIGS. 8 and 9 for cross-conduction conditions and the example shown in FIG. 10 for a normal condition. The bump charges are higher than the theoretical values (reference values) for the two examples with cross-conduction. For the normal condition, with no-cross conduction, there is a 11 nC different between the measured bump and the theoretical C.sub.oss charge (122 nC) which arises from parasitic capacitances C.sub.pcb and C.sub.pl, which are fixed values and independent from cross-conduction.

[0049] Since the on-state resistance R.sub.ds_on of a GaN HEMT is low, it is much easier to observe cross-conduction or potential cross-conduction by monitoring the drain current I.sub.D rather than by monitoring the drain-source voltage V.sub.DS. That is, the drain current bump during voltage commutation can be used to provide a method of monitoring and adjusting or controlling deadtime, e.g. reducing deadtime to reduce deadtime losses while avoiding cross-conduction. Also because the parasitic capacitance C.sub.oss of a GaN transistor is independent of load current, junction temperature and switching speed, this method of monitoring and controlling deadtime is independent of these operating parameters. Thus, a circuit comprising drain current bump filter can be used to provide a method of deadtime optimization.

[0050] For example, a method of controlling deadtime for a half bridge or full bridge switch topology comprising a driver, wherein high side and low side switches comprise GaN transistors, comprises:

receiving a first input comprising a low-side drain current signal I.sub.D;
receiving a second input indicative of a bulk voltage V.sub.dc;
generating a current difference signal I.sub.D-I.sub.LOAD, where I.sub.LOAD is a load current;
integrating the current difference signal I.sub.D-I.sub.LOAD over a time interval of t.sub.2-t.sub.1 during voltage commutation to generate a current charge output

∫.sub.t.sub.1.sup.t.sup.2(I.sub.D(t)-I.sub.LOAD)dt;

based on the voltage Va.sub.c obtaining a reference current charge C.sub.oss for the high side switch

∫.sub.0.sup.V.sup.dcC.sub.oss(V.sub.DS)dV.sub.DS 0<V.sub.DS<V.sub.dc; t.sub.1<t<t.sub.2;

comparing the current charge output and the reference current charge C.sub.oss, and generating a deadtime adjust output signal;
outputting the deadtime adjust signal to the driver.

[0051] For example, the deadtime adjust signal may be used to reduce or optimize deadtime to reduce deadtime losses, while avoiding cross-conduction. If cross-conduction is occurring, the current charge output will be significantly greater than the reference current charge C.sub.oss, and the deadtime adjust signal can be used to increase deadtime, or other operating parameters, can be changed, to avoid cross-conduction. If cross-conduction is not occurring, the current charge output will be close to, or ideally will match, the reference current charge C.sub.oss. For example, if cross-conduction is not occurring, the measured drain bump area is closely matches the theoretical C.sub.oss charge amount, and the deadtime may be adjusted to reduce the deadtime, and thereby reduce deadtime losses. If cross-conduction is occurring, the deadtime may be increased, or e.g. the V.sub.gs_off is adjusted.

[0052] For example, a GaN half-bridge may comprise a current sense output for sensing the drain current ID, and a deadtime optimization circuit comprises a drain current bump filter for generating a current charge output; and circuit elements for comparing the current charge output to a reference current charge C.sub.oss and generating a deadtime adjust signal. Current sensing may be based on any appropriate type of current sense circuit, e.g. resistive or inductive, or it may be a current sense output pin of the GaN device.

[0053] For example, FIG. 12 shows a functional block diagram of power switching system comprising GaN half-bridge comprising a circuit for implementing a method of deadtime optimization of an example embodiment, based on measuring a current bump during voltage commutation. The high-side and low-side switches comprise GaN transistors. The circuit for controlling deadtime for the half-bridge comprises:

an input for receiving the low-side drain current I.sub.D;
an input for sensing the bulk voltage V.sub.dc;
a unit for generating a current difference signal I.sub.D-I.sub.LOAD, where I.sub.LOAD is a load current;
a timer for recording and counting the deadtime;
an integrator for integrating the current difference signal I.sub.D-I.sub.LOAD over a time interval of t.sub.2-t.sub.1 during voltage commutation to generate a current charge output

∫.sub.t.sub.1.sup.t.sup.2(I.sub.D(t)-I.sub.LOAD)dt;

a reference source for obtaining a reference current charge C.sub.oss based on V.sub.dc;
deadtime adjustment circuitry for receiving the current charge output from the integrator,
comparing the current charge output with the reference current charge C.sub.oss, and generating a deadtime adjust signal;
an output for outputting the deadtime adjust signal to the driver.

[0054] For example, the unit for generating a current difference signal I.sub.D-I.sub.LOAD may be a DC blocking unit or a subtractor. The integrator may be an analog integrator or a digital integrator. For example, the reference source may provide real-time calculation of the reference current charge C.sub.oss, or real-time adjustment of a reference current charge C.sub.oss, or the reference source may perform an offline look-up from a table of reference current charge values. For example, the reference current charge can be obtained from calculation, and adjusted internally or externally in real-time, or obtained from an off-line look-up table, based on a sensed bulk voltage V.sub.dc (V.sub.bulk). The reference source or reference generation unit provides the reference current charge, which would be a constant value for the selected GaN transistors, based on the selected bulk voltage V.sub.dc.

[0055] If the measured current charge matches the reference current charge C.sub.oss, there is no cross-conduction. For example, the deadtime adjustment circuitry may comprise a comparator.

[0056] To perform deadtime optimization, the timer is used to keep decreasing the dead time between the high-side and low-side GaN switches until the measured current charge exceeds the reference current charge C.sub.oss. E.g. a minimum deadtime is selected which avoids cross-conduction, while minimizing deadtime and therefore minimizing deadtime losses.

[0057] FIG. 13 shows a flowchart to illustrate steps of a method of deadtime optimization of an example embodiment.

[0058] Methods and circuits of example embodiments for implementing the method use the drain current bump area during voltage commutation to diagnose and avoid cross-conduction, and adjust the deadtime accordingly to minimize deadtime losses, while avoiding cross conduction. Deadtime optimization circuits of example embodiments are applicable to GaN half-bridge and GaN full-bridge switch topologies.

[0059] Methods and circuits of example embodiments may provide for e.g. cycle-by-cycle (fast) implementation of deadtime optimization; implementation which provides periodic ongoing measurement and adjustment for deadtime optimization, or one time implementation, e.g. at the factory or on initial power-up. Although the Qoss bump should not change significantly with load, line, temperature or lifetime, for some applications, it may be beneficial to make periodic adjustments of deadtime, e.g. over an operational lifetime or upon a diagnostic command from field service, or based on a periodic DSP command.

[0060] Reference is made to an article by Y. Qiu, J. Vanderkloot, R. Hou and J. Lu, “Diagnosing for Cross-conduction in GaN Half-Bridge,” 2020 IEEE Applied Power Electronics Conference and Exposition (APEC), New Orleans, LA, USA, 2020, pp. 2577-2583, doi: 10.1109/APEC39645.2020.9124086, which is incorporated herein by reference.

[0061] Although embodiments of the invention have been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only and not to be taken by way of limitation, the scope of the present invention being limited only by the appended claims.