Methods and systems for high bandwidth communications interface

Abstract

A pair of ground planes arranged in parallel, a dielectric medium disposed in between the pair of ground planes, and a set of at least four signal conductors disposed in the dielectric medium, the set of at least four signal conductors having (i) a first pair of signal conductors arranged proximate to a first ground plane of the pair of ground planes and (ii) a second pair of signal conductors arranged proximate to a second ground plane of the pair of ground planes, each signal conductor of the set of at least four signal conductors configured to carry a respective signal corresponding to a symbol of a codeword of a vector signaling code.

Claims

1. A method comprising obtaining a plurality of signals via a plurality of signal conductors embedded in a dielectric medium, the plurality of signal conductors having pairs of equidistant signal conductors that are adjacent to respective ground planes of a pair of ground planes arranged in parallel; generating a plurality of outputs, each output associated with a respective transmission mode of a plurality of transmission modes, wherein the plurality of outputs are formed based on comparisons between pair-wise combinations of signals of the obtained plurality of signals, wherein the pair-wise combinations of signals comprises (i) pair-wise combinations of signals obtained from pairs of horizontally-proximate signal conductors, (ii) pair-wise combinations of signals obtained from pairs of vertically-proximate signal conductors, and (iii) pair-wise combinations of signals obtained from pairs of diagonally-proximate signal conductors.

2. The method of claim 1, wherein the plurality of signals are balanced.

3. The method of claim 1, wherein the pair of ground planes arranged in parallel are connected by conductive vias.

4. The method of claim 1, wherein the plurality of transmission modes are defined by an orthogonal matrix.

5. The method of claim 4, wherein the orthogonal matrix is a Hadamard matrix of size four.

6. The method of claim 5, wherein the plurality of signals correspond to codewords of a vector signaling code comprising all permutations of {+1, −⅓, −⅓, −⅓} and {−1, ⅓, ⅓, ⅓}.

7. The method of claim 1, wherein the pairs of equidistant signal conductors have periodic horizontal offsets along a length of the dielectric medium.

8. An apparatus comprising a plurality of signal conductors embedded in a dielectric medium, the plurality of signal conductors comprising pairs of equidistant signal conductors that are adjacent to respective ground planes of a pair of ground planes arranged in parallel, each signal conductor of the plurality of signal conductors carrying a respective signal of a plurality of signals; a plurality of multi-input comparators (MICs) configured to generate a plurality of outputs, each MIC of the plurality of MICs connected to the plurality of signal conductors and associated with a respective transmission mode of a plurality of transmission modes, the plurality of MICs configured to generate the plurality of outputs based on comparisons between pair-wise combinations of signals of the plurality of signals, wherein the pair-wise combinations of signals comprises (i) pair-wise combinations of signals obtained from a pair of horizontally-proximate signal conductors, (ii) pair-wise combinations of signals obtained from a pair of vertically-proximate signal conductors, and (iii) pair-wise combinations of signals obtained from a pair of diagonally-proximate signal conductors.

9. The apparatus of claim 8, wherein the plurality of signals are balanced.

10. The apparatus of claim 8, wherein the pair of ground planes arranged in parallel are connected via conductive vias.

11. The apparatus of claim 8, wherein the plurality of transmission modes are defined by an orthogonal matrix.

12. The apparatus of claim 11, wherein the orthogonal matrix is a Hadamard matrix of size four.

13. The apparatus of claim 12, wherein the plurality of signals correspond to codewords of a vector signaling code comprising all permutations of {+1, −⅓, −⅓, −⅓} and {−1, ⅓, ⅓, ⅓}.

14. The apparatus of claim 8, wherein the pairs of equidistant signal conductors have periodic horizontal offsets along a length of the dielectric medium.

15. The apparatus of claim 8, wherein the plurality of signal conductors are arranged in a square in the dielectric medium.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Various embodiments in accordance with the present disclosure will be described with reference to the drawings. Same numbers are used throughout the disclosure and figures to reference like components and features.

(2) FIG. 1 is a block diagram of an example system comprising a transmitting device, interconnection, and receiving device, in accordance with at least one embodiment of the invention.

(3) FIG. 2 shows several physical channel topologies suited for use with the described signal coding in at least one embodiment in accordance with the invention.

(4) FIGS. 3A and 3B illustrate different transmission modes in differential and H4 encoded communications.

(5) FIG. 4 is a block diagram of a H4 encoder and transmitter of the FIG. 1 system, in accordance with at least one embodiment of the invention.

(6) FIGS. 5A and 5B show block diagrams for the receiver and H4 decoder components of the FIG. 1 system utilizing a single process phase and multiple processing phases, in accordance with at least one embodiment of the invention.

(7) FIG. 6 is a chart shown example transmit wire values for each transmit data value, and corresponding example receive comparator outputs and receive data words, in accordance with at least one embodiment of the invention.

(8) FIGS. 7A and 7B show block diagrams of receivers incorporating two approaches to DFE compensation, in accordance with at least one embodiment of the invention.

(9) FIGS. 8A and 8B show individual wire signals of a transmitted H4 code and the combined signaling of all wires depicting the use of two of the four signal levels per transmit interval, in accordance with at least one embodiment of the invention.

(10) FIG. 9 is a block diagram illustrating a method, in accordance with some embodiments.

DETAILED DESCRIPTION

(11) Despite the increasing technological ability to integrate entire systems into a single integrated circuit, multiple chip systems and subsystems retain significant advantages. The physical infrastructure to support high-bandwidth chip-to-chip connectivity is available, if the power, complexity, and other circuit implementation issues for such interfaces could be resolved.

(12) For purposes of description and without limitation, example embodiments of at least some aspects of the invention herein described assume a systems environment of (1) at least one point-to-point communications interface connecting two integrated circuit chips representing a transmitter and a receiver, (2) wherein the communications interface is supported by an interconnection group of four high-speed transmission line signal wires providing medium loss connectivity at, as an example, 18.75 GHz (37.3 GigaSymbols/second) without excessive ripple loss characteristics or reflections, (3) the interconnection group of signal wires displaying low intra-ensemble skew, and (4) the communications interface operating at the example signaling rate of 37.3 GigaSymbols/second, delivering an aggregate throughput of approximately 112 gigabits/sec over the four wire circuit.

(13) As subsequently described, at least one embodiment of the invention uses low signal swing current mode logic pin drivers and interconnection wiring terminated at both transmitter and receiver.

(14) Physical Channel Wiring

(15) Several example physical channel topologies in accordance with at least one embodiment of the invention are shown in FIG. 2.

(16) Example configuration 201 illustrates in cross-section a quad-box stripline, with four signal conductors 202 embedded in dielectric medium 203 between ground planes 204. In some embodiments, vias 205 are incorporated to interconnect ground planes 204. In some embodiments, the locations of signal conductors 202 are modified by introducing periodic horizontal position offsets so as to provide more uniform characteristics for the four signal paths. As one example, the upper two signal conductors of 202 may be shifted left as the lower two signal conductors of 202 are simultaneously shifted right as illustrated in 210, and then the direction of these shifts reversed on each subsequent offset cycle, with the period and extent of the offsets chosen to provide more uniform characteristics for the four signal paths.

(17) Example configuration 211 illustrates in cross-section a quadax cable, with four signal conductors 212 embedded in dielectric medium 213 surrounded or essentially surrounded by conductive shield 214. The external profile of the dielectric medium and conductive shield will in practice be a balance between manufacturing simplicity (e.g. a round profile as in conventional coax cable) and optimized transmission characteristics (e.g. the square or rectangular shape of 201) as is suggested by the profile provided for illustrative purposes at 214. As with the previous example, periodic perturbations of the inter-wire spacing of conductors 212 and/or their locations may be made to provide more uniform characteristics for the four signal paths.

(18) Example configuration 221 shows a twisted quad cable, where individually insulated signal conductors 222 are twisted as a group around a common axis, either with or without a central insulating strand 223 to control overall diameter and spacing. Some embodiments may further optionally incorporate at least one of a central conductive neutral wire, surrounding insulation layer, and surrounding conductive shield layer to allow additional control over impedance characteristics and/or noise isolation.

(19) It will be apparent to one familiar with the art that each example of FIG. 2 utilizes three-dimensional structuring of signal conductors to provide essentially equal impedance characteristics for each of the four signal wires, and also essentially equal inter-wire coupling characteristics among the four signal wires. These characteristics facilitate signal propagation modes providing effectively equal propagation velocity for signals on each wire, as well as effectively equal attenuation and frequency response characteristics. Comparable transmission characteristics may also be provided by other known cable designs, including braid twisted quad conductor cable, quad micro-coax cable, etc.

(20) Other known cable designs including quad microstripline, dual pair microstripline, and dual twisted pair may also be usable with the described invention under some conditions. With such cables, not all signal propagation modes for the subsequently described H4 coded signals are identical, typically with one of the three major propagation modes experiencing reduced receive signal levels and slower propagation velocity. Some embodiments of the invention provide compensation for these effects through additional amplification of received signals of the degraded mode and delayed sampling of that mode's received signal values. Other embodiments provide a legacy communication capability, where signals are communicated using conventional dual differential transmission and reception, with reduced aggregate communications throughput.

(21) Example signal levels, signal frequencies, and physical dimensions described herein are provided for purposes of explanation, and are not limiting. Other embodiments of the invention may utilize different signaling levels, connection topology, termination methods, and/or other physical interfaces, including optical, inductive, capacitive, or electrical interconnection. Similarly, examples based on unidirectional communication from transmitter to receiver are presented for clarity of description; combined transmitter-receiver embodiments and bidirectional communication embodiments are also explicitly in accordance with the invention.

(22) Encoding Information Using Hadamard Transforms

(23) The Hadamard Transform, also known as the Walsh-Hadamard transform, is a square matrix of entries +1 and −1 so arranged that both all rows and all columns are mutually orthogonal. Hadamard matrices are known for all sizes 2N as well as for selected other sizes. In particular, the descriptions herein rely on 2×2 and 4×4 Hadamard matrices.

(24) The order 2 Hadamard matrix is:

(25) $\begin{array}{cc}{H}_2=\left[\begin{array}{cc}1& 1\\ 1& -1\end{array}\right]& \left(\mathrm{Eqn}.1\right)\end{array}$
and conventional differential encoding of one bit A may be obtained by multiplying A by the Hadamard matrix H.sub.2 to obtain values for the resulting output signals W and X. It will be apparent to one familiar with the art that multiplication times the upper vector of the matrix corresponds to introduction of a positive or negative common-mode signal onto W and X, a transmission mode not generally used in practice on differential circuits, while multiplication times the lower vector of the matrix produces the familiar differential signals of {+1, −1} for A positive, and {−1, +1} for A negative. This is illustrated in FIG. 3A, where the two signal lines 301 and 302 representing the signals W and X carry the encoded transmission mode 303 representing the {+1, −1} vector multiplied by the encoded bit A.

(26) The order 4 Hadamard matrix is:

(27) $\begin{array}{cc}{H}_4=\left[\begin{array}{cccc}+1& +1& +1& +1\\ +1& -1& +1& -1\\ +1& +1& -1& -1\\ +1& -1& -1& +1\end{array}\right]& \left(\mathrm{Eqn}.2\right)\end{array}$
and encoding of the three bits A, B, C may be obtained by multiplying those bits times the Hadamard matrix H.sub.4 to obtain four output values. As in the previous example, the uppermost vector corresponds to common mode signaling, which is not used herein, with the next three vectors being used to encode bits A, B, and C respectively into outputs W, X, Y, Z. This is graphically illustrated in FIG. 3B, where the four signal line 311, 312, 313, and 314 represent the signals W, X, Y, Z respectively in each illustration, with the three illustrations representing the three distinct transmission modes representing the bit A multiplied by the vector {+1, −1, +1, −1} at 320, the bit B multiplied by the vector {+1, +1, −1, −1} at 330, and the bit C multiplied by the vector {+1, −1, −1, +1} at 340.

(28) As in the example of FIG. 3A, the ovals in FIG. 3B identify signal pairs carrying opposing values. However, unlike in the previous example where only one transmission mode 303 was available for use, in the example of FIG. 3B each of the three illustrated modes 320, 330, and 340 may be used simultaneously to transmit A, B, and C. Thus, the observed signal levels on W, X, Y, Z used in such manner correspond to the sums of the three modes.

(29) One familiar with the art will note that all possible values of A, B, C encoded in this manner result in mode summed values for W, X, Y, Z which are balanced; that is, summing to the constant value zero. If the mode summed values for W, X, Y, Z are scaled such that their maximum absolute value is 1 (that is, the signals are in the range +1 to −1 for convenience of description,) it will be noted that all achievable values are permutations of the values {+1, −⅓, −⅓, −⅓} or of the values {−1, ⅓, ⅓, ⅓}. These are called the code words of the vector signaling code H4.

(30) H4 Code

(31) As used herein, “H4” code, also called Ensemble NRZ code, refers to a vector signaling code and associated logic for such code wherein a transmitter consumes three bits and outputs signals on four wires in each symbol period. In some embodiments, parallel configurations comprising more than one group may be used, with each group comprising three bits transmitted on four wires per symbol period and an H4 encoder and an H4 decoder per group. With an H4 code, there are four signal wires and four possible coordinate values, represented herein as +1, +⅓, −⅓, and −1. The H4 code words are balanced, in that each code word is either one of the four permutations of (+1, −⅓, −⅓, −⅓) or one of the four permutations of (−1, +⅓, +⅓, +⅓), all such permutations summing to the equivalent of a zero value. H4 encoded signal waveforms are shown in FIG. 8A. It should be noted that although the constellation of all code words utilizes four distinct signal levels, only two signal levels will be utilized in any one code word, as is illustrated by a superposition of all four signal waveforms, as shown in FIG. 8B.

(32) In a specific embodiment, a +1 might be sent as a signal using an offset of 200 mV, while a −1 is sent as a signal using an offset of −200 mV, a +⅓ is sent as a signal using an offset of 66 mV, and a −⅓ is sent as a signal using an offset of −66 mV, wherein the voltage levels are with respect to a fixed reference. Note that the average of all of the signals sent (or received, disregarding asymmetric effects of skew, crosstalk, and attenuation) in any single time interval regardless of the code word represented is “0”, corresponding to the offset voltage. There are eight distinct code words in H4, which is sufficient to encode three binary bits per transmitted symbol interval.

(33) Other variants of the H4 coding described above exist as well. The signal levels are given as examples, without limitation, and represent incremental signal values from a nominal reference level.

(34) Encoder and Transmitter

(35) FIG. 4 is a block diagram for one embodiment of the H4 encoder and transmitter components of the FIG. 1 system in accordance with the invention. This embodiment uses source- and destination-terminated current mode logic drivers with reduced signal swing.

(36) High-speed communications embodiments often exceed the performance capabilities of a single communications circuit instance. As an example of how such a limitation is overcome, FIG. 4 shows as an example a 4:1 mux architecture that supports a line rate of as much as 4× the capabilities of a single circuit instance in the same process technology. Each of the processing stages 420 and 430 are embodied as four distinct instances, each instance processing source data into symbol data for one transmission interval. Any number of phases may be used, from a single phase performing all operations, to sixteen or more, with each of such multiple phases possibly also extending over a greater or lesser portion of the described transmission system than this example.

(37) In one embodiment in accordance with the invention, source data, which may be subjected to scrambling, encryption, or encapsulation beyond the scope of this disclosure, is provided at 405. Multiplexer 410 sequentially distributes consecutive source data elements to the four encoding phases, and multiplexer 440 sequentially combines the resulting four encoded results into a single data stream for transmission. One embodiment accepts source data in twelve bit increments, which is then distributed as four three-bit portions to the four processing phases, and subsequently combined to produce the higher rate transmitted stream. Each H4 encoder 420 maps three bits of user data to one H4 code word, with the results buffered in flip-flops 430. At each symbol interval, one buffered H4 code word is selected, and then converted to the chosen wire signal levels by line drivers 450 for transmission on interconnection 460. This allows for transmission rates to be multiples of the processing rates of a single encoder or decoder.

(38) The specific mapping function between three bits of source data and a specific H4 code word may be chosen for implementation convenience, as will be subsequently described.

(39) Receiver and Decoder

(40) The complementary receiver and decoder for the described H4 transmitter system perform a number of operations. The interconnection wires are terminated in a matched impedance, conventional amplification and filtration may be applied to compensate for channel attenuation, received signal levels corresponding to the symbol representations of the H4 code are measured, symbols interpreted as valid code words of the H4 code, and the detected code words mapped back to received data.

(41) At least one embodiment in accordance with the invention combines at least some aspects of these receiver and decoder operations for efficiency. One embodiment in accordance with the invention shown in FIGS. 5A and 5B incorporate a differential comparator circuit operating on multiple inputs, summing the received signal values on two selected wires, summing the received signal values on the remaining two wires, and outputting a comparison of the two summed results. Such a multi-input comparator requires no fixed signal level reference and can provide a good level of common-mode noise rejection, in a circuit combining elements of line receiver and H4 code word detection operations. At least one embodiment in accordance with the invention further incorporates line equalization and amplification with the line receiver and code word detection operations.

(42) Three instances of such multi-input comparator circuits operating on permutations of the same four input signals are sufficient to detect all code words of H4. That is, given a multi-input comparator that performs the operation
R=(J+L)−(K+M)  (Eqn. 3)
where J, K, L, M are variables representing the four input signals values, then as one example and without limitation, the input permutations producing the three results R.sub.0, R.sub.1, R.sub.2 based on the equations
R.sub.0=(W+Y)−(X+Z)  (Eqn. 4)
R.sub.1=(Y+Z)−(W+X)  (Eqn. 5)
R.sub.2=(Y+X)−(Z+W)  (Eqn. 6)
are sufficient to unambiguously identify each code word of vector signaling code H4 as represented by receive signal input values W, X, Y, Z. The values R.sub.0, R.sub.1, R.sub.2 may represent analog signal results if both the addition and difference functions are performed linearly, or may represent binary outputs if the difference function is performed by a digital comparator, equivalent to performing a sign( ) function on analog outputs. Because of the nature of the encoded H4 code words, none of the analog results R.sub.0, R.sub.1, R.sub.2 will be at zero, implying that none of the corresponding digital comparator results will be ambiguous.

(43) For some encoder mappings of source data to transmitted H4 code words, a direct relationship between the detected result of these three receive comparators and the receive data exists, eliminating the need for additional decode mapping logic at the receiver. Thus, a preferred embodiment will first select the desired permutations of input signals to be processed by each of the three multi-input receive comparators, will then document the three comparator output values obtained for each valid code word, and will then define a transmit mapping function that performs the corresponding mapping of three transmit data bits to the four transmit signal values of the corresponding code word. One example of such a mapping is shown in FIG. 6.

(44) FIG. 5A shows a block diagram of such a receiver for a group of four wires using the H4 code. Each receive interconnection line 505 is terminated at 510. In some embodiments, line termination may further incorporate overvoltage protection, DC blocking capacitors, and introduction of a common mode or bias voltage for subsequent processing stages. Terminated receive signals 515 are presented to multi-input comparators 520, which perform the H4 detection by performing summation 521 and difference or comparison 522 operations. In this example, a direct mapping of comparator outputs to received data 525 is shown.

(45) As with the described transmitter example, multiple processing phases may be used to allow symbol signaling rates greater than might be supported by a single circuit instance in the available semiconductor technology. FIG. 5B illustrates multi-phase receive processing, with an example four phase embodiment of receive comparator subsystem 524. To show the transparent nature of the multi-phase processing technique, the example portion 524 of FIG. 5A may be replaced by the four phase embodiment of FIG. 5B, retaining common inputs 515 and outputs 525.

(46) As shown in FIG. 5B, terminated receive signals 515 are captured by sample-and-hold 530, providing stable signal levels 535 as inputs to each of the example four processing phases 540. To provide the maximum processing time to each processing phase 540 (which in this example is comprised of the receive comparator component 520 of FIG. 5A), one sample-and-hold per input signal is provided per phase (thus, in this example, sixteen total) with each operating at one quarter the receive symbol rate. Detected results 545 from all phases are combined by multiplexer 550 into a combined received data stream equivalent to that of FIG. 5A. Other embodiments may incorporate different numbers of phases and/or different numbers of sample-and-hold elements providing different timing constraints, and may incorporate greater or lesser amounts of the receive system into the multiple processing phases.

(47) H4 Code with Digital Feedback Equalization

(48) Modern high-speed serial receiver designs are strongly reliant on Decision Feedback Equalization (DFE) methods, which are well known solutions for compensation of transmission medium perturbations including signal reflections and crosstalk. It had been observed that such perturbations are driven by delayed components of previously transmitted data (e.g. as delayed reflections from impedance discontinuities in the communications path) which interfere with subsequently transmitted data. Thus, detected data may be stored by a DFE system at the receiver, and suitably delayed and attenuated components subtracted from the current input signal so as to nullify those effects.

(49) This simple feedback loop DFE is constrained by the need to fully detect the value of the currently received data bit in time to feed it back as compensation for signals in the next signal interval. As transmission rates increase, this window of time becomes smaller. Furthermore, distributing receive processing across multiple processing phases increases throughput, at the cost of latency. Thus, information about a given receive interval's data may not be available for many receive cycles. Solutions using “unrolled” DFE correction are known, allowing inline compensation to be performed for the critical initial receive intervals of the DFE process.

(50) Classic binary DFE solutions may be combined with the described H4 receiver designs at the point where individual modulation modes (representing individual data bits) are detected, if the signal reflections requiring compensation are similar for the four signal paths. Each mode is communicated as signals over all four signal paths, but the combinations of such signals is by definition orthogonal for each mode, thus signal perturbations on distinct paths is possible through judicious combination of modal compensations. It should be noted that signals encoded on the wire may take on any of four values (albeit two at any one time) while signals representing each transmission mode are always two-valued. Thus, storage and delay components of a DFE are at least twice as complex if performed on wire signals versus modulation mode signals.

(51) One embodiment in accordance with the invention is shown in the block diagram of FIG. 7A. The four receive signal inputs 701 are input to receive detector 524 (previously described in FIGS. 5A and 5B), which in this example is configured to produce three analog outputs 705 corresponding to the transmission modes used to communicate each data bit. On each such analog output, a DFE correction signal 735 from one of three binary DFE circuits 730 is summed 710 to nullify the signal distortions on that analog signal, and the signals optionally converted to digital value by comparators 740.

(52) As is well known to those familiar with the art, the required high gain of a digital comparator is often obtained using a series of stages of moderate gain. External signals may be injected at an interconnecting circuit node between two such stages; in one common example, an adjustable DC level is introduced at such a node to correct the comparator's input balance or offset. In another embodiment, elements 710 and 740 may thus represent stages within a multi-input comparator as in 520 of FIG. 5A. One familiar with the art will observe that a DFE correction signal may also be introduced at other circuit nodes, as one example at a comparator input, providing equivalent functionality.

(53) As is common practice, the Decision Feedback Equalization corresponding to at least the first several bit times preceding the current receive interval are “unrolled” or performed inline along with the data path processing for higher performance, rather than by a closed loop feedback method, by the three unrolled binary DFE circuits 720, with DFE corresponding to the remaining bit times being compensated being performed by conventional feedback loop DFE at 730.

(54) In the embodiment shown, feedback DFE circuits 730 accept digital bit inputs and output appropriately scaled and delayed analog signals, while unrolled DFE circuits 720 accepts digital inputs and produces digital bit outputs. Other embodiments in accordance with the invention may utilize different combinations of input signals and output results in the DFE components. In one embodiment, the three DFE circuits 730 operate on analog values 725, rather than from the equivalent binary values 745 obtained from comparators 740.

(55) An alternative and more complex DFE embodiment of the invention is also known, which may be applied if the reflections are markedly different amongst the four wires. In this approach shown in FIG. 7B, DFE is performed by adding 760 four DFE correction signals 755, one for each analog wire signal 751 rather than for each transmission mode, allowing independent equalization for each physical wire path at the cost of significantly greater complexity and power consumption. The compensated wire signals are processed by receive detector 524 to produce outputs 765. In such an embodiment, at least the first several bits may be equalized by an unrolled binary DFE 770 operating on the three individual modulation modes as before. For corrections beyond that amount, an enhanced architecture DFE is used. The three data outputs 795 are re-encoded 790 into the corresponding four level symbol representation 736 used on the line, and four four-level DFE circuits 790 perform the remainder of the equalization, each operating on one wire-level signal to produce compensation signals 755. In some embodiments, the function of digital comparators 782 are performed within DFE 770, so that outputs 775 are equivalent to outputs 795. Similarly, in at least one embodiment unrolled DFE 770 operates on digital output signals from receive detector 524 representing binary data bits.

(56) The number of bits of DFE compensation utilized in either described embodiment of the invention, both as inline “unrolled” DFE and as conventional feedback DFE, may be chosen based on the needs of the specific communications system, without limitation. At least one embodiment in accordance with the invention includes at least some DFE operations within the multiphase processing portion of the receiver.

(57) Receive Method Description

(58) To summarize and clarify the previous descriptions of receiver operations and their interactions with receive mode DFE and/or receive signal DFE, the following descriptions are made using the diagram of FIG. 9.

(59) In element 910, signals from the separate channels of the communications medium are received, obtaining channel signal values representing the signal of each channel.

(60) In some embodiments, additional processing including amplification, filtering, and frequency-dependent amplification may be performed on the signals of each channel as part of obtaining channel signal values, as is common practice. In some embodiments, correction signals derived from past channel activity are incorporated in this additional processing, as one example to neutralize past signal reflections and other spurious communications channel effects. Such correction based on past activity is known as Decision Feedback Equalization, herein being applied to channel signals.

(61) In element 920, elements of the vector signaling code are detected by a method comprising obtaining a first sum of two selected channel signal values, obtaining a second sum of the remaining two channel signal values, and comparison of the first sum and the second sum to obtain the detected element. Multiple elements are detected by choosing different selected channel signal values for each element; for the example H4 vector signaling code, three such elements may be detected by three different permutations of channel signal values used to produce a first sum and a second sum.

(62) In some embodiments, correction signals derived from previously detected elements of the vector signaling code are incorporated into detection of current elements of the vector signaling code, as one example in an alternative method of neutralizing past signal reflections and other spurious communications channel effects. As examples, a correction signal representing a compensation for past signal reflections and other spurious communication channel effects impacting one or more particular modulation modes may be introduced into element detection, so as to modify inputs to the comparison, or to bias the comparison operation itself. Such correction based on past activity is known as Decision Feedback Equalization, herein being applied to modulation modes of the communications channel.

(63) In element 920, elements of the vector signaling code are detected by a method comprising obtaining a first sum of two selected channel signal values, obtaining a second sum of the remaining two channel signal values, and comparison of the first sum and the second sum to obtain the detected element. Multiple elements are detected by choosing different selected channel signal values for each element; for the example H4 vector signaling code, three such elements may be detected by three different permutations of channel signal values used to produce a first sum and a second sum.

(64) In element 930, received data derived from the detected elements of the vector signaling code are output. As previously described, in preferred embodiments the transmit encoding is chosen such that the detected elements of the vector signaling code directly correspond to bits of the received data.

(65) The described method thus measures and acts upon physical signal inputs, and produces a physical result of received data, which may be acted upon by subsequent components of a larger system or process.

(66) The examples presented herein illustrate the use of vector signaling codes for point-to-point chip-to-chip interconnection. However, this should not been seen in any way as limiting the scope of the described invention. The methods disclosed in this application are equally applicable to other interconnection topologies and other communication media including optical, capacitive, inductive, and wireless communications. Thus, descriptive terms such as “voltage” or “signal level” should be considered to include equivalents in other measurement systems, such as “optical intensity”, “RF modulation”, etc. As used herein, the term “physical signal” includes any suitable behavior and/or attribute of a physical phenomenon capable of conveying information. Physical signals may be tangible and non-transitory.