Abstract
A complementary circuit, including a logic unit which includes pull-up depletion-mode MOS transistors and pull-down depletion-mode MOS transistors and a level shifting circuit coupled to the logic unit.
Claims
1. A complementary circuit, comprising: a logic unit configured to provide a logic function and a digital operation, the logic unit comprising pull-up depletion-mode circuit MOS transistors and pull-down depletion-mode MOS transistors, the logic unit including a digital switch; and a level shifting circuit including diodes which are implemented by a circuitry arrangement of a heterojunction field-effect transistor (HJFET) device, wherein an input and an output of the level shifting circuit comprise complementary signals, wherein the depletion-mode MOS devices and the HJFET devices are monolithically integrated, wherein the logic unit and the level shifting circuit comprise a first capacitor and a second capacitor which are implemented by a circuitry arrangement of the depletion-mode MOS transistors, and wherein, the level shifter operates in a first phase and a second phase such that: in the first phase: the first capacitor is charged to a first value while the second capacitor is discharged; and in the second phase: the first capacitor is connected to the second capacitor and by preservation of charge, the second capacitor is charged to a predetermined value.
2. The complementary circuit of claim 1, wherein input signals applied to gates of the pull-up depletion-mode MOS transistors are complementary to input signals applied to gates of the pull-down depletion-mode MOS transistors.
3. The complementary circuit of claim 1, wherein the level shifting circuit comprises depletion-mode MOS transistors having a single channel conductivity type and at least one diode.
4. The complementary circuit of claim 1, wherein the level shifting circuit shifts an output voltage range of the logic unit to a same range as an input voltage range of the logic unit.
5. The complementary circuit of claim 1, wherein the level shifting circuit comprises diodes which are implemented by a circuitry arrangement of heterojunction field-effect transistor (HJFET) devices.
6. The complementary circuit of claim 1, wherein the level shifting circuit is coupled to the logic unit.
7. The complementary circuit of claim 1, wherein the pull-up and pull-down transistors include a single channel conductivity type including negative threshold voltages.
8. The complementary circuit of claim 1, wherein the pull-up and pull-down transistors are both n-channel or are both p-channel.
9. The complementary circuit of claim 1, wherein, in the first phase, V.sub.X is a first value and V.sub.x is a second value less than the first value, and wherein, in the second phase, the second value of V.sub.x is greater than the first value of V.sub.X.
10. A system, comprising: a circuit comprising a heterojunction field-effect transistor (HJFET) device and a depletion-mode MOS device; and a complementary circuit coupled to the circuit, the complementary circuit including: a logic unit configured to provide a logic function and a digital operation, the logic unit comprising pull-up depletion-mode MOS transistors and pull-down depletion-mode MOS transistors, the logic unit including a digital switch; and a level shifting circuit including diodes which are implemented by a circuitry arrangement of the heterojunction field-effect transistor (HJFET) device, wherein an input and an output of the level shifting circuit comprise complementary signals, wherein the depletion-mode MOS devices and the HJFET devices are monolithically integrated, wherein the logic unit and the level shifting circuit comprise a first capacitor and a second capacitor which are implemented by a circuitry arrangement of the depletion-mode MOS transistors, and wherein, the level shifter operates in a first phase and a second phase such that: in the first phase: the first capacitor is charged to a first value while the second capacitor is discharged; and in the second phase: the first capacitor is connected to the second capacitor and by preservation of charge, the second capacitor is charged to a predetermined value.
11. The system of claim 10, wherein input signals applied to gates of the pull-up depletion-mode MOS transistors are complementary to input signals applied to gates of the pull-down depletion-mode MOS transistors.
12. The system of claim 10, wherein the level shifting circuit comprises depletion-mode MOS transistors having a single channel conductivity type and at least one diode.
13. The system of claim 10, wherein the level shifting circuit shifts an output voltage range of the logic unit to approximately a same range as an input voltage range of the logic unit.
14. The system of claim 10, wherein the level shifting circuit comprises diodes which are implemented by a circuitry arrangement of heterojunction field-effect transistor (HJFET) devices.
15. The system of claim 10, wherein the level shifting circuit shifts an output voltage range of the logic unit to a same range as an input voltage range of the logic unit.
16. The system of claim 10, wherein the level shifting circuit is coupled to the logic unit.
17. An active matrix display, comprising: a row driver implemented using a complementary circuit, the complementary circuit including: a logic unit configured to provide a logic function and a digital operation, the logic unit comprising pull-up depletion-mode MOS transistors and pull-down depletion-mode MOS transistors, the logic unit including a digital switch; and a level shifting circuit including diodes which are implemented by a circuitry arrangement of a heterojunction field-effect transistor (HJFET) device, wherein an input and an output of the level shifting circuit comprise complementary signals, wherein the depletion-mode MOS devices and the HJFET devices are monolithically integrated, wherein the logic unit and the level shifting circuit comprise a first capacitor and a second capacitor which are implemented by a circuitry arrangement of the depletion-mode MOS transistors, and wherein, the level shifter operates in a first phase and a second phase such that: in the first phase: the first capacitor is charged to a first value while the second capacitor is discharged; and in the second phase: the first capacitor is connected to the second capacitor and by preservation of charge, the second capacitor is charged to a predetermined value.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) Aspects of the invention will be better understood from the following detailed description of the exemplary embodiments of the invention with reference to the drawings, in which:
(2) FIGS. 1A-1C exemplarily depict inverter/buffer logic gates including at least one logic unit and a level shifter and a truth table thereof;
(3) FIGS. 2A-2B exemplarily depict an NOR/OR logic gate including at least one logic unit and a level shifter and a truth table thereof;
(4) FIGS. 3A-3B exemplarily depict an AND/NAND logic gate including at least one logic unit and a level shifter and a truth table thereof;
(5) FIG. 4 exemplarily depicts a level shifter according to one exemplary embodiment;
(6) FIGS. 5A-5D exemplarily depict level shifters according to a second exemplary embodiment;
(7) FIG. 6 exemplarily depicts a positive-edge-triggered D-Hip-Flop according to one exemplary embodiment;
(8) FIG. 7A exemplarily depicts a Hailey Simulation Program with Integrated Circuit Emphasis (HSPICE) simulation result of the level shifter according to FIGS. 4A-4B;
(9) FIG. 7B exemplarily depicts an HSPICE simulation result of the level shifter according to FIG. 5A;
(10) FIG. 7C exemplarily depicts an HSPICE simulation result of the level shifter according to FIG. 5D;
(11) FIG. 7D exemplarily depicts an HSPICE simulation result of the inverter logic gate of FIG. 1A;
(12) FIG. 7E exemplarily depicts an HSPICE simulation result of the NOR logic gate of FIG. 2A;
(13) FIG. 7F exemplarily depicts an HSPICE simulation result of the NAND logic gate of FIG. 3A; and
(14) FIG. 7G exemplarily depicts an HSPICE simulation result of the positive-edge-trigger D-Flip-Flop circuit of FIG. 6.
DETAILED DESCRIPTION
(15) The invention will now be described with reference to FIG. 1A-7G, in which like reference numerals refer to like parts throughout. It is emphasized that, according to common practice, the various features of the drawing are not necessarily to scale. On the contrary, the dimensions of the various features can be arbitrarily expanded or reduced for clarity.
(16) With reference now to the example depicted in FIG. 1A and FIG. 1B, a complementary circuit is exemplarily depicted which includes of at least one logic unit including pull-up and pull-down depletion-mode metal-oxide-semiconductor (MOS) transistors having a single channel type (i.e., either an n-channel or a p-channel). The input signals applied to the gates of the pull-up transistors are complementary to that applied to the gates of the pull-down transistors.
(17) As exemplary depicted in FIGS. 4A-5D, the complementary circuit includes a level shifting circuit including depletion-mode MOS transistors having a single channel type, and various diodes D.sub.1-D.sub.4 and capacitors C.sub.1-C.sub.3. The level shifting circuit shifts the output voltage range of the logic unit to about the same range as the input voltage range of the logic unit.
(18) The complementary circuits depicted in FIGS. 1A-5D can include diodes that are implemented by the circuitry arrangement of HJFET devices. A diode may be implemented by using the gate terminal of an HJFET as the first terminal of the diode, and using either or both the drain and source terminals of the HJFET as the second terminal of the diode. When both the drain and source terminals are used, they may be electrically connected to each other to form a single terminal. Also, the capacitors can be implemented by the circuitry arrangement of depletion mode MOS devices. A capacitor can be implemented by using the gate terminal of a depletion mode MOS transistor as the first terminal of the capacitor, and using either or both the drain and source terminals of the depletion mode transistor as the second terminal of the capacitor. When both the drain and source terminals are used, they may be electrically connected to each other to form a single terminal. However, a capacitor also can be formed monolithically from two (2) metal layers and at least one dielectric layer (i.e., an MIM capacitor), which may also include one or more layers of a doped semiconductor (e.g., a-Si:H). Further, the depletion-mode MOS and HJFET devices can be monolithically integrated (e.g. using the process examples as in the co-pending U.S. patent application Ser. No. 15/266,414).
(19) It is noted that the invention can include an active matrix display with a row driver implemented using the complementary circuitry depicted in FIGS. 1A-5D and an HJFET backplane where the row driver and the HJFET backplane are monolithically integrated (e.g. using the process examples as in the co-pending U.S. patent application Ser. No. 15/266,414).
(20) In one embodiment, an active matrix organic light-emitting diode (AMOLED) display can be disposed (implemented) on a flexible plastic substrate. The TFT backplane can include of HJFET devices enabling the high TFT stability required for driving the OLED. The row driver may include complementary circuits (e.g., as exemplarily depicted in FIGS. 1A-5D) which can be integrated monolithically with the backplane and the column driver CMOS chip can be attached to one side of the display panel.
(21) With reference again to FIGS. 1A-1B, the MOS transistors are depletion-mode. The MOS transistors exemplarily depicted are n-channel but p-channel transistors could be used as well. Further, the complementary circuits in FIGS. 1A-1B are configured such that V.sub.H>V.sub.DD−|V.sub.T|, V.sub.L<V.sub.SS−|V.sub.T| (note V.sub.T<0 for depletion-mode n-channel transistors). In a preferred embodiment, V.sub.H=V.sub.DD. FIG. 1C exemplarily depicts a truth table for the inverters depicted in FIGS. 1A-1B. It is noted that a buffer could be realized by interchanging the output terminals of the invertor exemplarily depicted in FIGS. 1A-1B.
(22) FIG. 2A exemplary depicts a complementary circuit of a NOR logic gate with FIG. 2B exemplarily depicting the truth table for the complementary circuit of FIG. 2A.
(23) FIG. 3A exemplary depicts a complementary circuit of an AND logic gate with FIG. 3B exemplarily depicting the truth table for the complementary circuit of FIG. 3A.
(24) It is noted that in some embodiments, the level shifters use complementary inputs as exemplarily depicted in FIGS. 2A and 3A.
(25) With reference to FIG. 4, FIG. 4 exemplarily depicts a level shifter according to one embodiment. The MOS transistors exemplarily depicted are n-channel but p-channel transistors could be used as well. The capacitor/diode pairs connected to the gates of the input TFTs (i.e. all TFTs except the top-middle one) shift the DC levels of the input V.sub.x and V.sub.X signals. Accordingly, the gate voltages of the input TFTs may be expressed as V.sub.p1=V.sub.X−V.sub.HH, V.sub.p2=V.sub.X−V.sub.LL+V.sub.1, V.sub.p3=V.sub.X−V.sub.HH−V.sub.LL, and V.sub.p5=V.sub.x−V.sub.HH−V.sub.LL. (Note the two TFTs on the right have the same gate voltage V.sub.p1).
(26) The basic operation of the level shifter according to FIG. 4A is as follows in two phases. In phase 1 (i.e. when V.sub.X is high and V.sub.x is low), C.sub.1 is charged to V.sub.1+2V.sub.LL via the two TFTs on the left, while C.sub.2 is discharged to 0V via the two TFTs on the right. In phase 2 (i.e. when V.sub.x is high and V.sub.X is low), C.sub.1 is connected to C.sub.2 via the two TFTs in the middle. By preservation of electric charge, C.sub.2 is charged to (V.sub.1+2V.sub.LL)×C.sub.1/(C.sub.1+C.sub.2), or (V.sub.LL+V.sub.1+|V.sub.T|), whichever is lower. It is noted that when current drops to 0 (e.g., steady-state), V.sub.T is stored across the capacitor (references in FIG. 4) connected to the gate-source of the middle-top TFT.
(27) Various variations of this type of circuit and level-shifting may be implemented based on FIG. 4. For example, capacitors C.sub.1 and C.sub.2 may be charged to other voltage levels, connected in series instead of in parallel, or charged in parallel and then connected in series (or vice versa).
(28) In one exemplary embodiment, V.sub.LL=4V, V.sub.1=2V, V.sub.T=−3.25V, C.sub.1=10 pF, C.sub.2=0.5 pF, and all other capacitors are set to 1 pF. The circuit of FIG. 4 converts the range of V.sub.x from (4-8V) to a predicted range of (0-9V). Given the finite channel conductance of the TFTs, the simulated HSPICE range is (˜0.5-8.5V) as exemplarily depicted in FIG. 7A. A channel width-to-length ratio (W/L) of 4 was used for all the TFTs in this simulation. In the simulation examples provided throughout this disclosure (FIGS. 7A-7G) the simulated TFTs are n-channel, have a threshold voltage (V.sub.T) of −3.25V, a gate oxide thickness of 50 nm, and channel sheet resistance (R.sub.sh) of approximately 30 KΩ/□ at gate-to-source voltage (V.sub.GS) of 0V and drain-to-source voltage (V.sub.DS) of 0.1V. The said channel sheet resistance may be obtained e.g. by using a 50 nm-thick LTPS channel doped to a donor concentration (N.sub.D) of approximately 5×10.sup.17 cm.sup.−3.
(29) It is noted that V.sub.LL in FIG. 4 may be chosen to have approximately the same value as the low logic level V.sub.L e.g. of the logic gates of FIGS. 1A/1B, 2A and 3A. For example, if V.sub.LL=V.sub.L, then V.sub.HH=V.sub.H. However other values may be chosen for V.sub.LL as well and the general relationship is V.sub.HH−.sub.H=V.sub.LL−V.sub.L. Also, in the said logic gates, a value of V.sub.L is close to but higher than V.sub.SS, and V.sub.H is close to but lower than V.sub.DD. Thus, in some embodiments, V.sub.LL is set as V.sub.SS, i.e. using the same power supply for both V.sub.SS and V.sub.LL. This may result in V.sub.HH being close to, but lower than V.sub.DD. For example, V.sub.DD=8V, and V.sub.SS=V.sub.LL=4V. V.sub.1 has an arbitrary value, e.g. 2V.
(30) FIGS. 5A to 5D exemplarily depict level shifters according to other embodiments of the invention. With reference generally to FIGS. 5A to 5D, the direct current (DC) level of V.sub.x (or V.sub.out in FIG. 5D) is down shifted and applied to the gate of the pull-up TFT. The gate of the pull-down TFT is connected to a DC voltage, e.g. ground (or optionally, as in FIG. 5C, DC level of V.sub.X is down-shifted and applied to the gate of the pull-down TFT). A DC level of V.sub.x is down-shifted using C.sub.2/D.sub.2 and applied to the source of the pull-down TFT. The lower level of this signal is transferred to V.sub.out whereas its upper level is blocked. In some embodiments, the DC level of V.sub.x is optionally up-shifted using C.sub.3/D.sub.3 (e.g., FIG. 5B) or otherwise directly applied to the drain of the pull-up TFT. The upper level of this signal is transferred to V.sub.out whereas its lower level is blocked. The configuration of the circuit depicted in FIG. 5C can be advantageous to the circuit depicted in FIG. 5A in some embodiments because larger negative V.sub.GS may be available to turn-off (or reduce the off-current of) the pull-down TFT when the pull-up TFT is on. The configuration of the circuit depicted in FIG. 5D can be advantageous to the circuit depicted in FIG. 5A in some embodiments because the larger negative V.sub.GS may be available to turn-off (or reduce the off-current of) the pull-up TFT when the pull-down TFT is on.
(31) It is noted that various combinations of the functions and/or components or cascading of the stages is possible of the circuits depicted in FIGS. 5A-5D.
(32) Exemplary HSPICE simulation results of the level shifters according to FIGS. 5A and 5D are depicted in FIGS. 7B and 7C, respectively. For both simulations, C.sub.1=1 pF, C.sub.2=20 pF, V.sub.1=4V, V.sub.2=4V, and W/L=4 for the pull-down TFT. For the pull-up TFT, W/L=0.2 and 20 in the simulations of FIGS. 7B and 7C respectively. A small pull-up W/L ratio was used in the first simulation to reduce current flow through the pull-up TFT when the pull-down TFT is on; whereas a large W/L ratio was used to enhance the switching speed in the second simulation. In FIGS. 7B and 7C, V.sub.G1 denotes the gate voltage of the pull-up TFT (which is equal to the anode voltage of D.sub.1) and V.sub.D2 denotes the anode voltage of D.sub.2 (which is equal to the source voltage of the pull-down TFT). Exemplary HSPICE simulation results of the inverter, NOR and NAND gates according to FIGS. 1A, 2A and 3A are depicted in FIGS. 6D, 6E and 6F, respectively. The level shifter simulated in FIG. 7B was incorporated in the simulation of these logic gates.
(33) FIG. 6 exemplarily depicts a positive-edge-triggered D-Hip-Flop according to one exemplary embodiment. The NAND logic gates employed in the construction of the D-Hip-Flop circuit may be implemented using the embodiment of FIG. 3A. As will be appreciated by those skilled in the art, the circuit construct of the D-Flip-Flop of FIG. 6 comprised of NAND logic gates based on the embodiment of FIG. 3A is the same as the circuit construct of a conventional CMOS D-Flip-Flop circuit comprised of conventional CMOS NAND gates, except that complementary input, output and intermediary signals are used for the operation of the D-Flop-Flop of FIG. 6; for example, the input signals of a conventional CMOS D-Flip-Flop with the same construct may include CLK and D whereas the input signals of the D-Flip-Flop of FIG. 6 may include CLK, CLK, D and D; and the output signals of a conventional CMOS D-Flip-Flop with the same construct may include Q and Q.sub.bar whereas the output signals of the D-Flip-Flop of FIG. 6 may include Q, Q, Q.sub.bar and Q.sub.bar (note Q is complementary to Q.sub.bar, therefore Q.sub.bar≈Q). Similarly, various conventional logic circuits known in the art may be implemented using the disclosed logic units as the building blocks of the circuit and providing complementary signals as described. In one example, D-Hip-Flops implemented according to FIG. 6 are cascaded to implement a shift register, which may be used as the row (gate) driver of an active-matrix light-emitting diode display. Such a shift register circuit may be fabricated monolithically with an HJFET backplane (e.g. using the process examples as in the co-pending U.S. patent application Ser. No. 15/266,414). Exemplary simulation results of a D-Flip-Flop according to FIG. 6 is given in FIG. 7G. The NAND gate simulated in FIG. 7F was incorporated in the simulation of the D-Hip-Flop of FIG. 7G. As noted, apart from the use of complementary signals, the simulated D-Flip-Flop provides the same functionality as that of a conventional CMOS D-Flip-Flop.
(34) Thus, a complementary circuit as exemplarily depicted in FIGS. 1A to 5D including depletion-mode thin-film transistors having a single channel type and implemented with minimal standby (static) power can be provided thereby to reduce the manufacturing cost and capital equipment cost compared to the conventional LTPS TFT process. In addition, the number of mask steps may be reduced compared to the conventional LTPS process. Further, the process temperature may be reduced from 400-600° C. to 200° C. and below, compared to the conventional LTPS. The use of low cost and/or flexible substrates such as plastic and conventional glass is made possible without compromising the device performance and system-level performance. Also, device and system-level performance is enhanced (for a given power consumption), or the power consumption is reduced (for a given system performance), compared to the conventional LTPS TFT process.
(35) The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
(36) Further, Applicant's intent is to encompass the equivalents of all claim elements, and no amendment to any claim of the present application should be construed as a disclaimer of any interest in or right to an equivalent of any element or feature of the amended claim.
