Post over-erase correction method with auto-adjusting verification and leakage degree detection

Abstract

A post over-erase correction (POEC) method with an auto-adjusting verification mechanism and a leakage degree detection function detects g.sub.m degradation or leakage degree of flash cells before or after entering the POEC process. When a preset condition is satisfied, the auto-adjusting verification mechanism of the POEC is switched on to further reduce leakage current. After cycling, the POEC repairs Vt of over-erased cells to a higher level to solve leakage issues. The erase shot count increases due to slower erase speeds after cycling. Therefore, the cycling degree of flash cells is detected by observing the shot number that the erase operation used. When the leakage phenomenon becomes serious, the bit line (BL) leakage current, amount of repaired BLs, and over-erase correction (OEC) shot number will increase during the OEC procedure. Therefore, the leakage degree of flash cells can be detected by inspecting the above data.

Claims

1. A post over-erase correction method with an auto-adjusting verification mechanism and a leakage degree detection function comprising: programming a plurality of flash cells; erasing the plurality of flash cells; performing over-erase correction; determining a target degree to obtain a switch condition result; and turning on the auto-adjusting verification mechanism and performing post over-erase correction based upon the switch condition result; wherein determining the target degree to obtain a switch condition result considers g.sub.m degradation.

2. The post over-erase correction method with an auto-adjusting verification mechanism and a leakage degree detection function according to claim 1, wherein reference current is produced by multiple sets of reference cells or constant current and turning on the auto-adjusting verification mechanism reduces an amount of reference cells or constant current to lower reference current.

3. The post over-erase correction method with an auto-adjusting verification mechanism and a leakage degree detection function according to claim 1, turning on the auto-adjusting verification mechanism and performing post over-erase correction repairs threshold voltage of over-erased cells to a higher level with or without adjusting power over-erase correction programming voltage.

4. The post over-erase correction method with an auto-adjusting verification mechanism and a leakage degree detection function according to claim 1, further comprising: recording an erase shot number for each erase procedure.

5. The post over-erase correction method with an auto-adjusting verification mechanism and a leakage degree detection function according to claim 4, further comprising: comparing the erase shot number with a target cycling-degree to confirm that the erase shot number has reached a target cycling-degree.

6. The post over-erase correction method with an auto-adjusting verification mechanism and a leakage degree detection function according to claim 5, wherein the switch condition result is a switch on condition when the erase shot number has reached the target cycling-degree.

7. The post over-erase correction method with an auto-adjusting verification mechanism and a leakage degree detection function according to claim 6, wherein the switch on condition turns on the auto-adjusting verification mechanism and the post over-erase correction is performed.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a flowchart illustrating an over-erase correction and post over-erase correction method of the prior art.

(2) FIG. 2 is a drawing illustrating of a circuit comparing cell current and reference current to verify the state of flash cells of the prior art.

(3) FIG. 3 is a graph illustrating g.sub.m degradation of the prior art.

(4) FIG. 4A is a drawing illustrating two post over-erase correction method with adjustable verification mechanism according to an embodiment of the present invention.

(5) FIG. 4B is a drawing illustrating two post over-erase correction method with adjustable verification mechanism according to an embodiment of the present invention.

(6) FIG. 5 is a flowchart illustrating a method of determining the switching condition of the post over-erase correction mechanism according to an embodiment of the present invention.

(7) FIG. 6A is a flowchart illustrating methods of determining the switching condition of the post over-erase correction mechanism according to an embodiment of the present invention.

(8) FIG. 6B is a flowchart illustrating methods of determining the switching condition of the post over-erase correction mechanism according to an embodiment of the present invention.

(9) FIG. 6C is a flowchart illustrating methods of determining the switching condition of the post over-erase correction mechanism according to an embodiment of the present invention.

(10) FIG. 7 is a flowchart illustrating a method for performing post over-erase correction when g.sub.m degradation is detected according to an embodiment of the present invention.

(11) FIG. 8 is a graph illustrating detecting g.sub.m degradation according to an embodiment of the present invention.

(12) FIG. 9 is a flowchart illustrating determining the switching condition of the post over-ease correction mechanism according to an embodiment of the present invention.

(13) FIG. 10 is a diagram illustrating adjusting reference current to change a verification mechanism according to an embodiment of the present invention.

(14) FIG. 11A is a graph illustrating changing a comparison mechanism based on word line voltage according to an embodiment of the present invention.

(15) FIG. 11B is graph illustrating changing a comparison mechanism based on reference current according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

(16) To facilitate understanding of the object, characteristics and effects of this present disclosure, embodiments together with the attached drawings for the detailed description of the present disclosure are provided.

(17) Refer to FIG. 4A and FIG. 4B, which are drawings illustrating two post over-erase correction methods with adjustable verification mechanisms according to embodiments of the present invention. The present invention detects g.sub.m degradation or leakage degree of flash cells before or after the POEC1 step. When a preset condition is satisfied, the verification mechanism of the POEC2 is switched on to further reduce leakage current. Since the un-cycled flash cells suffer less g.sub.m degradation and leakage degree, the probability of switching on of POEC2 is low at initial state. Therefore, the initial erase time is reasonable.

(18) After cycling, the POEC2 repairs Vt of over-erased cells to a higher level for solving leakage issues. Such solutions are obtaining a reasonable read margin and t.sub.PP after cycling while the increased erase time is acceptable since the allowable block erase time is longer after cycling. Moreover, the risk of over soft-programming due to degradation of programmability after cycling is also reduced. The programming voltage of the POEC can be changed to a lower level to further reduce the risk of over soft-programming.

(19) The POEC verification method 500 begins by pre-programming the flash cells in Step 510. In Step 520 the flash cells are erased and over-erase correction is performed in Step 530.

(20) In Step 540, determination is made on whether or not to switch on the POEC method with adjustable verification mechanism (POEC2). If it is determined to switch on the POEC method, perform post over-erase correction using the adjustable verification mechanism in Step 560 and then end in Step 590. If it is determined to not switch on the POEC method with adjustable verification, perform post over-erase correction in Step 550 and then end in Step 590.

(21) There are several methods to determine the switch condition of the POEC mechanism.

(22) Refer to FIG. 5, which is a flowchart illustrating a method of determining the switching condition of the post over-erase correction mechanism according to an embodiment of the present invention

(23) The embodiment of the present invention illustrated in FIG. 5 is one method to detect leakage-degree of flash cells. The erase shot number increases due to slower erase speeds after cycling. Therefore, the cycling-degree of flash cells can be detected by observing the shot number that the erase operation used.

(24) In Step 520, the flash cells are erased and over-erase correction is performed in Step 530. For each erase operation the erase shot number is recorded in Step 525. In Step 540, the erase shot number is used to determine whether or not the erase shot number has reached a target cycling-degree.

(25) If the erase shot number has reached the target cycling-degree, the POEC method with adjustable verification mechanism is switched on and post over-erase correction with the adjustable verification mechanism (Step 560 of FIG. 4A and FIG. 4B) is performed.

(26) If the erase shot number has not reached the target cycling-degree, the POEC method with adjustable verification mechanism is not switched on and post over-erase correction (Step 550 of FIG. 4A) is performed. Or the method is done in Step 590 in FIG. 4B.

(27) Refer to FIG. 6A, FIG. 6B and FIG. 6C, which is are flowcharts illustrating methods of determining the switching condition of the post over-erase correction mechanism according to an embodiment of the present invention.

(28) The embodiment of the present invention illustrated in FIG. 6A is for another method of detecting leakage-degree of flash cells. When the leakage phenomenon becomes serious, the amount of repaired BLs, and the OEC shot number will increase during the OEC operation. Therefore, the leakage-degree of flash cells can be detected by inspecting the above data.

(29) In Step 520 the flash cells are erased and over-erase correction is performed in Step 530. For each over-erase correction operation, the amount of repaired BLs and the OEC shot number are recorded in Step 533. In Step 540 the amount of repaired BLs and the OEC shot number are used to determine whether or not the amount of repaired BLs and the OEC shot number have reached a target cycling-degree.

(30) If the amount of repaired BLs, and the OEC shot number have reached a target cycling-degree, the POEC method with adjustable verification mechanism is switched on and post over-erase correction with adjustable verification mechanism (Step 560 of FIG. 4A and FIG. 4B) is performed.

(31) If the amount of repaired BLs and the OEC shot number have not reached the target cycling-degree, the POEC method with adjustable verification mechanism is not switched on and post over-erase correction (Step 550 of FIG. 4A) is performed. Or the method is done in Step 590 in FIG. 4B.

(32) The embodiment of the present invention illustrated in FIG. 6B and FIG. 6C are two methods for detecting leakage current directly by OEC verification.

(33) The embodiment of the present invention illustrated in FIG. 6B is for another method of detecting leakage-degree of flash cells. When g.sub.m degradation after cycling the leakage phenomenon becomes serious, the BL leakage current after POEC1 whether or not affect the OFF current can be checked by OEC verification with different conditions of OEC verification. For example, WL voltage=1V and Iref=Ioec2.

(34) In Step 520 the flash cells are erased, over-erase correction1 (OEC1) is performed in Step 530. In Step 533 over-erase correction verification2 (OECV2) is performed to checked the BL leakage after OEC1 whether it causes the OFF current. Different verified conditions are used for OEC1 and OECV2. For example, the verification WL voltage of OEC1 is 0V and IREF=Ioecv1=4 uA; the verification WL voltage of OEC2 is 1V and IREF=Ioecv2<14 uA. When OEC1 is performed and verification passed in Step 530, if the result of OECV2 verification is pass in Step 533, i.e. the cell current is less than Ioecv2, which means this bit line will contribute to the OFF current after POEC1 is performed or means g.sub.m degradation. It is required to switch on the POEC method with adjustable verification mechanism (POEC2). If the result of OECV2 verification is fail in Step 533, i.e. the cell current is greater than Ioecv2, which means this bit line will not contribute to the OFF current after POEC1 is performed or means gm normal. It is not required to switch on the POEC method with adjustable verification mechanism (POEC2). In Step 540, determination is made on whether or not to switch on the POEC method with adjustable verification mechanism (POEC2). If it is determined to switch on the POEC method, perform post over-erase correction using the adjustable verification mechanism in Step 560 and then end in Step 570. If it is determined to not switch on the POEC method with adjustable verification, perform post over-erase correction in Step 550 and then end in Step 570.

(35) The embodiment of the present invention illustrated in FIG. 6C is for another method of detecting leakage-degree of flash cells. When the leakage phenomenon becomes serious, the BL leakage current can be detected directly. Therefore, the BL leakage current can be detected by using the OEC verification with a well-chosen condition of verification.

(36) In Step 520 the flash cells are erased, over-erase correction1 (OEC1) is performed in Step 530 and post over-eras correction1 (POEC1) is performed in Step 550. In Step 533 over-erase correction verification2 (OECV2) is performed to detect the BL leakage. In Step 540 check whether or not the BL leakage current is greater than a target leakage. Different verified conditions are used for OEC1 and OECV2. For example, the verification WL voltage of OEC1 is 0V˜0.5V and IREF=Ioecv1=4 uA. The verification WL voltage of OEC2 is 0.3V˜1V and the IREF=Ioecv1=4 uA.

(37) If the BL leakage current is greater than a target leakage, the POEC method with adjustable verification mechanism is switched on and post over-erase correction with adjustable verification mechanism (Step 560) is performed.

(38) If the BL leakage current is not greater than a target leakage, the POEC method with adjustable verification mechanism is not switched on and the method is done in Step 570.

(39) Refer to FIG. 7, which is a flowchart illustrating a method for performing post over-erase correction when g.sub.m degradation is detected according to an embodiment of the present invention.

(40) The g.sub.m degradation of flash cells is detected during the first POEC mechanism operation or after the first POEC mechanism (POEC1) is finished. If g.sub.m degradation is detected, the POEC with adjustable verification mechanism (POEC2) is performed to further repair the Vt of flash cells to a higher level with or without adjusting the programming voltage of POEC.

(41) The adjustable verification mechanism illustrated in FIG. 7 comprises the following. The reference current is produced by multiple sets of reference cells or constant current (REF1, REF2, REF3). Once the switching condition is reached, the number or amount of reference cells or constant current is reduced to lower the reference current.

(42) In Step 520 the flash cells are erased and over-erase correction is performed in Step 530. In Step 545, the post over-erase correction mechanism is performed.

(43) The POEC mechanism of Step 545 comprises performing the POEC with mechanism 1 (POEC1).

(44) In Step 555, determine if there is g.sub.m degradation. If g.sub.m degradation is detected, switch on the POEC2 method and perform the POEC method with adjustable verification mechanism in Step 560. After performing the POEC2 method, the method is done in Step 570.

(45) If g.sub.m degradation is not detected in Step 555, the POEC2 method is not switched on and the method is done in Step 570.

(46) Refer to FIG. 8, which is a graph illustrating detecting g.sub.m degradation according to an embodiment of the present invention. Initially, the post over-erase correction with mechanism 1 (POEC1) repairs cells with WL=POEC_verify and Iref=Ipoecv1 (For example, POEC_verify=3.5V, and Ipoecv1=10 uA). After that, WL and Iref are set to g.sub.m_verify and I g.sub.m-test, respectively, to detect g.sub.m degradation (For example, g.sub.m_verify=3V, and I g.sub.m-test=6.5 uA). Once the cell current is higher than I g.sub.m-test, meaning that g.sub.m degradation occurs. When g.sub.m degradation occurs, the POEC method with adjustable verification mechanism (POEC method with mechanism 2, POEC2) repairs cells with different mechanisms. For example, Iref=Ipoecv2 and WL=POEC_verify or Iref=I g.sub.m-test and WL=g.sub.m_verify. The programming voltage (both WL and BL voltage) of POEC2 can be adjusted for preventing over soft-programming.

(47) In the embodiment illustrated in FIG. 8, g.sub.m degradation is detected with WL=g.sub.m-verify and Iref=I g.sub.m-test.

(48) Refer to FIG. 9, which is a flowchart illustrating determining the switching condition of the post over-ease correction mechanism according to an embodiment of the present invention.

(49) Different combinations of the method of the present invention mentioned above are used to determine the switching condition of the POEC.

(50) For example, the following conditions are used in various embodiments.

(51) Consider only one of either the erase shot number, the repaired BL amount during OEC, the OEC shot number, the BL leakage current, or g.sub.m degradation.

(52) Consider both the erase shot number and g.sub.m degradation, as shown in FIG. 9.

(53) Consider both the repaired BL amount during OEC and g.sub.m degradation. Consider both the OEC shot number and g.sub.m degradation. Consider both the BL leakage current and g.sub.m degradation.

(54) In the embodiment illustrated in FIG. 9, the switching condition of the POEC method considers both the erase shot number and g.sub.m degradation.

(55) In Step 520 the flash cells are erased and over-erase correction is performed in Step 530. For each erase operation the erase shot number is recorded in Step 525. In Step 540 the erase shot number is used to determine whether or not the erase shot number has reached a target cycling-degree.

(56) If the erase shot number has not reached a target cycling-degree, POEC1 is performed in Step 550 and the method is done in Step 570.

(57) If the erase shot number has reached the target cycling-degree, in Step 555, determine if g.sub.m degradation is detected.

(58) If g.sub.m degradation is detected in Step 555, switch on the POEC2 method and perform the POEC method with adjustable verification mechanism (POEC2) in Step 560.

(59) If g.sub.m degradation is not detected in Step 555, do not switch on the POEC2 method and post over-erase correct is performed with mechanism 1 (POEC1). The After that, the method is done in Step 570.

(60) Refer to FIG. 10, which is a diagram illustrating adjusting reference current to change a verification mechanism according to an embodiment of the present invention.

(61) As shown in FIG. 10, the reference current is produced by multiple sets of reference cells or constant current. Once the POEC switching condition is reached, the number of reference cells or constant current is reduced to lower the reference current.

(62) Two methods are used to change the verification mechanism of the POEC. Since the reference current is established by reference cells or constant current, the current comparison mechanism can be changed by modulating word line (WL) voltage or the reference current, as shown in FIG. 11A and FIG. 11B, respectively. When the preset cycling-degree is detected, the comparison condition is changed to repair the threshold voltage of over-erased cells to a higher level.

(63) While the present disclosure has been described by means of specific embodiments, numerous modifications and variations could be made thereto by those skilled in the art without departing from the scope and spirit of the present disclosure set forth in the claims.