SLOT WAVEGUIDE FOR A PHASE SHIFTER BASED ON FERROELECTRIC MATERIALS

Abstract

The present invention relates to a slot waveguide formed by a vertical material stack comprising a top layer with a first refractive index, a center layer including a ferroelectric material and with a second refractive index, and a Si.sub.1-xGe.sub.x pseudosubstrate layer with 0<x≤1 and with a third refractive index. The center layer is grown on the Si.sub.1-xGe.sub.x pseudosubstrate layer. The second refractive index is lower than the first refractive index and lower than the third refractive index. The slot waveguide can be included in a phase-shifter including two vertically arranged electrodes configured for providing a vertical electrical field (E) extending between the top layer and the bottom layer of the slot waveguide and for providing a complementary-metal-oxide-semiconductor compatible driver voltage. The phase-shifter can be configured for providing a linear electro-optical effect inside the center layer of the slot waveguide.

Claims

1. A slot waveguide formed by a vertical material stack comprising: a top layer with a first refractive index, a center layer including a ferroelectric material and with a second refractive index, and a Si.sub.1-xGe.sub.x pseudosubstrate layer with 0<x≤1 and with a third refractive index, wherein the center layer is grown on the Si.sub.1-xGe.sub.x pseudosubstrate layer, and wherein the second refractive index is lower than the first refractive index and lower than the third refractive index.

2. The slot waveguide according to claim 1, wherein the center layer is made of barium titanate and wherein 0.8<x≤1, preferably 0.85≤x≤0.93 or wherein the center layer is made of a layer stack including the ferroelectric material and a buffer layer with a layer thickness below 2.5 nm.

3. The slot waveguide according to claim 1, wherein the Si.sub.1-xGe.sub.x layer is grown on a silicon substrate.

4. The slot waveguide according to claim 1, wherein x=1 such that the Si.sub.1-xGe.sub.x pseudosubstrate layer is a germanium layer and wherein the germanium layer is grown on a silicon substrate using a buffer layer approach in order to relax the germanium layer, on a silicon substrate using selective epitaxy, or on an insulator substrate.

5. The slot waveguide according to claim 1, wherein the center layer is epitaxially grown and/or the Si.sub.1-xGe.sub.x pseudosubstrate layer is epitaxially grown.

6. The slot waveguide according to claim 1, wherein the Si.sub.1-xGe.sub.x pseudosubstrate layer has a thickness between 5 monolayers and 10 nm.

7. The slot waveguide according to claim 1, wherein the top layer is a doped amorphous-silicon layer, a doped amorphous Si.sub.1-yGe.sub.y layer, or a doped poly-silicon layer.

8. The slot waveguide according to claim 1, comprising: a bottom layer with a fourth refractive index, wherein the fourth refractive index is larger than the second refractive index.

9. The slot waveguide according to claim 8, wherein the bottom layer is a doped crystalline-silicon layer or a doped Si.sub.1-zGe.sub.z layer.

10. A phase-shifter comprising: a slot waveguide according to claim 8, and two vertically arranged electrodes configured for providing a vertical electrical field (E.sub.v) extending between the top layer and the bottom layer of the slot waveguide and for providing a complementary-metal-oxide-semiconductor compatible driver voltage, wherein the phase-shifter is configured for providing a linear electro-optical effect inside the center layer of the slot waveguide.

11. The phase-shifter according to claim 10, wherein a first of the two vertically arranged electrodes is formed by a conductivity region of the top layer and a second of the two vertically arranged electrodes is formed by a conductivity region of the bottom layer.

12. The phase-shifter according to claim 10, wherein the phase-shifter is an electro-optical modulator configured for intensity modulation.

13. An electronic-photonic integrated circuit comprising a phase-shifter according to claim 10.

14. The electronic-photonic integrated circuit according to claim 13, wherein the phase shifter is integrated in the front end of line.

15. A method for making a slot waveguide formed by a vertical material stack comprising the steps: providing a Si.sub.1-xGe.sub.x pseudosubstrate layer with 0<x≤1 and with a third refractive index, growing a center layer on the Si.sub.1-xGe.sub.x pseudosubstrate layer, wherein the center layer includes a ferroelectric material and has a second refractive index, and providing a top layer with a first refractive index, wherein the second refractive index is lower than the first refractive index and lower than the third refractive index.

16. The slot waveguide according to claim 2, wherein the Si.sub.1-xGe.sub.x layer is grown on a silicon substrate.

17. The slot waveguide according to claim 16, wherein x=1 such that the Si.sub.1-xGe.sub.x pseudosubstrate layer is a germanium layer and wherein the germanium layer is grown on a silicon substrate using a buffer layer approach in order to relax the germanium layer, on a silicon substrate using selective epitaxy, or on an insulator substrate.

18. The slot waveguide according to claim 4, wherein the center layer is epitaxially grown and/or the Si.sub.1-xGe.sub.x pseudosubstrate layer is epitaxially grown.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The present invention will be more fully understood from the following detailed description of embodiments thereof, taken together with the drawings in which:

[0049] FIG. 1A shows a cross sectional view of a prior art phase shifter;

[0050] FIG. 1B shows a top view of the prior art phase shifter of FIG. 1A;

[0051] FIG. 2 shows a cross sectional view of an embodiment of a slot waveguide;

[0052] FIG. 3A shows a cross sectional view of an embodiment of a phase-shifter comprising the slot waveguide of FIG. 2;

[0053] FIG. 3B shows a top view of the embodiment of a phase-shifter of FIG. 3A;

[0054] FIG. 4 shows a cross sectional view of an embodiment of an EPIC comprising the embodiment of the phase-shifter;

[0055] FIG. 5 shows a schematic flow diagram representing an embodiment of a method for making a slot waveguide formed by a vertical material stack.

DETAILED DESCRIPTION

[0056] In the following reference is made to FIG. 1A and FIG. 1B. FIG. 1A schematically shows a cross sectional view of a phase shifter 100 according to the state of the art. FIG. 1B shows the respective top view of the phase shifter 100. The phase shifter 100 is formed by a slot waveguide 110, a first electrode 122, and a second electrode 124.

[0057] The slot waveguide 110 is formed on a dielectric Si substrate 126 and comprises a Si top layer 112, a Si bottom layer 120, and a slot region 111. The top layer 112 and bottom layer 120 are so called slabs of the slot waveguide 110. The slot region 111 is made of a layer stack of a SiO.sub.2 layer 118, a SrTiO.sub.3 layer 116 and a BaTiO.sub.3 layer 114.

[0058] The Si slab material has a refractive index of 3.98 for a wavelength of 590 nanometer. The refractive index of SrTiO.sub.3 is 2.28 for a wavelength of 590 nanometer and the refractive index of BaTiO.sub.3 is 2.43 for a wavelength of 590 nanometer. Thus, the slab material has a higher refractive index than the slot region material such that a field confinement is achieved within the slot region 111.

[0059] The BaTiO.sub.3 layer 114 is oriented in c-axis orientation, has a large LEOE, and is used as EO active layer. The BaTiO.sub.3 layer 114 is arranged on the SrTiO.sub.3 layer 116 which serves as template layer to reduce lattice mismatch and thermal expansion coefficient mismatch between the BaTiO.sub.3 layer 114 and the SiO.sub.2 layer 118. This allows suppressing a biaxial tensile in-plane strain which may otherwise result in an a-axis growth of BaTiO.sub.3 instead of c-axis growth. The SiO.sub.2 layer 118 serves as an interfacial layer, which is formed by diffusion of oxygen from the SrTiO.sub.3 layer 116 into the Si bottom layer 120. The interfacial SiO.sub.2 layer 118 has typically a thickness between 1 nm and 3 nm.

[0060] The electrodes 122 and 124 are bulk electrodes made of gold (Au). The electrodes 122 and 124 provide a CMOS compatible driver voltage 128. The driver voltage 128 is a voltage, which can drive a CMOS.

[0061] The first electrode 122 and the second electrode 124 are arranged on the dielectric Si substrate 126. The electrodes 122 and 124 are arranged on opposite sides of the slot waveguide 110, such that a horizontal electrical field EH extending from the first electrode 122 to the second electrode 124 is provided by them.

[0062] The SiO.sub.2 layer 118 has a dielectric permittivity of about ε.sub.SiO.sub.2=4, which is very low compared to BaTiO.sub.3 which has a dielectric permittivity of about ε.sub.BaTiO.sub.3=1000. Also SrTiO.sub.3 has a lower dielectric permittivity compared to BaTiO.sub.3, namely of about ε.sub.SrTIO.sub.3=300. As a consequence, most of the voltage drops inside the SrTiO.sub.3 template layer 116 and the SiO.sub.2 interfacial layer 118 resulting in a reduced effective electrical field inside the BaTiO.sub.3 layer and decreased EO performance. This results in unwanted energy consumption.

[0063] FIG. 2 shows a cross sectional view of an embodiment of a slot waveguide 200 which may be implemented in a phase shifter 300 shown in FIG. 3A and FIG. 3B which is improved compared to the prior art phase shifter 100. In particular, the phase shifter 300 allows an enhanced optical-electrical field overlap and to provide a highly efficient phase shifter with reduced energy consumption.

[0064] The slot waveguide 200 is formed by a vertical material stack 202 that comprises a top layer 212 with a first refractive index, a center layer 214 with a second refractive index, a Si.sub.1-xGe.sub.x pseudosubstrate layer 216 with a third refractive index, and a bottom layer 222 with a fourth refractive index. The center layer 214 includes a ferroelectric material. The center layer 214 is grown on the Si.sub.1-xGe.sub.x pseudosubstrate layer 216 and together they form a slot region 211. The bottom layer is optional.

[0065] In this embodiment, the top layer 212 and the bottom layer 222 are made of Si, i.e., the first refractive index and the fourth refractive index are equal. In particular, the top layer 212 is a doped a-Si layer and the bottom layer 222 is a doped c-Si layer. In other embodiments, the top layer may be a poly-Si layer.

[0066] The bottom layer 222 is a Si substrate, on which the Si.sub.1-xGe.sub.x pseudosubstrate layer is grown. The Si.sub.1-xGe.sub.x pseudosubstrate layer includes Ge, i.e., 0<x≤1, such that the third refractive index is lower than the first refractive index and the fourth refractive index.

[0067] In this embodiment, the center layer 214 is made of BaTiO.sub.3 and x=0.9, i.e., the Si.sub.1-xGe.sub.x pseudosubstrate layer 216 is made of Si.sub.0.1Ge.sub.0.9. The Si.sub.1-xGe.sub.x pseudosubstrate layer 216 has a refractive index of 5.40 for a wavelength of 590 nanometer, i.e., a higher refractive index than the SrTiO.sub.3 template layer used in the prior art phase shifter 100. The second refractive index is thus lower than the first refractive index, the third refractive index, and the fourth refractive index. The use of the Si.sub.1-xGe.sub.x pseudosubstrate layer 216 allows increasing the optical field enhancement inside the BaTiO.sub.3 layer 214. Furthermore, the overlap between optical and electrical field is increased. Such material composition reduces the lattice mismatch and thermal expansion coefficient mismatch between the c-Si bottom layer 222 and the BaTiO.sub.3 layer 214. This allows growing the BaTiO.sub.3 layer 214 on the Si.sub.1-xGe.sub.x pseudosubstrate layer 216 without inducing any interfacial layer. Thus, a voltage drop by an interfacial layer is avoided and the effective electrical field inside the BaTiO.sub.3 layer 214 is increased. Furthermore, the BaTiO.sub.3 layer 214 grows in c-axis orientation on the Si.sub.1-xGe.sub.x pseudosubstrate layer 216, allowing to induce a large LEOE.

[0068] In other embodiments, x may also have a different value, for example, x may be a value between 0.8 and 1, such as 0.8<x≤1, or 0.85≤x≤0.93. In other embodiments, x=1 such that the Si.sub.1-xGe.sub.x pseudosubstrate layer may be a Ge layer. The Ge layer may be grown, for example, on a Si substrate using a buffer layer approach in order to relax the Ge layer, on a Si substrate using selective epitaxy, or on an insulator substrate, e.g., a SOI.

[0069] In other embodiments, the center layer may also, for example, be made of a layer stack including BaTiO.sub.3, LiNbO.sub.3, or any other ferroelectric material, and a buffer layer with a layer thickness below 2.5 nm, e.g., a SrTiO.sub.3 buffer layer. A respective effective second refractive index is thus lower than the first refractive index, the third refractive index, and the fourth refractive index. The other ferroelectric material may be, for example, any other ferroelectric material having a perovskite structure.

[0070] In this embodiment, the center layer 214 is epitaxially grown and the Si.sub.1-xGe.sub.x pseudosubstrate layer is epitaxially grown. In other embodiments, only one or none of them may be expitaxially grown.

[0071] The Si.sub.1-xGe.sub.x pseudosubstrate layer 216 has a thickness of 10 nm. In other embodiments, the Si.sub.1-xGe.sub.x pseudosubstrate layer may also have a thickness, for example, between 5 monolayers and 10 nm.

[0072] In the following reference is made to FIG. 3A and FIG. 3B. FIG. 3A schematically shows a cross sectional view of an embodiment of the phase-shifter 300 comprising the slot waveguide 200 of FIG. 2. FIG. 3B shows the respective top view of the embodiment of the phase-shifter 300 of FIG. 3A. Identical features are referred to using the same reference numerals for FIG. 2, FIG. 3A, and FIG. 3B.

[0073] Besides the slot waveguide 200 described with respect to FIG. 2, the phase shifter 300 comprises two vertically arranged electrodes in form of a first electrode, here a top electrode 310, and a second electrode, here a bottom electrode 320. The bottom electrode 320 is connected to a metal electrode 322. The top electrode 310 and the metal electrode 322 are connected to a power source 328. The vertically arranged electrodes 310 and 320 are provided with a driver voltage of 2 V by the power source 328 which is compatible for CMOS. The vertically arranged electrodes 310 and 320 thus provide a vertical electrical field E.sub.V extending between the top layer 212 and the bottom layer 222 of the slot waveguide 200. The phase-shifter 300 provides a LEOE inside the center layer 214 of the slot waveguide 200. In other embodiments, the phase-shifter may be used as an EO modulator configured for intensity modulation, e.g., by implementing the phase-shifter, for example, in an interferometer, e.g., a Mach-Zehnder-interferometer, or a resonator, e.g., a Fabry-Perot-resonator or a ring resonator to form an EO modulator.

[0074] In this embodiment, the top electrode 310 is formed by a doped conductivity region of the top layer 212. The bottom electrode 320 is formed by a doped conductivity region of the bottom layer 222. The top layer 212 is a doped a-Si layer and the bottom layer 222 is a doped c-Si layer. The doping concentration of the conductivity regions are higher than the doping concentration of the remaining parts of the top layer 212 and the remaining parts of the bottom layer 222. The doping concentration of the conductivity region, which forms the top electrode 310 is 10.sup.20 atoms per cubic centimeter. The doping concentration of the conductivity region, which forms the bottom electrode 320 is also 10.sup.20 atoms per cubic centimeter. The doping concentration for the remaining parts of the top layer 310 and bottom layer 222 is 10.sup.17 atoms per cubic centimeter. Here, a c-Si rib waveguide acts as bottom layer 222. In other embodiments, the doping concentration within the top electrode 310 and/or the bottom electrode 320 may also be, for example, between 10.sup.10 to 10.sup.20 atoms per cubic centimeter. The remaining parts of the top layer 212 and/or the bottom layer 222 may also have a doping concentration of, for example, below 10.sup.10 atoms per cubic centimeter.

[0075] The vertical arrangement of the electrodes 310 and 320 for the horizontal waveguide configuration allows an integration in the FEOL of an EPIC.

[0076] FIG. 4 shows a cross sectional view of an embodiment of an EPIC 400 comprising the embodiment of the phase-shifter 300. In this embodiment, the phase shifter 300 is integrated in the FEOL. Identical features are referred to using identical reference numerals for FIG. 3A, FIG. 3B, and FIG. 4.

[0077] The EPIC 400 has a front-end 450 and a back end 440. The front-end 450 is fabricated with a FEOL technology. The front-end 450 comprises a Si photonic integrated circuit (PIC) region 420 and an electronic integrated circuit (EIC) region 430. The Si PIC region 420 comprises a Ge photodiode 410, Si waveguides 412 and a phase shifter 300. Impinging light signals 414 may be received and transmitted light signals 416 may be transmitted from the EPIC 400. The EIC region 430 comprises a SiGe heterojunction bipolar transistor (SiGe:C HBT) 432, an n-channel metal-oxide-semiconductor (NMOS) 434 and a p-channel metal-oxide-semiconductor (PMOS) 436 which form a Bi-CMOS. The back-end 440 comprises an interconnect stack 442 with several metal planes 444 and 446.

[0078] An integration of the phase shifter 300 of FIG. 3A and FIG. 3B into the EPIC 400 allows an integration in the front-end 440. The bottom electrode 320 of the phase shifter 300 allows additional photonic components, such as a Ge photo diode 410, to couple the light signals between the phase shifter 300 and the Ge photo diode 410 directly. A light coupling with a metal plane can thus be avoided. The direct coupling between the phase shifter 300 and the Ge photo diode 410 allows the reduction of optical power consumption of the EPIC 400.

[0079] FIG. 5 shows a schematic diagram representing an embodiment of a method 500 for making a slot waveguide formed by a vertical material stack, e.g., the slot waveguide presented in FIG. 2.

[0080] In step 510, a Si.sub.1-xGe.sub.x pseudosubstrate layer with 0<x≤1 is provided. For fabricating the slot waveguide 200 of FIG. 2, for example, a Si.sub.0.1Ge.sub.0.9 pseudosubstrate layer is provided. The Si.sub.0.1Ge.sub.0.9 pseudosubstrate layer has a third refractive index of 5.40. In other embodiments, the Si.sub.1-xGe.sub.x pseudosubstrate layer may be epitaxially grown on a bottom layer, such as a Si substrate.

[0081] In step 520, a center layer is epitaxially grown on the Si.sub.1-xGe.sub.x pseudosubstrate layer. The center layer includes a ferroelectric material and has a second refractive index. For fabricating the slot waveguide 200 of FIG. 2, the center layer is made of BaTiO.sub.3 with a refractive index of 2.43. In other embodiments, another ferroelectric material may also be used instead, e.g., LiNbO.sub.3. In other embodiments, for example, if the Si.sub.1-xGe.sub.x pseudosubstrate layer is made of Ge, a buffer layer, such as a SrTiO.sub.3 buffer layer, with a thickness of 2.5 nm may be grown on the Ge layer, before the center layer is grown on it.

[0082] In step 530, a top layer with a first refractive index is provided. In this embodiment, the top layer is epitaxially grown on the center layer. In other embodiments, the top layer may be transferred onto the top layer or there may be a further layer arranged between the top layer and the center layer. For fabricating the slot waveguide 200 of FIG. 2, the top layer is an a-Si layer with a refractive index of 3.98. The slot waveguide is formed such that the second refractive index is lower than the first refractive index and lower than the third refractive index.

[0083] The slot waveguide as made by the method 500 may be integrated in a phase-shifter which may be implemented in a resonator or interferometer for forming an EO modulator, or may be included in an EPIC in the FEOL.

[0084] In summary, an integrated EO phase shifter comprising a slot waveguide formed by a vertical Si—Si.sub.1-xGe.sub.x-BTO-Si stack with 0<x≤1 is proposed. The electrodes are formed by doped Si layers enabling large electric field strengths at CMOS compatible driver voltages to obtain a strong LEOE inside the BTO layer. This gives perspective to highly efficient EO modulators using the LEOE in a PIC technology. Further, the solution proposed here may simplify the development of a FEOL integration, since the electrodes are formed by doped Si layers.

[0085] The present invention relates to a slot waveguide formed by a vertical material stack comprising a top layer with a first refractive index, a center layer including a ferroelectric material and with a second refractive index, and a Si.sub.1-xGe.sub.x pseudosubstrate layer with 0<x≤1 and with a third refractive index. The center layer is grown on the Si.sub.1-xGe.sub.x pseudosubstrate layer. The second refractive index is lower than the first refractive index and lower than the third refractive index. The slot waveguide can be included in a phase-shifter including two vertically arranged electrodes configured for providing a vertical electrical field extending between the top layer and the bottom layer of the slot waveguide and for providing a CMOS compatible driver voltage. The phase-shifter can be configured for providing a linear electro-optical effect inside the center layer of the slot waveguide. This configuration allows integrating the phase-shifter in the FEOL of an EPIC.