METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, COMPONENT FOR USE THEREIN AND CORRESPONDING SEMICONDUCTOR DEVICE
20220199500 · 2022-06-23
Assignee
Inventors
Cpc classification
H01L21/4821
ELECTRICITY
H01L23/49861
ELECTRICITY
International classification
Abstract
A leadframe includes a pattern of electrically-conductive formations with one or more sacrificial connection formations extending bridge-like between a pair of electrically-conductive formations. The sacrificial connection formation or formations are formed at one of the first surface and the second surface of the leadframe and have a thickness less than the leadframe thickness between the first surface and the second surface. A filling of electrically-insulating material is molded between the electrically-conductive formations of the leadframe, with electrically-insulating material molded between the connection formation(s) and the other surface of the leadframe. The sacrificial connection formation(s) counter deformation and displacement of parts during formation and pre-molding of the leadframe.
Claims
1. A method, comprising: processing a sheet which includes a first surface, a second surface opposite the first surface, and a leadframe thickness between the first surface and the second surface, to form a leadframe which includes a semiconductor chip mounting area, a pattern of electrically-conductive formations and at least one connection formation extending bridge-like between a pair of electrically-conductive formations in said pattern of electrically-conductive formations; wherein the at least one connection formation is at one of the first surface and the second surface has a formation thickness that is less than said leadframe thickness; molding a filling of electrically-insulating material between electrically-conductive formations in said pattern of electrically-conductive formations, with electrically-insulating material from said filling present between said at least one connection formation and the other of the first surface and the second surface of the leadframe; and eliminating said at least one connection formation between said pair of electrically-conductive formations in said pattern of electrically-conductive formations.
2. The method of claim 1, wherein processing the sheet comprises performing a first half-etching from the first surface of the sheet and performing a second half-etching from the second surface of the sheet to form said leadframe, and wherein molding comprises filling openings provided by said first and second half-etchings with the electrically-insulating material and solidifying the electrically-insulating material filling the openings to have a first surface coplanar with the first surface of the processed sheet and have a second surface coplanar with the second surface of the processed sheet.
3. The method of claim 1, further comprising mounting a semiconductor chip to the semiconductor chip mounting area.
4. The method of claim 1, wherein the semiconductor chip mounting area is present at the first surface and the at least one connection formation is present at the second surface.
5. The method of claim 1, wherein the at least one connection formation is formed together with said pattern of electrically-conductive formations in the leadframe.
6. The method of claim 1, wherein processing comprises etching metal material of the sheet to form the at least one connection formation and said pattern of electrically-conductive formations.
7. The method of claim 1, wherein the at least one connection formation thickness is approximately half said leadframe thickness.
8. A leadframe having a first surface and a second surface opposite the first surface and a leadframe thickness between the first surface and the second surface, comprising: a semiconductor chip mounting area at the first surface; a pattern of electrically-conductive formations; at least one connection formation extending bridge-like between a pair of electrically-conductive formations in said pattern of electrically-conductive formations; wherein the at least one connection formation is located at one of the first surface and the second surface of the leadframe and has a formation thickness less than said leadframe thickness; and a filling of electrically-insulating material molded between electrically-conductive formations in said pattern of electrically-conductive formations, with electrically-insulating material from said filling molded between said at least one connection formation and the other of the first surface and the second surface of the leadframe, and said filling having a first surface coplanar with the first surface of the leadframe and having a second surface coplanar with the second surface of the leadframe.
9. The leadframe of claim 8, wherein the at least one connection formation is located at the second surface of the leadframe.
10. The leadframe of claim 8, wherein the at least one connection formation thickness is approximately half said leadframe thickness.
11. The leadframe of claim 8, wherein the semiconductor chip mounting area, the pattern of electrically-conductive formations and the at least one connection formation are defined by first half-etch openings extending from the first surface second half-etch openings extending from the second surface.
12. A semiconductor device, comprising: a leadframe having a first surface and a second surface opposite the first surface and a leadframe thickness between the first surface and the second surface, and including: a semiconductor chip mounting area at the first surface; and a pattern of electrically-conductive formations; a first filling of electrically-insulating material molded between electrically-conductive formations in said pattern of electrically-conductive formations; a semiconductor chip mounted to the semiconductor chip mounting area; and at least one recess at one of the first surface and the second surface of the leadframe, the at least one recess extending bridge-like between a pair of electrically-conductive formations in said pattern of electrically-conductive formations; wherein the at least one recess has a depth less than said leadframe thickness between the first surface and the second surface and said pair of electrically-conductive formations in said pattern of electrically-conductive formations are mutually electrically insulated at said recess.
13. The semiconductor device of claim 12, further comprising a second filling of electrically-insulating material molded over the semiconductor chip and onto the first surface of the leadframe and first filling.
14. The semiconductor device of claim 12, further comprising, at said recess, mutually protruding portions of the electrically-conductive formations which form end abutments of at least one connection formation which would have extended bridge-like between the pair of electrically-conductive formations in said pattern of electrically-conductive formations.
15. The semiconductor device of claim 14, wherein the mutually protruding portions are located at one of the first surface and the second surface of the leadframe and have a portion thickness less than said leadframe thickness.
16. The semiconductor device of claim 12, wherein the at least one recess is located at the second surface of the leadframe.
17. The semiconductor device of claim 12, wherein said first filling has a first surface coplanar with the first surface of the leadframe and has a second surface coplanar with the second surface of the leadframe.
18. The semiconductor device of claim 12, wherein the semiconductor chip mounting area and the pattern of electrically-conductive formations are defined by first half-etch openings extending from the first surface second half-etch openings extending from the second surface, said first and second half-etched openings filled by said first filling.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0022] One or more embodiments will now be described, by way of example only, with reference to the annexed figures, wherein:
[0023]
[0024]
[0025]
[0026]
[0027]
[0028] It will be appreciated that, for the sake of clarity and ease of understanding, the various figures may not be drawn to a same scale.
DETAILED DESCRIPTION
[0029] In the ensuing description, various specific details are illustrated in order to provide an in-depth understanding of various examples of embodiments according to the description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that various aspects of the embodiments will not be obscured.
[0030] Reference to “an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment”, “in one embodiment”, or the like, that may be present in various points of the present description do not necessarily refer exactly to one and the same embodiment. Furthermore, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments. The headings/references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.
[0031] Also, throughout the figures, like parts or elements are indicated with like reference symbols, and a corresponding description will not be repeated for each and every figure for brevity.
[0032] The designation leadframe (or lead frame) is currently used (see, for instance the USPC Consolidated Glossary of the United States Patent and Trademark Office) to indicate a metal frame which provides support for a semiconductor chip or die as well as electrical leads to couple the semiconductor chip or die to other electrical components or contacts.
[0033] Essentially, a leadframe comprises an array of electrically-conductive formations (leads) which from a peripheral location extend inwardly in the direction of the semiconductor chip or die, thus forming an array of electrically-conductive formations from the die pad having at least one semiconductor chip or die attached thereon. This may be via a die attach adhesive (a die-attach film or DAF, for instance).
[0034] Electrical coupling of the leads in the lead frame with the semiconductor chip or die may be via wires forming a wire-bonding pattern around the chip or die.
[0035] The leadframe together with the semiconductor die or dice (currently referred to also as semiconductor chip or chips) mounted thereon is one of the main parts of the plastic package of a semiconductor device. It is made of electrically-conductive material (metal such as copper, for instance) and configured and shaped to support the die or dice attached thereon using different interposed material: glue, tape, solder paste.
[0036] Various types of semiconductor devices may benefit from using pre-molded leadframes. A pre-molded leadframe includes resin/plastic material around the metal leads and the die paddles onto which semiconductors chips or dice can be attached; a molding compound (epoxy resin, for instance) is subsequently molded onto the chips or dice attached onto the pre-molded leadframe.
[0037]
[0038] As illustrated (merely by way of example) in
[0039] As illustrated herein by way of example, the leadframe 10 (for use in a semiconductor device such as an electronic fuse—briefly e-fuse of eFuse, for example) may include other pads or paddles 14′, 14″ configured to be coupled to (power) connections such as so-called ribbons for the semiconductor chip or chips IC (shown in dashed outline).
[0040] Those of skill in the art will easily appreciate that the description provided herein in connection with the die pad 14 also applies to pads or paddles such as 14′ and/or 14″.
[0041] A conventional technology used to produce a leadframe such as 10 is photoetching. Raw (e.g. copper) sheet in the form of panels or reels are covered top/bottom with resist that is developed by masking and etched. Metal exposed is etched away and the resist eventually removed. Both leads 12 and pads/paddles 14, 14′, and 14″ can be formed simultaneously with this technology.
[0042] Semiconductor dice such as the integrated circuit IC shown in the figures are attached to the pads such as 14 and gold, silver or copper wires (not visible in the figures for simplicity) are provided during a wire-bonding process in order to connect the die/dice with the leads/pads. After wire bonding, encapsulation/solder plating steps complete the packaging flow.
[0043] In those types of semiconductor devices using pre-molded leadframes, the “naked” leadframe of
[0044] Such a pre-molded leadframe is visible in
[0045] A molding compound is subsequently molded onto the (pre-molded) leadframe 10 having chips or dice 14 attached thereon. Such a molding compound (epoxy resin, for instance, different or identical to the pre-mold resin 16) is not visible in
[0046] In general terms, pre-molded leadframe technology as discussed in the foregoing is conventional in the art, which makes it unnecessary to provide a more detailed description herein.
[0047] During the pre-molded leadframe manufacturing process (see
[0048] As noted, the various structures (leads 12, pads or paddles 14, 14′, 14″, including die pads 14) should desirably retain their position with displacement or deformation avoided during leadframe formation and during filling by the pre-mold resin.
[0049] In one or more embodiments, temporary (sacrificial) connections may be provided as exemplified at 100 in
[0050] In one or more embodiments, the connections 100 can be provided as half-etched formations at the bottom or back side of the leadframe during the etching process which leads to producing the “naked” leadframe 10 of
[0051] As visible in the cross-sectional view of
[0052] According to current language in the art, the designation “half-etched” is used herein to denote connections 100 that do not extend over the whole depth or height of the leadframe 10 (as measured between the opposed surfaces of the leadframe 10), without this implying that the connections 100 should have by way of necessity a thickness/height equal or in the vicinity of 50% the thickness/height of the leadframe 10. As shown in
[0053] Depending on the applications/processes, the thickness/height of the connections 100 can be chosen in order to facilitate subsequent removal of the connections 100 (as schematically illustrated in dashed lines at SE in
[0054] As illustrated in
[0055] Removal of the connections 100 may involve, for instance, a (further) etching step of the leadframe 10.
[0056] Such (selective) etching—as indicated by SE in
[0057] As discussed, the connections 100 facilitate keeping the leadframe structure firmer and stronger during formation of the leadframe 10 (by etching, for instance) as well as during pre-molding, reducing the risk of undesired deformation and displacement of parts.
[0058] As can be appreciated comparing
[0059] As illustrated herein by way of example, the leadframe 10 may include other pads or paddles 14′, 14″ configured to be receive (power) connections such as so-called ribbons or clips R coupled to the semiconductor chip or chips IC (shown in dashed outline).
[0060] A molding compound 18 is molded onto the (pre-molded) leadframe 10 having the chip(s) IC and electrical contacts (ribbons) R arranged thereon at the top or front surface, facing upward in
[0061] Of course, reference to an electronic fuse as a semiconductor device 20 to which embodiments may apply is merely by way of example and is not to be construed in a limiting sense of the embodiments.
[0062] The representation of
[0063] These residues 100′ may include notches or recesses in the bottom or back surface of the leadframe 12 (and the device 20) at those locations where the connections 100 were originally provided, with these connections subsequently removed (“etched out”, for instance) to provide electrical insulation between electrically-conductive structures of the leadframe 10, such as 14 and 14′ in
[0064] It is noted that in certain embodiments, residues 100′ may include notches or recesses which are subsequently at least partly filled by other materials such as plating.
[0065] In any case the residues 100′ remain and their presence can be detected in a final complete device as “testimonials” of the provision and subsequent removal of the connections 100, that is as evidence of connection removal.
[0066] As illustrated in
[0067] One or more embodiments thus effectively reduce undesired deformation and displacement of a leadframe during formation thereof (via etching, for instance) and during pre-molding, while saving space for additional pads/paddles and signal leads, with no particular constraints in design, facilitating manufacturing of smaller packages.
[0068] To sum up, one or more embodiments may concern a method of manufacturing semiconductor devices (for instance, 20), wherein the method comprises: arranging at least one semiconductor chip (for instance, IC) onto at least one semiconductor chip mounting area (for instance, the die mounting pad 14) in a first (top or front, for instance) surface of a leadframe (for instance, 10), the leadframe comprising a pattern of electrically-conductive formations (for instance, leads 12 and pads/paddles 14, 14′, 14″) and having a second (bottom or back, for instance) surface opposite the first surface and a leadframe thickness between the first surface and the second surface (that is, measured in a direction normal to the general plane of the leadframe).
[0069] A method as exemplified herein may comprise: forming (providing) at least one (sacrificial) connection formation (for instance, 100) extending bridge-like between a pair of electrically-conductive formations (see, for instance, 14, 14′ in
[0070] A method as exemplified herein may comprise forming the at least one connection formation at the second (for instance, bottom or back) surface of the leadframe. A method as exemplified herein may comprise forming or providing (for instance, via etching) the at least one connection formation together with said pattern of electrically-conductive formations in the leadframe.
[0071] A method as exemplified herein may comprise forming (providing) the at least one connection formation and said pattern of electrically-conductive formations by etching metal material.
[0072] A method as exemplified herein may comprise forming (providing) the at least one connection formation with a thickness approximately half said leadframe thickness between the first surface and the second surface.
[0073] As used herein, the wording “approximately” denotes a technical feature being produced within the technical tolerance of the method used to manufacture it.
[0074] A leadframe (such as 10, for instance) as exemplified herein lends itself to being supplied as a component for use in a method as exemplified herein. Such a component may be provided as a “naked” (e.g. metal-only) leadframe as exemplified in
[0075] Advantageously, the at least one connection formation may be located at the second surface of the leadframe (10).
[0076] Advantageously, the at least one connection formation may have a thickness approximately half said leadframe thickness between the first surface and the second surface of the leadframe.
[0077] Here again, the wording “approximately” denotes a technical feature being produced within the technical tolerance of the method used to manufacture it.
[0078] A component as discussed herein may be likewise supplied as a “pre-molded” (e.g. metal plus pre-mold resin) leadframe as exemplified in
[0079] A semiconductor device (see, for instance, 20 in
[0080] In a semiconductor device as exemplified herein, the at least one recess (for instance, 100′) may be located at the second surface of the leadframe.
[0081] Without prejudice to the underlying principles, the details and the embodiments may vary, even significantly, with respect to what has been described by way of example only without departing from the scope of the embodiments.
[0082] The claims are an integral part of the technical disclosure provided herein in connection with the embodiments.
[0083] The extent of protection is determined by the annexed claims.