Tap stabilizer method and structure for coherent optical receiver

Abstract

A method and structure for a coherent optical receiver device. Timing recovery (TR) is implemented after channel dispersion (i.e., chromatic dispersion (CD) and polarization mode dispersion (PMD)) compensation blocks. This architecture provides both improves performance and reduces power consumption of the device. Also, a TR loop is provided, enabling computing, by an error evaluation module, a first sampling phase error (SPE) and computing, by a timing phase information (TPI) module coupled to the error evaluation module, a second SPE from a plurality of CD equalizer taps PMD equalizer taps. The first and second SPE are combined into a total phase error (TPE) in a combining module, and the resulting TPE is filtered by a timing recovery (TR) filter coupled to an interpolated timing recovery (ITR) module and the combining module. The ITR module then synchronizes an input signal of the coherent optical receiver according to the TPE.

Claims

1. A method of operating a coherent optical receiver, the method comprising: receiving at equalizer circuitry an input signal from a time variant optical channel, the input signal comprising a plurality of polarization signals, and a transfer matrix of the equalizer circuitry comprising a plurality of taps; based on the plurality of taps, compensating for polarization mode dispersion of the plurality of polarization signals to generate an equalized signal, calculating a determinant based on the transfer matrix and estimating a first sampling phase error based on the determinant; performing timing phase error compensation including (i) based on the first sampling phase error, determining a mean sampling phase error to prevent shifting of the plurality of taps due to interaction between the timing phase error compensation and symbol error compensation, and (ii) based on the mean sampling phase error, synchronizing a clock of the coherent optical receiver with phase of the input signal to generate a synchronized signal based on the equalized signal; sampling the synchronized signal to generate a recovered data signal; and performing the symbol error compensation including, based on at least one of the synchronized signal or the recovered data signal, determining a symbol error and adjusting the plurality of taps to compensate for the symbol error.

2. The method of claim 1 wherein the input signal is a dual-polarization input signal comprising a x-type polarization input signal and a y-type polarization input signal.

3. The method of claim 1, further comprising: determining a second sampling phase error based on at least one of the synchronized signal or the recovered data signal; and generating the mean sampling phase error based on the second sampling phase error.

4. The method of claim 3, wherein the second sampling phase error is computed according to a baud rate synchronization technique based on a Muller and Mueller phase error.

5. The method of claim 1, further comprising performing chromatic dispersion compensation on the input signal to generate the equalized signal.

6. The method of claim 1, wherein: calculating the determinant comprises calculating a determinant of the transfer matrix; and the first sampling phase error is estimated based on the determinant of the transfer matrix.

7. The method of claim 1, wherein: calculating the determinant comprises calculating a determinant of a product of the transfer matrix and a conjugate transpose of the transfer matrix; and the first sampling phase error is estimated based on the determinant of the product of the transfer matrix and the conjugate transpose of the transfer matrix.

8. The method of claim 1, further comprising: determining a second sampling phase error based on at least one of the synchronized signal or the recovered data signal; and generating the mean sampling phase error based on the second sampling phase error.

9. The method of claim 8, further comprising generating the mean sampling phase error based on a sum of the first sampling phase error and the second sampling phase error.

10. The method of claim 8, further comprising determining the second sampling phase error and the symbol error based on the synchronized signal and the recovered data signal.

11. The method of claim 1, further comprising: receive the plurality of polarization signals via a plurality of inputs of a multiple-input multiple-output (MIMO) feedforward equalizer of the equalizer circuitry; and output a second plurality of polarization signals via a plurality of outputs of the MIMO feedforward equalizer; and generating the synchronized signal based on the second plurality of polarization signals.

12. The method of claim 1, further comprising: operating the equalizer circuitry in a frequency domain; and performing the timing phase error compensation in a time domain.

13. The method of claim 1, wherein a frequency domain representation of the transfer matrix of the equalizer circuitry includes the plurality of taps.

14. A coherent optical receiver comprising: an input configured to receive from a time variant optical channel an input signal including a plurality of polarization signals; equalizer circuitry configured to, based on a plurality of taps, compensate for polarization mode dispersion of the plurality of polarization signals to generate an equalized signal, wherein a transfer matrix of the equalizer circuitry includes the plurality of taps; timing phase circuitry configured to calculate a determinant based on the transfer matrix and estimate a first sampling phase error based on the determinant; timing recovery circuitry configured to perform timing phase error compensation including (i) based on the first sampling phase error, determine a mean sampling phase error to prevent shifting of the plurality of taps due to interaction between the timing phase error compensation and symbol error compensation, and (ii) based on the mean sampling phase error, synchronize a clock of the coherent optical receiver with phase of the input signal to generate a synchronized signal based on the equalized signal; and symbol recovery circuitry configured to (i) sample the synchronized signal to generate a recovered data signal, and (ii) perform the symbol error compensation including, based on at least one of the synchronized signal or the recovered data signal, determining a symbol error and adjusting the plurality of taps to compensate for the symbol error.

15. The coherent optical receiver of claim 14, wherein the timing phase circuitry is configured to: when calculating the determinant, calculate a determinant of the transfer matrix; and estimate the first sampling phase error based on the determinant of the transfer matrix.

16. The coherent optical receiver of claim 14, wherein the timing phase circuitry is configured to: when calculating the determinant, calculate a determinant of a product of the transfer matrix and a conjugate transpose of the transfer matrix; and estimate the first sampling phase error based on the determinant of the product of the transfer matrix and the conjugate transpose of the transfer matrix.

17. The coherent optical receiver of claim 14, wherein: the symbol recovery circuitry is configured to determine a second sampling phase error based on at least one of the synchronized signal or the recovered data signal; and the timing recovery circuitry is configured to generate the mean sampling phase error based on the second sampling phase error.

18. The coherent optical receiver of claim 17, wherein the timing recovery circuitry is configured to generate the mean sampling phase error based on a sum of the first sampling phase error and the second sampling phase error.

19. The coherent optical receiver of claim 17, wherein the symbol recovery circuitry is configured to determine the second sampling phase error and the symbol error based on the synchronized signal and the recovered data signal.

20. The coherent optical receiver of claim 14, wherein: the equalizer circuitry includes a multiple-input-multiple-output (MIMO) feedforward equalizer, the MIMO feedforward equalizer is configured to receive the plurality of polarization signals via a plurality of inputs and output a second plurality of polarization signals via a plurality of outputs; and the timing recovery circuitry is configured to generate the synchronized signal based on the second plurality of polarization signals.

21. The coherent optical receiver of claim 14, wherein: the equalizer circuitry is configured to operate in a frequency domain; and the timing recovery circuitry is configured to perform the timing phase error compensation in a time domain.

22. The coherent optical receiver of claim 14, wherein a frequency domain representation of the transfer matrix of the equalizer circuitry includes the plurality of taps.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In order to more fully understand the present invention, reference is made to the accompanying drawings. Understanding that these drawings are not to be considered limitations in the scope of the invention the presently described embodiments and the presently understood best mode of the invention are described with additional detail through the use of the accompanying drawings in which:

(2) FIG. 1 is a simplified diagram illustrating a block diagram of a coherent optical receiver according to an example of the present invention.

(3) FIG. 2 is a simplified diagram illustrating a block diagram of a portion of a coherent optical receiver according to an example of the present invention.

(4) FIG. 3A-3D are simplified graphs illustrating simulations for a coherent optical receiver according to conventional example.

(5) FIG. 4A-4D are simplified graphs illustrating simulations for a coherent optical receive according to an example of the present invention.

(6) FIG. 5A-5D are simplified graphs illustrating simulations for a coherent optical receiver according to conventional example.

(7) FIG. 6A-6D are simplified graphs illustrating simulations for a coherent optical receive according to an example of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

(8) The present invention relates to communication systems and integrated circuit (IC) devices. More particularly, the present invention provides for improved methods and devices for optical communication.

(9) The following description is presented to enable one of ordinary skill in the art to make and use the invention and to incorporate it in the context of particular applications. Various modifications, as well as a variety of uses in different applications will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to a wide range of embodiments. Thus, the present invention is not intended to be limited to the embodiments presented, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

(10) In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without necessarily being limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.

(11) The reader's attention is directed to all papers and documents which are filed concurrently with this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference. All the features disclosed in this specification, (including any accompanying claims, abstract, and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

(12) Furthermore, any element in a claim that does not explicitly state “means for” performing a specified function, or “step for” performing a specific function, is not to be interpreted as a “means” or “step” clause as specified in 35 U.S.C. Section 112, Paragraph 6. In particular, the use of “step of” or “act of” in the Claims herein is not intended to invoke the provisions of 35 U.S.C. 112, Paragraph 6.

(13) Please note, if used, the labels left, right, front, back, top, bottom, forward, reverse, clockwise and counter clockwise have been used for convenience purposes only and are not intended to imply any particular fixed direction. Instead, they are used to reflect relative locations and/or directions between various portions of an object.

(14) Clock timing recovery (TR) critical for data communications, and optical data communications are no exception. Certain conventional devices implement timing recovery operations with intersymbol interference (ISI)-free samples. However, there is an interaction problem between timing synchronization and equalization in coherent optical applications. A high higher of multiplications and oversampling is required by squared or fourth-power based TR algorithms, which leads to increased power consumption. Examples of the present invention address this problem with a receiver architecture based on asynchronous frequency domain equalization.

(15) In an example, the present invention provides for the TR operation after channel dispersion compensation blocks (e.g., for chromatic dispersion (CD) and polarization mode dispersion (PMD)). This architecture provides both improves performance and reduces power consumption of the receiver device. Performance is improved because channel impairments (e.g., high order PMD, residual CD, very low excess bandwidth, etc.) do not impact the TR operation. The latency of the TR loop is not affected since the feed-forward equalization (FFE) equalizer is not included within the TR loop. Power consumption is reduced because the use of the FFE immediately after the bulk chromatic dispersion (BCD) equalizer, which enables residual CD and PMD to be jointly compensated in only one frequency-domain (FD) equalizer. Using a frequency domain block least-means-square (LMS) adaptation reduces the complexity of the device architecture. Further, baud rate timing recovery algorithms, such as Muller and Mueller (M&M) can be adopted. Thus, in an example, the present invention adopts an asynchronous FD adaptive equalizer to implement timing recovery with equalized signals, and to reduce implementation complexity.

(16) FIG. 1 is a simplified diagram illustrating a block diagram of a coherent optical receiver according to an example of the present invention. As shown, device 100 can include an input signal; a first fast Fourier transform (FFT) module receiving the input signal, the first FFT module 111 being configured to compute a first discrete Fourier transform (DFT) of the input signal; a chromatic dispersion (CD) equalizer module 120 coupled to the first FFT module 111, the CD equalizer module 120 being configured to compensate for CD affecting the input signal; a polarization mode dispersion (PMD) equalizer module 130 coupled to the CD equalizer and a least means square (LMS) module 180, the PMD equalizer module 130 being configured to compensate for PMD affecting the input signal following compensation by the CD equalizer module. The PMD equalizer module 130 includes a plurality of PMD taps. In a specific example, the CD equalizer module includes a non-adaptive frequency-domain (FD) equalizer, and the PMD equalizer module includes an adaptive FD equalizer. Further, the input can be a dual polarization input with an x-type and y-type inputs.

(17) In an example, the device can also include an inverse FFT (IFFT) module 140 coupled to the PMD equalizer module 130, the IFFT module being configured to compute an inverse DFT of the input signal; an interpolated timing recovery (ITR), slicer, and error evaluation module 150 coupled to the IFFT module 140. The ITR, slicer, and the error evaluation can be separate modules, the ITR module being configured to retime the input signal, the slicer module being configured to derive the data stream, and the error evaluation module being configured to retime the input signal. Further details are provided in reference to FIG. 2.

(18) In an example, the device can include a zero padding module 160 coupled to the slicer and error evaluation module 150, the zero padding module 160 being configured to increase a sampling rate of the input signal; and a second FFT module 170 coupled to the zero padding module 160, the second FFT module 170 being configured to compute a second DFT of the input signal. In an example, the LMS module 180 is coupled to the second FFT module 170, the CD equalizer module 120, and the PMD equalizer module 130. The LMS module 180 outputs to the PMD equalizer module 130 and is configured to filter the input signal. Those of ordinary skill in the art will recognize other variations, modifications, and alternatives.

(19) The reduction of complexity results from not having to use separate FD BCD and FFE equalizers. As shown in FIG. 1, only one (dual polarization) FFT and only one (dual polarization) IFFT are required in the signal path. An architecture using separate FD blocks for the BCD and FFE requires extra FFTs and IFFTs as a result of going back and forth from the frequency domain to the time domain. Further, the LMD update can be viewed as computing a correlation between the input signal and the error. Here, this correlation is computed in the frequency domain, which reduces complexity the same way as in convolution computations.

(20) With this architecture, an interaction problem arises when TR is achieved after the adaptive equalizer (i.e., PMD equalizer). This problem occurs because the adaptation algorithm of the equalizer and the timing-synchronizer use the same (equalized) signal as their input. The equalizer tries to compensate the misadjustment of the discrete time impulse response due to the sampling phase error, while the TR tries to equalize the distortion of the impulse response by changing the sampling phase. As a consequence, the timing phase and the equalizer taps are drifting. Conventional solutions to this problem have severe drawbacks in (time variant) coherent optical channels. Making the timing loop much faster than the equalizer can mitigate this interaction problem, but the timing phase may still drift slowly over long periods of time.

(21) According to an example of the present invention, a constrained adaptive algorithm can be used to reduce or eliminate strong interaction between the adaptive equalizer and the timing recovery loop. Constraining multiple equalizer taps can be done if the adaptive filter is known to have a certain characteristic (e.g., linear phase implies tap symmetry). A constrained adaptive algorithm can also be applied in which the magnitude and the phase responses of the adaptive equalizer remain unchanged at a given frequency. Timing phase information (TPI) contained within the equalizer taps can also be fed into the timing recovery loop as a factor for computing sampling phase error.

(22) FIG. 2 is a simplified diagram illustrating a block diagram of a portion of a coherent optical receiver according to an example of the present invention. As shown, device 200 includes a PMD equalizer module 210, which is similar to the PMD equalizer module 130 of FIG. 1. This PMD equalizer is coupled to an ITR module 220. In a specific example, an IFFT module (such as IFFT module 140 of FIG. 1) is configured between the PMD equalizer module 210 and the ITR module 220. The ITR module is configured to synchronize the input signal according to a tap stabilizing algorithm.

(23) Let c be the impulse response of the equalizer and τ.sub.n be the timing error. Assuming that the timing error is small, the equalizer impulse response in the presence of timing error can be expressed as a linear function of the timing error τ.sub.n as follows:
c(E(τ.sub.n))=s.sub.cE(τ.sub.n)+c.sub.τ=0
where s.sub.c is the vector of the slope of the equalizer coefficients and E(τ.sub.n) comes from the averaging of the equalizer loop.

(24) Since the TR loop is achieved after the adaptive equalizer, its timing function will be modified as a result of the variation of the equalizer coefficients. If c.sub.τ=0 is available, it is possible to extract the mean timing error by adding a new timing-error signal obtained from the equalizer taps as follows:
s.sub.cE(τ.sub.n)=c(E(τ.sub.n))−c.sub.τ=0
This approach requires a priori knowledge of the particular equalizer coefficients at an optical timing phase (c.sub.τ=0).

(25) In an example, the present tap stabilizer algorithm can be used to obtain sampling phase information based on the response of an multiple input multiple output (MIMO) FFE. The algorithm can use the Jones matrix because it is unitary, its determinant is independent of the fiber impairments (i.e., DGD, second order PMD (SOPMD)), and contains information of the timing error. This scheme is able to provide reliable information even in the presence of highly dispersive channels. Furthermore, this scheme is able to work with any roll-off factor and can be applied to blind adaptation procedures.

(26) The channel transfer matrix at the FFE input can be written as follows:
H(ω)=G(ω)J(ω)
where the scalar linear factor G(ω) represents the total response of the transmit pulse, residual CD, and receive pulse, while J(ω) is the PMD Jones unitary matrix (i.e., det{J(ω)}=1) given by the following:

(27) $J\left(\omega \right)=\left[\begin{array}{cc}U\left(\omega \right)& V\left(\omega \right)\\ -V^{*}\left(\omega \right)& U^{*}\left(\omega \right)\end{array}\right]$
The determinant of the channel transfer matrix is as follows:
det{H(ω)}=G.sup.2(ω)det{J(ω)}=G.sup.3(ω)
Here, the determinant is not affected by the PMD.

(28) Let F(ω) be the transfer matrix of the FSE given by the following:

(29) $F\left(\omega \right)=\left[\begin{array}{cc}{F}_{11}\left(\omega \right)& F_{12}\left(\omega \right)\\ F_{21}\left(\omega \right)& F_{22}\left(\omega \right)\end{array}\right]$
From the above, F(ω) can be rewritten as follows:
F(ω)=P(ω)J.sup.H(ω)
where P(ω) is a scalar linear factor that depends on G(ω) (and possibly the noise power for minimum mean-square error (MMSE) criteria), while the superscript “H” denotes transpose and conjugate.

(30) The determinant of the equalizer transfer matrix is as follows:
det{F(ω)}=P.sup.2(ω)det{J.sup.H(ω)}=P.sup.2(ω)
Here, the determinant is not affected by the PMD. That is, the determinant is independent of PMD variation such as polarization rotation.

(31) Let J(ω.sub.0, t) and F(ω.sub.0, t)=P(ω.sub.0)J.sup.H(ω.sub.0, t) be the PMD matrix and the FSE transfer matrix at a given frequency ω.sub.0 and instant t, respectively. For simplicity, the CD parameter is assumed to not change with time (i.e., P(ω.sub.0, t)=P(ω.sub.0)). The determinant can be defined as follows:
S(ω.sub.0,t)=det{F(ω.sub.0,t)}=P.sup.2(ω.sub.0)
Here, S(ω.sub.0, t) is independent of PMD time variations.

(32) Let F(ω.sub.0,0) be the transfer matrix at instant t=0. In the presence of a clock offset ΔT, the transfer matrix at instant t is as follows:
F(ω.sub.0,t)=e.sup.−jω.sup.0.sup.ωP(ω.sub.0)J.sup.H(ω.sub.0,t)
where τ=ΔT/(T+ΔT)t<200×, with T being the symbol period.
From the above, S(ω.sub.0, t) is as follows:
S(ω.sub.0,t)=e.sup.−j2ω.sup.0.sup.τS(ω.sub.0,0)
from which the determinant contains information of the sampling phase error.

(33) Denoting |S(ω.sub.0,t)|=K and taking into account the following:
S(ω.sub.0,t)=e.sup.−j2ω.sup.0.sup.τS(ω.sub.0,0)
Note that p(ω.sub.0, t) is as follow:
p(ω.sub.0,t)=S(ω.sub.0,t)S*(ω.sub.0,0)=K.sup.2e.sup.−j2ω.sup.τ
Then, the phase error signal can be obtained from the following:
ε.sub.fse=−angle(p(ω.sub.0,t))=2ω.sub.0ω
The sampling phase error is derived directly from the FFE taps, therefore it can be used even during a blind adaptation procedure. The phase error as defined previously can be used directly for timing recovery. Further note that P+I TR loop will avoid any FFE tap shifting (i.e., T.fwdarw.0).

(34) In practical receivers, independent carrier recovery for each polarization can be used at the output of the FFE. In this case, the FFE taps for each polarization can be slowly rotated with arbitrary phases, as shown by the following:
F(ω.sub.0,t)=e.sup.−jω.sup.0.sup.τe.sup.jϕ(t)P(ω.sub.0)R(t)J.sup.H(ω.sub.0,t)
with the following:

(35) $R\left(t\right)=\left\{\begin{array}{cc}{e}^{\frac{{\varphi }_x\left(t\right)-{\varphi }_y\left(t\right)}{2}}& 0\\ 0& e^{\frac{-j\left({\varphi }_x\left(t\right)-{\varphi }_y\left(t\right)\right)}{2}}\end{array}\right\}\varphi \left(t\right)=\frac{{\varphi }_x\left(t\right)+{\varphi }_y\left(t\right)}{2}$
Here, R(t) is unitary and the phase of the determinant of F(ω.sub.0, 0) varies with the rotations of the FFE taps, shown by the following:
S(ω.sub.0,t)=e.sup.−j2ω.sup.0.sup.τe.sup.j2ϕ(t)S(ω.sub.0,0)

(36) Thus, the rotations of the equalizer taps impact the phase of the determinant of F(ω.sub.0, 0); therefore, it cannot be used to provide reliable information of the sampling phase. However, in order to mitigate the impact of the taps rotation on the sampling phase estimation, S(ω.sub.0, t) is defined as the determinant of the following matrix:

(37) $\begin{array}{c}{M}_f\left({\omega }_0,t\right)=F\left({\omega }_0,t\right)F^H\left(-{\omega }_0,t\right)\\ =e^{-j2{\omega }_0\tau }{.Math.P\left({\omega }_0\right).Math.}^{2}R\left(t\right)J^H\left(-{\omega }_0,t\right)R^H\left(t\right)\\ =e^{-j2{\omega }_0\tau }{.Math.P\left({\omega }_0\right).Math.}^{2}Z\left({\omega }_0,-{\omega }_0,t\right)\end{array}$
where Z(ω.sub.0, −ω.sub.0, t) is a unitary matrix for all (w.sub.0, t).
Thus, the taps rotation does not affect the phase of the determinant, which is shown as follows:
S(ω.sub.0,t)=det{M.sub.f(ω.sub.0,t)}=e.sup.−j4ω.sup.0.sup.τ|P(ω.sub.0)|.sup.4

(38) Let F(Ω.sub.0) be the transfer matrix of the discrete time FSE given by the following:

(39) $F\left({\Omega }_0\right)=\left[\begin{array}{cc}{F}_{11}\left({\Omega }_0\right)& F_{12}\left({\Omega }_0\right)\\ F_{21}\left({\Omega }_0\right)& F_{22}\left({\Omega }_0\right)\end{array}\right]$
where Ω.sub.0 is as follows:

(40) ${\Omega }_0={\omega }_0\frac{T}{\mathrm{OS}}$
where OS is an oversampling factor.

(41) Elements of F(Ω.sub.0)can be evaluated as follows:

(42) $F_{\mathrm{ab}}\left({\Omega }_0\right)=\underset{k=0}{\overset{N_{\mathrm{FSE}}-1}{.Math.}}{f}_{\mathrm{ab}}\left(k\right)e^{-\mathrm{jk}{\Omega }_0}$
where f.sub.ab(k), a, b∈[1,2] are the taps of the FSE and N.sub.FSE is the number of taps.
If Ω.sub.0 is set as follows:

(43) ${\Omega }_0=\pm \frac{\pi }{4}$
then the filtering process is simplified for VLSI implementation.

(44) Returning to the device architecture 200, an error evaluation or error computation module 250 is coupled to the ITR module 220. The error evaluation module can be configured to compute a slicer error and a first sampling phase error (SPE). The slicer error can be outputted to an LMS module, similar to LMS module 180 of FIG. 1. In order to provide a proper bandwidth for the TR loop, the sampling phase information derived from the FSE taps can be combined with a baud rate synchronization technique, such as one based on the Muller and Mueller (M&M) phase error. In a specific example, the first SPE is calculated according to a baud rate synchronization technique based on a M&M phase error, which can be represented by the following equation:

(45) ${\mathrm{.Math.}}_{\mathrm{mm}}=K_{\mathrm{mm}}ℛ\left\{{.Math.}_{{\mathrm{nN}}_p+2}^{\left(n+1\right)N_p}{\hat{a}}^{*}\left(k\right)q\left(k-1\right)-{\hat{a}}^{*}\left(k-1\right)q\left(k\right)\right)$

(46) where K.sub.mm is a certain gain,

(47) where refers to real component of a complex number,

(48) where N.sub.p is a parallelism factor,

(49) where q(k) is an input of slicer and error evaluation module, and

(50) where â* is an output of the slicer and error evaluation module.

(51) In an example, a compression module 230 can be coupled between the ITR module 220 and the error computation module 250. The compression module 230 can be configured to compress the dual polarization input signal. Further, a slicer module 240 can be coupled to both the compression module 230 and the error computation module 250. The slicer module 240 can be configured to derive a data stream from the input signal. Those of ordinary skill in the art will recognize other variations, modifications, and alternatives.

(52) In an example, the device 200 also includes a timing phase information (TPI) module 260, a combining module 270, and a timing recovery (TR) filter 280. The TPI module 260 can be coupled to the PMD equalizer module 210 or to an IFFT module that is coupled to the PMD equalizer module 210 (as described for the ITR module 220). The TPI module 260 can be configured to compute a second SPE from the plurality of PMD taps from the PMD equalizer module 210. Then, the combining module 270 can combine the first SPE and the second SPE into a total phase error (TPE). That is, the total phase error is ε.sub.t=ε.sub.mm+ε.sub.fse. The TR filter 280 can filter the TPE to be used by the ITR module 220 to synchronize the input signal.

(53) The present invention provides for device structures and methods of computing sampling phase error according to the algorithms described previously. In a specific example, the TPI module computes the second SPE according to the following equation:

(54) 0${\mathrm{.Math.}}_{\mathrm{fse}}=-K_{\mathrm{fse}}\mathrm{angle}\left(\det \left(M_f\right)\right)$$\mathrm{where}{K}_{\mathrm{fse}}=\left[2^{-1},\mathrm{.Math.},2^{-4}\right],\mathrm{and}$$\mathrm{where}{M}_f=e^{-j2{\omega }_0\tau }{.Math.P\left({\omega }_0\right).Math.}^{2}Z\left({\omega }_0,-{\omega }_0,t\right),\mathrm{where}{\omega }_0\mathrm{is}a\mathrm{given}\mathrm{frequency},\mathrm{where}\tau =\frac{\Delta T}{\left(T+\Delta T\right)t}<200\times {10}^{-6}t,\mathrm{where}P\left({\omega }_0\right)\mathrm{is}a\mathrm{CD}\mathrm{parameter},\mathrm{and}$$\mathrm{where}Z\left({\omega }_0,-{\omega }_0,t\right)\mathrm{is}a\mathrm{unitary}\mathrm{matrix}\mathrm{for}\mathrm{all}\left({\omega }_0,t\right).$

(55) In a specific example, the TPI module computes the second SPE according to the following equation:

(56) ${\mathrm{.Math.}}_{\mathrm{fse}}=2{\omega }_0\tau$$\mathrm{where}{\omega }_0\mathrm{is}a\mathrm{given}\mathrm{frequency},\mathrm{and}$$\mathrm{where}\tau =\frac{\Delta T}{\left(T+\Delta T\right)t}<200\times {10}^{-6}t,\mathrm{where}t\mathrm{is}a\mathrm{given}\mathrm{time},\mathrm{and}$$\mathrm{where}T\mathrm{is}a\mathrm{symbol}\mathrm{period}.$

(57) In an example, the present invention provides a method of operating a coherent optical receiver device. The method can include providing an input signal; computing, by a first fast Fourier transform (FFT) module receiving the input signal, a first discrete Fourier transform (DFT) of the input signal. The method can include compensating, by a chromatic dispersion (CD) equalizer module coupled to the first FFT module, for CD affecting the input signal; and compensating, by a polarization mode dispersion (PMD) equalizer module coupled to the CD equalizer module and coupled to a least means square (LMS) module and having a plurality of PMD taps, for PMD affecting the input signal following the compensation by the CD equalizer module. Further, the method can include computing, by an inverse FFT (IFFT) module coupled to the PMD equalizer module, an inverse DFT of the input signal. In an example, the method includes filtering, by the LMS module coupled to the CD equalizer module and the second FFT module and the PMD equalizer module, the input signal.

(58) In an example, the method includes computing a total sampling error from two sampling phase errors. More specifically, the method can include computing, by an error evaluation module coupled to the IFFT module, a first sampling phase error (SPE); and computing, by a timing phase information (TPI) module coupled to the error evaluation module and the IFFT module, a second SPE from the plurality of PMD taps. Then, the method includes combining, by a combining module coupled to the TPI module and the error evaluation module, the first and second SPE into a total phase error (TPE). Further, the method includes filtering, by a timing recovery (TR) filter coupled to an interpolated timing recovery (ITR) module and the combining module, the TPE. With the filtered TPE, the method includes synchronizing, by the ITR module, the input signal according to the TPE. Outside of the TR loop, the method includes computing, by a second FFT module coupled to the error evaluation module, a second DFT of the input signal, which is fed to the LMS module.

(59) FIG. 3A-3D are simplified graphs illustrating simulations for a coherent optical receiver according to conventional example. As shown, graphs 301-304 illustrate a first test case applying the constrained adaptive algorithm or tap stabilizer algorithm. Here, the LMS step-size is 2.sup.−11 and the clock offset is 0 ppm. FIG. 3A (graph 301) shows the signals at the FFE taps (i.e., PMD equalizer taps). FIG. 3B (graph 302) shows the sampling phase error computed from the PMD equalizer taps. FIG. 3C (graph 303) shows the clock error and FIG. 3D (304) shows an Rx constellation.

(60) FIG. 4A-4D are simplified graphs illustrating simulations for a coherent optical receive according to an example of the present invention. As shown, graphs 401-404 illustrate a second test case with an unconstrained adaptive algorithm (i.e., without the tap stabilizer algorithm). The LMS step-size and clock offset are the same as for FIGS. 3A-3D (i.e., 2.sup.−11 and 0 ppm, respectively). Similarly, FIG. 4A (graph 401) shows the signals at the FFE taps equalizer taps. FIG. 4B (graph 402) shows the sampling phase error computed from the PMD equalizer taps. FIG. 4C (graph 403) shows the clock error and FIG. 4D (404) shows an Rx constellation. Compared to the case of FIGS. 3A-3D, this case does not estimate the sampling phase error as accurately.

(61) FIG. 5A-5D are simplified graphs illustrating simulations for a coherent optical receiver according to conventional example. As shown, graphs 501-504 illustrate a third test case applying the tap stabilizer algorithm with a time variant differential-group-delay (DGD). Here, the LMS step-size is 2.sup.−8 and the channel is characterized by DGD=T/2.fwdarw.Rot. KHz.fwdarw.DGD=T/2. FIG. 5A (graph 501) shows the signals at the FFE taps (i.e., PMD equalizer taps). FIG. 5B (graph 502) shows the sampling phase error computed from the PMD equalizer taps. FIG. 5C (graph 503) shows the clock error and FIG. 5D (504) shows an Rx constellation.

(62) FIG. 6A-6D are simplified graphs illustrating simulations for a coherent optical receive according to an example of the present invention. As shown, graphs 601-604 illustrate a fourth test case with without the tap stabilizer algorithm with a time variant DGD. The LMS step-size and channel characterization are the same as for FIGS. 5A-5D (i.e., 2.sup.−8 and DGD=T/2.fwdarw.Rot. KHz.fwdarw.DGD=T/2, respectively). Similarly, FIG. 6A (graph 401) shows the signals at the FFE taps equalizer taps. FIG. 6B (graph 602) shows the sampling phase error computed from the PMD equalizer taps. FIG. 6C (graph 603) shows the clock error and FIG. 6D (604) shows an Rx constellation. Compared to the case of FIGS. 5A-5D, this case does not estimate the sampling phase error as accurately.

(63) While the above is a full description of the specific embodiments, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustrations should not be taken as limiting the scope of the present invention which is defined by the appended claims.