Converter circuit, corresponding device and offset compensation method

Abstract

A converter circuit includes an analog-to-digital signal conversion path. An input port receives an analog input signal having an offset, and an output port delivers a digital output signal quantized over M levels. The digital output signal is sensed by a digital-to-analog feedback path, which includes a digital-to-analog converter applying to the input port an analog feedback signal produced as a function of an M-bit digital word under control of a two-state signal having alternating first and second states. M-bit digital word generation circuitry coupled to the digital-to-analog converter and sensitive to the two-state signal produces, alternately, during the first states, a first M-bit digital word, which is a function of the digital output signal quantized over M levels, and, during the second states, a second M-bit digital word, which is a function a correction value of the offset in the analog input signal.

Claims

1. A converter circuit, comprising: an analog-to-digital signal conversion path from an input port to an output port, the input port configured to receive an analog input signal having an offset, and the output port configured to deliver a digital output signal quantized over M levels, the digital output signal resulting from conversion to digital of the analog input signal; a digital-to-analog feedback path from the output port to the input port, the feedback path comprising a digital-to-analog converter configured to apply to the input port of the analog-to-digital signal conversion path an analog feedback signal produced as a function of an M-bit digital word under control of a two-state signal having alternating first states and second states during which the two-state signal has a first value and a second value, respectively; and M-bit digital word generation circuitry sensitive to the two-state signal and configured to produce the M-bit digital word, alternately: during the first states, as a first M-bit digital word which is a function of the digital output signal quantized over the M levels; and during the second states, as a second M-bit digital word which is a function a correction value of the offset in the analog input signal.

2. The converter circuit of claim 1, wherein the digital word generation circuitry comprises two-state signal generation circuitry configured to produce the two-state signal having the alternating first states and second states, wherein the two-state signal generation circuitry comprises: a counter circuit configured to be clocked by a clock signal; and a counter threshold circuit configured to set the two-state signal to the first state and to the second state at a first count value and a second count value, respectively, of the counter circuit.

3. The converter circuit of claim 2, wherein the counter circuit comprises an N-bit counter, and the counter threshold circuit comprises N-bit thresholds, providing the first count value and the second count value, respectively.

4. The converter circuit of claim 1, wherein the digital-to-analog converter in the digital-to-analog feedback path comprises a plurality of M bias cells, wherein each bias cell in the plurality of M bias cells is individually switchable, as a function of a logical value of a respective one of the bits in the M-bit digital word, to a conductive state during which the bias cell electrically couples at least one output line of the digital-to-analog converter to at least one signal source.

5. The converter circuit of claim 4, wherein: the input port to the analog-to-digital signal conversion path comprises a differential input with a first input node and a second input node configured to receive the analog input signal applied therebetween; the digital-to-analog converter in the digital-to-analog feedback path comprises a first output line and a second output line configured to apply the analog feedback signal between the first input node and the second input node of the input port of the analog-to-digital signal conversion path; and in the conductive state, each bias cell electrically couples the first output line and the second output line of the digital-to-analog converter to a first signal source and a second signal source, respectively.

6. The converter circuit of claim 4, wherein the M-bit digital word generation circuitry comprises a dynamic matching circuit configured to receive the M-bit digital word and to cyclically vary the respective one of the bits in the M-bit digital word as a function of which each bias cell in the plurality of M bias cells is individually switchable to the conductive state.

7. The converter circuit of claim 4, wherein: the M bias cells are configured to provide respective, substantially identical bias contributions to the digital-to-analog converter; at least one of the M bias cells comprises a set of H bias sub-cells, wherein each sub-cell in the set of H bias sub-cells is configured to provide a bias current contribution to the digital-to-analog converter which is 1/H the substantially identical bias contribution; and the H bias sub-cells in the at least one of the M bias cells are configured to be switched to the conductive state: identically to one another during the first states as a function of the logical value of the respective one of the bits in the M-bit digital word to provide a respective bias contribution of the at least one of the M bias cells to the digital-to-analog converter; and differently from one another during the second states to provide a reduced bias contribution of the at least one of the M bias cells to the digital-to-analog converter, the reduced bias contribution being a function of a number of the sub-cells in the set of H bias sub-cells that are in the conductive state.

8. The converter circuit of claim 4, wherein the digital-to-analog converter in the digital-to-analog feedback path comprises a set of L supplemental bias cells activatable during the second states, as a function of a third digital word, the third digital word comprising the second M-bit digital word supplemented by a set of L bits of correction value of the offset in the analog input signal.

9. The converter circuit of claim 4, wherein each bias cell comprises an electronic switch.

10. The converter circuit of claim 9, wherein each electronic switch comprises a metal-oxide-semiconductor field-effect transistor.

11. A device, comprising: a signal source, the signal source configured to produce an analog signal having an offset; and a converter circuit comprising: an analog-to-digital signal conversion path from an input port to an output port, the input port coupled to the signal source to receive the analog signal having the offset, and the output port configured to deliver a digital output signal quantized over M levels, the digital output signal resulting from conversion to digital of the analog signal from the signal source; a digital-to-analog feedback path from the output port to the input port, the feedback path comprising a digital-to-analog converter configured to apply to the input port of the analog-to-digital signal conversion path an analog feedback signal produced as a function of an M-bit digital word under control of a two-state signal having alternating first states and second states during which the two-state signal has a first value and a second value, respectively; and M-bit digital word generation circuitry sensitive to the two-state signal and configured to produce the M-bit digital word, alternately: during the first states, as a first M-bit digital word which is a function of the digital output signal quantized over the M levels; and during the second states, as a second M-bit digital word which is a function a correction value of the offset in the analog signal.

12. The device according to claim 11, further comprising: a digital decimation filter coupled to the output port and configured to filter the digital output signal from the output port.

13. The device of claim 11, wherein the device is integrated on a semiconductor substrate.

14. A method, comprising: receiving, at an input port of an analog-to-digital signal conversion path, an analog input signal having an offset; delivering, at an output port, a digital output signal quantized over M levels, the digital output signal resulting from conversion to digital of the analog input signal; feeding back, from the output port to the input port, via a digital-to-analog feedback path comprising a digital-to-analog converter, an analog feedback signal produced as a function of an M-bit digital word; and producing the M-bit digital word, alternately: during first time intervals, as a first M-bit digital word which is a function of the digital output signal quantized over M levels; and during second time intervals interleaved with the first time intervals, as a second M-bit digital word which is a function a correction value of the offset in the analog input signal.

15. The method of claim 14, further comprising: generating a two-state signal having alternating first states and second states during which the two-state signal has a first value and a second value, respectively; selecting the first time interval in accordance with the first value of the two-state signal; and selecting the second time interval in accordance with the second value of the two-state signal.

16. The method of claim 15, further comprising: individually switching a plurality of M bias cells in the digital-to-analog converter, as a function of a logical value of a respective one of the bits in the M-bit digital word, to a conductive state during which the bias cell electrically couples at least one output line of the digital-to-analog converter to at least one signal source.

17. The method of claim 16, further comprising: differentially receiving, by first and second input nodes of the input port, the analog input signal; applying, by first and second output lines of the digital-to-analog converter, the analog feedback signal between the first and second input nodes of the input port; and electrically coupling, by each bias cell in the conductive state, the first output line and the second output line to a first signal source and a second signal source, respectively.

18. The method of claim 16, further comprising: cyclically varying the respective one of the bits in the M-bit digital word as a function of which each bias cell in the plurality of M bias cells is individually switchable to the conductive state.

19. The method of claim 16, wherein at least one of the M bias cells comprises a set of H bias sub-cells, and the method further comprises: providing, by the M bias cells, respective, substantially identical bias contributions to the digital-to-analog converter; providing, by each sub-cell in the set of H bias sub-cells, a bias current contribution to the digital-to-analog converter which is 1/H the substantially identical bias contribution; and switching the H bias sub-cells in the at least one of the M bias cells to the conductive state: identically to one another during the first states as a function of the logical value of the respective one of the bits in the M-bit digital word to provide a respective bias contribution of the at least one of the M bias cells to the digital-to-analog converter; and differently from one another during the second states to provide a reduced bias contribution of the at least one of the M bias cells to the digital-to-analog converter, the reduced bias contribution being a function of a number of the sub-cells in the set of H bias sub-cells that are in the conductive state.

20. The method of claim 16, further comprising: activating, during the second states, a set of L supplemental bias cells in the digital-to-analog converter, as a function of a third digital word, the third digital word comprising the second M-bit digital word supplemented by a set of L bits of correction value of the offset in the analog input signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) One or more embodiments will now be described, by way of example only, with reference to the annexed figures, wherein:

(2) FIG. 1 is a block diagram of a conventional converter in a current-based implementation;

(3) FIG. 2 is a block diagram of a conventional converter in a voltage-based implementation;

(4) FIG. 3 is a circuit diagram illustrating possible details of converter according to FIG. 1;

(5) FIG. 3A is a time diagram exemplary of possible operation of a converter according to FIG. 1 including details as per FIG. 3;

(6) FIG. 4 is a circuit diagram illustrating possible details of a converter according to FIG. 3;

(7) FIG. 5 is a block diagram of a converter according to embodiments of the present description in a current-based implementation;

(8) FIG. 6 is a block diagram of a converter according to embodiments of the present description in a voltage-based implementation;

(9) FIG. 7 is a circuit diagram illustrating possible details of a converter according to either one of FIG. 5 or FIG. 6;

(10) FIG. 8 is a circuit diagram illustrating possible details of a converter according to FIG. 5;

(11) FIG. 9 is a circuit diagram illustrating possible details of a voltage-based converter according to FIG. 6;

(12) FIG. 10 is a circuit diagram illustrating possible developments of the solution illustrated in FIG. 7;

(13) FIG. 11 is a circuit diagram illustrative of possible developments of a current-based converter according to FIG. 5;

(14) FIG. 12 is a circuit diagram illustrative of possible developments of a voltage-based converter according to FIG. 6;

(15) FIG. 13 is a circuit diagram illustrative of possible developments of a current-based converter according to FIG. 5; and

(16) FIG. 14 is a circuit diagram illustrative of possible developments of a voltage-based converter according to FIG. 6.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(17) In the following description various specific details are given to provide a thorough understanding of various exemplary embodiments of the present specification. The embodiments may be practiced without one or several specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring various aspects of the embodiments. Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the possible appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

(18) The headings/references provided herein are for convenience only, and therefore do not interpret the extent of protection or scope of the embodiments.

(19) The diagrams of FIGS. 1 and 2 are exemplary of the architecture of a conventional (continuous time) delta-sigma converter 10 comprising an analog-to-digital signal conversion path 12: from an input port 14 configured to receive an analog input signal affected by an offset (that is likely to have a certain offset superposed thereon), and to an output port 16 configured to deliver a digital output signal quantized over M levels as a result of (delta-sigma) conversion to digital of the analog input signal applied at the input port 14.

(20) As illustrated in FIGS. 1 and 2, the converter 10 also comprises a digital-to-analog feedback path 18 from the output port 16 to the input port 14. The feedback path 18 comprises a digital-to-analog converter 20 configured to sense and convert to analog the digital output signal at the output port 16 and to apply an analog feedback signal at the input port 14 of the analog-to-signal conversion path 12.

(21) In a possible, advantageous “differential” implementation as illustrated in FIGS. 1 and 2, the input port 14 to the analog-to-digital conversion path comprises a differential input with a first input node 141 and a second input node 142 to a (fully) differential amplifier 22 having capacitive output-input feedback paths (see the capacitors C.sub.int) providing integrator-like operation of the amplifier 22.

(22) The (differential) output from the amplifier/integrator 22 is supplied to a “rest-of-loop” filter 24 which in turn supplies via a “sampling” switch 26 operated at a frequency f.sub.s a M-level quantizer 28 which provides the digital output signal at the output port 16.

(23) Optionally, a digital decimation filter 30 can be arranged downstream the output port 16 in order to correspondingly filter the digital output signal at the output port 16.

(24) As illustrated in both FIGS. 1 and 2, the first input node 141 and the second input node 142 are configured to receive a (differential) analog input current signal I.sub.SD_IN applied thereto.

(25) In current-based implementations as illustrated in FIG. 1, the differential analog input current signal I.sub.SD_IN is expected to be obtained from a sensor S generating a sensing signal in the form of a sensing current I.sub.SENSE.

(26) In voltage-based implementations as illustrated in FIG. 2, the differential analog input current signal I.sub.SD_IN is expected to be obtained via voltage-to-current translator resistors (shown but not expressly labeled in FIG. 2 for simplicity) from a sensor S which generates a sensing signal in the form of a sensing voltage V.sub.SENSE.

(27) As illustrated in both FIGS. 1 and 2, the digital-to-analog converter 20 in the digital-to-analog feedback path 18 comprises a first output line 120 and a second output line 220 configured to apply (inject) an analog feedback (current) signal at the first input node 141 and the second input node 142 of the input port 14 of the analog-to-digital signal conversion path 12.

(28) As illustrated in both FIGS. 1 and 2, the digital-to-analog converter 20 in the digital-to-analog feedback path 18 is configured to be coupled (as discussed in the following) to compensation sources such as a generator of a current of intensity I.sub.LSB/2 (current-based implementation of FIG. 1) or generators of voltages +V.sub.LSB/2, −V.sub.LSB/2 (voltage-based implementation of FIG. 2).

(29) Here again: in current-based implementations as illustrated in FIG. 1, the differential analog feedback current signal injected at the first input node 141 and the second input node 142 of the input port 14 of the analog-to-digital signal conversion path 12 is expected to be obtained from the digital-to-analog converter 20 as a current signal;

(30) in voltage-based implementations as illustrated in FIG. 2, the differential analog feedback current signal injected at the first input node 141 and the second input node 142 of the input port 14 of the analog-to-digital signal conversion path 12 is obtained starting from voltage signals produces by the digital-to-analog converter 20 via voltage-to-current translator resistors (again shown but not expressly labeled for simplicity in FIG. 2).

(31) In conventional converters as exemplified in FIGS. 1 and 2 the DAC 20 can be realized using a return-to-zero (RTZ) technique to limit the degradation of the signal-to-noise ratio (SNR) due to clock jitter. In fact, it is possible to demonstrate that, in a converter as considered herein, the SNR using a DAC with an RTZ signal with a duty cycle DC.sub.RTZ=t.sub.on/(t.sub.on+t.sub.off) is lower by a factor (DC.sub.RTZ.sub.2/2).sup.1/2 than the SNR obtained without using a RTZ DAC.

(32) In the circuit of FIG. 1 the input signal to the converter 10 is a current signal I.sub.SD_IN, and consequently the DAC 20 in the converter is “current-based”, namely configured to produce at its output an (analog) current signal I.sub.DAC to be combined with (subtracted from, for instance) the input current signal.

(33) In FIG. 1, the current from the sensor S (to be amplified and converted to digital) is designated I.sub.SENSE. An offset component I.sub.OFF present in I.sub.SENSE can be determined during a calibration phase and subtracted via an input signal offset correction circuit OC so that current signal I.sub.SD_IN applied to the converter input (to be amplified and converted into digital) includes only a “useful” signal component (which is a function of the physical entity to be measured) from the sensor S. The I.sub.OFF current can thus be a fixed current (in DC) estimated during the calibration phase.

(34) In FIG. 2, the signal from the sensor S is a voltage signal designated V.sub.SENSE, which can be converted into a current signal via voltage-to-current translator resistors (shown but not expressly labelled for simplicity on the left-hand side of FIG. 2). Here again, an offset component I.sub.OFF can be determined during a calibration phase and subtracted via an input signal offset correction circuit OC. As exemplified in FIG. 2, the circuit OC can generate the offset current I.sub.OFF as a voltage signal designated which is converted into a current signal via voltage-to-current translator resistors (again shown but not expressly labeled for simplicity on the left-hand side of FIG. 2).

(35) In FIG. 2 the DAC 20 in the converter is “voltage-based”, namely configured to produce at its output an (analog) voltage signal with the current I.sub.DAC to be combined with the input current signal produced via voltage-to-current translator resistors (shown but not expressly labelled for simplicity on the left-hand side of FIG. 2) with a voltage drop imposed across each resistor with respect to the virtual ground voltage of the amplifies 22 at the converter input.

(36) Irrespective of possible differences in implementation details (current-based v. voltage-based) the same operating criteria apply to the converters illustrated in FIG. 1 and in FIG. 2. In both instances, input signal offset correction circuitry (primarily, the block designated OC) is provided which has a cost both in terms of semiconductor area occupied and in terms of current consumption.

(37) FIG. 3 and FIG. 4 are illustrative of possible conventional implementations of a RTZ DAC circuit 20 for use in the (current-based) architecture of FIG. 1.

(38) Similar implementations are feasible for voltage-based architectures as exemplified in FIG. 2, which will not be discussed in detail for brevity.

(39) Essentially, in both instances illustrated in FIGS. 3 and 4 the digital-to-analog converter 20 comprises a plurality of M electronic switch (bias) cells 201, . . . , 20j, . . . , 20M where M equals the number of levels of the quantizer 28.

(40) The electronic switch cells 201, . . . , 20j, . . . , 20M comprise electronic switches such as transistors. Metal-oxide-semiconductor field-effect transistor (MOSFET) transistors (both P-type and N-type) are exemplary of such electronic switches which can be made selectively conductive or non-conductive with the current flow path therethrough (source-drain in the case of field-effect transistors such as MOSFETs) made current-pervious or current-impervious as a function of a (logic) signal applied to a control electrode (gate, in the case of field-effect transistors such as MOSFETs).

(41) Whatever the implementation details (for instance the logic control signals applied to the MOSFET gates can take opposite values depending on whether a P-type or a N-type transistor is used to implement a certain electronic switch at a certain location), the cells 201, . . . , 20j, . . . , 20N are switchable under the control of a logic signal RTZ (or the negated version thereof, namely RTZ) between:

(42) a conductive state, during which the cells 201, . . . , 20j, . . . , 20N electrically couple the first output line 120 and the second output line 220 of the DAC 20 to a first signal source 20A and a second signal source 20B, respectively, and

(43) a non-conductive state during which the first and second output lines 120, 220 are decoupled from the first and second signal sources 20A and 20B.

(44) In the—purely exemplary—case considered herein, the cells 201 to 20M comprise (reference is made to a generic cell 20j with j=1, . . . , M):

(45) a first electronic switch pair 20j11, 20j12 comprising a first and a second electronic switch (P-MOS and N-MOS transistors, for instance) which, during their conductive state, couple the first output line 120 to the first signal source 20A and the second signal source 20B, respectively,

(46) a second electronic switch pair 20j21, 20j22 comprising a (further) first and a (further) second electronic switch (P-MOS and N-MOS, transistors for instance) which, during their conductive state, couple the second output line 220 to the first signal source 20A and the second signal source 20B respectively.

(47) Control nodes (gates in the case of field effect transistors such as MOSFET transistors) are provided configured to selectively provide a conductive state of these switches (transistors) 20j11, 20j12, 20j21, 20j22 as a function of the logical state of a respective digital signal applied thereto.

(48) A DAC 20 relying on a “thermometric” code will be considered here for simplicity, with no limiting intent on embodiments.

(49) In such a “thermometric” code, with M=3, for instance:

(50) a level “0” corresponds to all the 3 bits being equal to zero,

(51) a level “1” corresponds to a first bit being equal to one and second and third bit being equal to zero,

(52) a level “2” correspond to the first two bits being equal to one and the third being equal to zero, a level “3” corresponds to all the 3 bits being equal to one.

(53) Byway of contrast with such a “thermometric” arrangement, where one, two and three bits are subsequently made equal to one (just like the lines or bars of a thermometer) in a binary code, two bits are used to represent the numbers from 0 to 3, namely 00, 01, 10, 11.

(54) For representing the numbers from 0 to 7:

(55) seven bits are used with a thermometric coding (a possible “thermometric” count sequence from 0 to 7 being 0000000, 0000001, 0000011, 0000111, 0001111, 0011111, 0111111, 1111111)

(56) three bits are used to count with a binary code (a possible count sequence from 0 to 7 being 000, 001, 010, 011, 100, 101, 110, 111).

(57) A DAC as considered herein by way of example using a thermometric coding may include 7 branches, with each branch providing a unitary current (for example 7 branches with a current 1*I each).

(58) A same type of DAC operation could be achieved by considering branches with a current value weighed in a binary mode and driven via a binary code: for instance, in an exemplary case with a count from 0 to 7 one might use three branches, providing respective currents with values 4*I, 2*I and 1*I driven with the three bits of the corresponding binary representation.

(59) A DAC as exemplified in FIG. 3 (assuming again to refer to M=7 as an example) can produce a differential current I.sub.DAC as the sum of (I.sub.DAC/2)_PMOS—as produced by the PMOS transistors illustrated—and (I.sub.DAC/2)_NMOS—as produced by the NMOS transistors illustrated.

(60) More specifically, the following may thus apply:

(61) level “0”.fwdarw.(IDAC/2)_PMOS=−I−I−I−I−I−I−I=−7*I and (IDAC/2)_NMOS=−I−I−I−I−I−I−I=−7*I, and therefore IDAC=(−14*I)/2=−7*I;

(62) level “1”.fwdarw.(IDAC/2)_PMOS=−I−I−I−I−I−I+I=−5*I and (IDAC/2)_NMOS=−I−I−I−I−I−I+I=−5*I, and therefore IDAC=(−10*I)/2=−5*I; and, similarly:

(63) level “2”.fwdarw.IDAC=(−6*I)/2=−3*I,

(64) level “3”.fwdarw.IDAC=(−2*I)/2=−1*I,

(65) level “4”.fwdarw.IDAC=(+2*I)/2=+1*I,

(66) level “5”.fwdarw.IDAC=(+6*I)/2=+3*I,

(67) level “6”.fwdarw.IDAC=(+10*I)/2=+5*I,

(68) level “7”.fwdarw.IDAC=(+14*I)/2=+7*I.

(69) As discussed, a same type of DAC operation could be achieved by considering branches with current values weighed in a binary mode and driven via a binary code.

(70) The following discussion refers to arrangements where the transistors 20j11, 20j12 are P-MOS and the transistors 20j21, 20j22 are N-MOS receiving at the control electrodes (gates) logic signals produced by (combinational) logic circuitry CL shown at the top of the figure. This logic circuitry is driven by a return-to-zero signal RTZ produced by associated circuitry not visible in the figures for simplicity. The signal is an on-off (two-state) signal with a period Ts comprising an “on” time or state t.sub.on and an “off” time or state t.sub.off, thus with a duty cycle given by t.sub.on/(t.sub.on+t.sub.off).

(71) FIGS. 3 and 4 provide just possible examples of how operation of the cells 201, . . . , 20j, . . . , 20N as discussed previously can be obtained as a function of RTZ (possibly including the binary complementary or negated version thereof, namely RTZ) and other logical signals generated by logic circuitry CL as exemplified at the top of the figures.

(72) Those of skill in the art (this will similarly apply to FIGS. 8 to 14 which are discussed in the following in connection with various embodiments) may devise a variety of alternative solutions where the same operation of the cells 201, . . . , 20j, . . . , 20N can be obtained as a function of RTZ using different circuitry, for instance if different types of switches (are used for 20j11, 20j12, 20j21, 20j22 (N-MOS in the place of P-MOS, just to make an example).

(73) In the (purely exemplary) case illustrated in FIG. 3:

(74) when the signal RTZ=0 (and therefore RTZ=1) the gates of the bias PMOS (20j11, 20j12, for instance) are connected to a supply voltage VDD and the gates of the bias NMOS (20j21, 20j22, for instance) are connected to GND: in other words, the current mirrors implemented thereby are off, so that the (differential) output current I.sub.DAC at the lines 120, 220 equals zero;

(75) when the RTZ=1 the I.sub.DAC current depends on a M bit digital word called SDout [M−1: 0], which—in a case as exemplified—can be assumed to be simply the digital output from the M bit converter 28, designated B.sub.1, B.sub.2, . . . , B.sub.M).

(76) A (M-bit) logic circuit as exemplified at CL comprises:

(77) a NAND gate CL1 receiving as inputs B.sub.1, B.sub.2, . . . , B.sub.M and RTZ and having cascaded therewith an inverter CL2;

(78) a NAND gate CL3 receiving as inputs B.sub.1, B.sub.2, . . . , B.sub.M (at a logically inverted input) and RTZ and having cascaded therewith an inverter CL4;

(79) an inverter CL5 producing RTZ from RTZ.

(80) In the exemplary case of FIG. 3:

(81) if RTZ=1 and B.sub.1, B.sub.2, . . . , B.sub.M=0, then BP.sub.1, BP.sub.2, . . . , BP.sub.M=0 (BP.sub.1, BP.sub.2, . . . , BP.sub.M=1) and BN.sub.1, BN.sub.2, . . . , BN.sub.M=0 (BN.sub.1, BN.sub.2, . . . , BN.sub.M=1) and therefore the current output from the DAC is equal to I.sub.DAC=(−1−1 . . . −1)*I.sub.LSB=−M*I.sub.LSB.

(82) The value I.sub.LSB is an “elementary” current contribution related to the least significant bit (LSB) in the M-bit word from the quantizer 28. This is generated by a current generator (of any known type) providing a current of intensity I.sub.LSB/2 between the sources 20A, 20B implemented (by way of example) as diode-connected “upper” (20A) and “lower” (20B) transistor pairs having the current flow paths therethrough (source-drain, in the exemplified case of field-effect transistors such as MOSFET transistors) traversed by a current set by the generator of I.sub.LSB/2. These control electrodes (gates, in the exemplified case of field-effect transistors such as MOSFET transistors) are configured to be coupled in a current-mirror arrangement (via corresponding switch pairs 200A, 200B controlled by RTZ) to “head” and “tail” transistors pairs included in the various cells 201, . . . , 20j, . . . , 20M upstream and downstream of the transistor pairs 20j11, 20j12, 20j21, 20j22 (j=1, . . . , M)

(83) If RTZ=1 and B.sub.1=1, B.sub.2, . . . , B.sub.M=0, then BP.sub.1=1, BP.sub.2, . . . , BP.sub.M=0 (BP.sub.1=0, BP.sub.2, . . . , BP.sub.M=1) and BN.sub.1=1, BN.sub.2, . . . , BN.sub.M=0 (BN.sub.1=0; BN.sub.2, . . . , BN.sub.M=1) and therefore the current flow output from the DAC 20 is equal to I.sub.DAC=(+1−1 . . . −1)*I.sub.LSB=(−M+2)*I.sub.LSB.

(84) And so on, if RTZ=1 and B.sub.1, B.sub.2, . . . , B.sub.M=1 then BP.sub.1, BP.sub.2, . . . , BP.sub.M=1 (BP.sub.1, BP.sub.2, . . . , BP.sub.M=0) and BN.sub.1, BN.sub.2, . . . , BN.sub.M=1 (BN.sub.1, BN.sub.2, . . . , BN.sub.M=0) and therefore the current output from the DAC is equal to I.sub.DAC=(+1+1 . . . +1)*I.sub.LSB=M*I.sub.LSB.

(85) A noted disadvantage of the architecture of FIG. 3 lies in that the switching on and off of the bias currents supplied to the differential pairs is characterized by the associated on and off switching time constants (this is exemplified in FIG. 3A) which, moreover, will also depend process, temperature and voltage variations.

(86) This results in a deviation of the output signal from the “ideal” desired signal and a degradation in SNR.

(87) Such a disadvantage, which becomes more evident as the sampling frequency f.sub.s (ideally represented by the switch 26 upstream of the quantizer 28) increases, can be addressed by resorting to a solution as exemplified in FIG. 4.

(88) In FIG. 4, parts or elements like parts or element as already discussed in connection with the previous figures are indicated by like reference symbols, so that a detailed description will not be repeated here for brevity.

(89) Comparison with FIG. 3 facilitates understanding that, in an arrangement as exemplified in FIG. 4, the switch arrangement 200A, 200B controlled by RTZ (as exemplified in FIG. 3) is no longer present and the M cells 201, . . . , 20j, . . . , 20M are always kept on by additional switches (NMOS and PMOS transistors 2001C, . . . , 200jC, . . . , 200MC, for instance) controlled by the signals RTZ and RTZ which direct the current flow towards GND or VDD when RTZ=0 (and therefore RTZ=1).

(90) The disadvantage discussed previously is therefore overcome at the cost of an increase in current consumption: in fact during the phase/state with RTZ=0 the current flows (in a useless manner) towards GND and towards VDD.

(91) In fact when the signal RTZ=0, RTZ=1, with BP.sub.1, BP.sub.2, . . . , BP.sub.M=1, and BP.sub.1, BP.sub.2, . . . , BP.sub.M=1, BN.sub.1, BN.sub.2, . . . , BN.sub.M=0, and BN.sub.1, BN.sub.2, . . . , BN.sub.M=0. In other words, the unit currents of the DAC 20 flow towards GND through the PMOS driven via RTZ and towards VDD through the NMOS driven via RTZ.

(92) When RTZ=0, I.sub.DAC=0 and when RTZ=1 the I.sub.DAC current depends on the M-bit digital word called SDout [M−1: 0] (here again that digital word can be assumed to coincide with the M-bit digital output of the quantizer 28.

(93) In fact, if RTZ=1 and B.sub.1, B.sub.2, . . . , B.sub.M=0 one has BP.sub.1, BP.sub.2, . . . , BP.sub.M=0 (BP.sub.1, BP.sub.2, . . . , BP.sub.M=1) and BN.sub.1, BN.sub.2, . . . , BN.sub.M=0 (BN.sub.1, BN.sub.2, . . . , BN.sub.M=1) and therefore the current output from the DAC 20 is equal to I.sub.DAC=(−1−1 . . . −1)*I.sub.LSB=−M*I.sub.LSB.

(94) If RTZ=1 and B.sub.1=1, B.sub.2, . . . , B.sub.M=0 one has BP.sub.1=1, BP.sub.2, . . . , BP.sub.M=0 (BP.sub.1=0, BP.sub.2, . . . , BP.sub.M=1) and BN.sub.1=1, BN.sub.2, . . . , BN.sub.M=0 (BN.sub.1=0, BN.sub.2, . . . , BN.sub.M=1) and therefore the current flow output from the DAC 20 is equal to I.sub.DAC=(+1−1 . . . −1)*I.sub.LSB=(−M+2)*I.sub.LSB.

(95) And so on, if RTZ=1 and B.sub.1, B.sub.2, . . . , B.sub.M=1, then BP.sub.1, BP.sub.2, . . . , BP.sub.M=1 (BP.sub.1, BP.sub.2, . . . , BP.sub.M=0) and BN.sub.1, BN.sub.2, . . . , BN.sub.M=1 (BN.sub.1, BN.sub.2, . . . , BN.sub.M=0) and therefore the current output from the DAC 20 is equal to I.sub.DAC=(+1+1 . . . +1)*I.sub.LSB=M*I.sub.LSB.

(96) It will be appreciated that, while primarily referred to a current-based implementation of the DAC 20 as exemplified in FIG. 1, the discussion related to FIGS. 3 and 4 applies mutatis-mutandis (e.g., the voltage-to-current translator resistors at the output of the DAC 20) to a voltage-based implementation of the DAC 20 as exemplified in FIG. 2.

(97) It will be similarly appreciated that the previous discussion related to FIGS. 1 to 4 (including FIG. 3A) essentially corresponds to conventional solutions, which makes it unnecessary to provide a more in-depth analysis and description.

(98) Such a previous discussion is primarily intended to facilitate the understanding of embodiments as discussed in the following in connection with FIGS. 5 to 14.

(99) For that reason, in FIGS. 5 to 14, parts or elements like parts or element already discussed in connection with FIGS. 1 to 4 are indicated by like reference symbols and—unless otherwise indicated in the following—the detailed description of these parts and elements provided in connection with FIGS. 1 to 4 will apply to like parts and elements FIGS. 5 to 14 and will not be repeated for brevity.

(100) One or more embodiments as discussed in the following in connection with FIGS. 5 to 14 are based on the recognition that in solutions as exemplified in FIG. 4—during the phase/state with RTZ=0—the current flows towards GND and towards VDD in a useless manner, thus unnecessarily increasing current consumption.

(101) Conversely, in one or more embodiments as discussed in the following, such a current can be used to provide offset correction, thus saving on the current used for offset correction.

(102) In addition to providing savings in terms of (average) current dissipated, one or more embodiments will also facilitate saving semiconductor area: in one or more embodiments no specific, additional offset correction circuitry is needed insofar as offset correction can be performed at the feedback loop itself (DAC 20).

(103) Direct comparison of FIGS. 1 and 2 with FIGS. 5 and 6 shows that one or more embodiments again relate to current-based (FIG. 5) and voltage-based (FIG. 6) continuous-time converter circuits 10 comprising an analog-to-digital signal conversion path (amplifier/integrator 22, rest of loop filter 24, sampling switch 26 operating at a frequency f.sub.s, M-level quantizer 28) from an input port 14 configured to receive an analog input signal I.sub.SD_IN having an offset I.sub.OFF to be compensated) to an output port 16 configured to deliver a digital output signal quantized over M levels resulting from conversion to digital of the analog input signal.

(104) A digital decimation filter 30 can be optionally coupled to the output port 16.

(105) The converter circuits 10 exemplified in FIGS. 5 and 6 also comprise a digital-to-analog feedback path 18 from the output port 16 to the input port 14, with such a feedback path comprising a digital-to-analog converter 20 configured to sense and convert to analog the digital output signal and to apply an analog feedback signal at the input port 14.

(106) The converter circuits 10 exemplified in FIGS. 5 and 6 may again advantageously adopt a differential configuration where the input port 14 to the analog-to-digital conversion path 12 again comprises a differential input 14 with a first input node 141 and a second input node 142 configured to receive the analog input signal input signal I.sub.SD_IN applied therebetween.

(107) In the converter circuits 10 exemplified in FIGS. 5 and 6, the digital-to-analog converter 20 in the digital-to-analog feedback path 18 comprises a first output line 120 and a second output line 220 configured to apply an analog (current) feedback signal at the first input node 141 and the second input node 142 of the input port 14 of the analog-to-digital signal conversion path.

(108) The similarity of definitions and reference symbols in FIGS. 1 and 2 and FIGS. 5 and 6 evidences that, unless otherwise indicated in the following, the description of certain details of implementation provided previously in connection with FIGS. 1 and 2 applies to FIGS. 5 and 6: a description of these like details will not be repeated here for brevity.

(109) This also applies (unless otherwise indicated in the following) to the possibility for the digital-to-analog converter 20 in the digital-to-analog feedback path 18 to comprise (see FIGS. 8 and 9 for a current-based implementation and a voltage-based implementation, respectively) a plurality of M electronic switch cells, 201, . . . , 20j, . . . , 20M, where M again equals the number of levels of the quantizer 28 and the number of bits in B.sub.1, B.sub.2, . . . , B.sub.M, for instance.

(110) In the converter circuits 10 exemplified in FIGS. 5 to 9, the cells 201, . . . , 20j, . . . , 20M are switchable to a conductive state, during which these cells electrically couple the first output line 110 and the second output line 120 to a first signal source 20A and to a second signal source 20B, respectively.

(111) In the converter circuits 10 exemplified in FIGS. 5 to 9, operation of the cells 201, . . . , 20j, . . . , 20M can be controlled by logic control circuitry 40 as exemplified in FIG. 7.

(112) That is, in the converter circuits 10 exemplified in FIGS. 5 to 9 the digital-to-analog converter 20 may essentially comprise M cells as exemplified in FIG. 8 (current-based implementation) or FIG. 9 (voltage-based implementation) plus logic control circuitry 40 as exemplified in FIG. 7.

(113) In one or more embodiments as exemplified in FIGS. 8 and 9, the electronic switch cells 201, . . . , 20j, . . . , 20M may again comprise electronic switches such as transistors.

(114) MOSFET transistors (both P-type and N-type) are again exemplary of such electronic switches which can be made selectively conductive or non-conductive with the current flow path therethrough (source-drain in the case of field-effect transistors such as MOSFETs) made current-pervious and current-impervious as a function of a (logic) signal applied to a control electrode (gate, in the case of field-effect transistors such as MOSFETs).

(115) Here again, the logic control signals applied can take opposite values depending on whether a P-type or a N-type transistor is used to implement a certain electronic switch at a certain location.

(116) In the—purely exemplary—case considered herein, the cells 201 to 20M again comprise (reference is made to a generic cell 20j with j=1, . . . , M):

(117) a first electronic switch pair 20j11, 20j12 comprising a first and a second electronic switch (P-MOS and N-MOS transistors, for instance) which, during their conductive state, couple the first output line 120 to the first signal source 20A and the second signal source 20B, respectively,

(118) a second electronic switch pair 20j21, 20j22 comprising a (further) first and a (further) second electronic switch (P-MOS and N-MOS, transistors for instance) which, during their conductive state, couple the second output line 220 to the first signal source 20A and the second signal source 20B respectively.

(119) Control nodes (gates in the case of field effect transistors such as MOSFET transistors) are provided configured to selectively provide a conductive state of these switches (transistors) 20j11, 20j12, 20j21, 20j22 as a function of the logical state of a respective digital signal applied thereto.

(120) Once more, the following discussion refers to arrangements where the transistors 20j11, 20j12 are P-MOS and the transistors 20j21, 20j22 are N-MOS receiving at the control electrodes (gates) logic signals produced by the logic circuitry 40 of FIG. 7—as a function—a return-to-zero signal RTZ produced as discussed in the following. The signal RTZ is an on-off (two-state) signal with a period Ts comprising an “on” time or state (hereinafter referred to a T.sub.GAIN for reason which will become clearer in the following) or and an “off” time or state T.sub.OFF, thus with a duty cycle given by t.sub.GAIN/(t.sub.GAIN+t.sub.OFF).

(121) Like FIGS. 3 and 4 discussed previously, FIGS. 8 and 9 provide just possible examples of how operation of the cells 201, . . . , 20j, . . . , 20N as discussed can be obtained as a function of RTZ (possibly including the binary complementary or negated version thereof, namely RTZ) and other logical signals generated by the logic circuitry 40 as exemplified in FIG. 7.

(122) Based on the disclosure provided herein, those of skill in the art may devise a variety of alternative solutions where the same operation of the cells 201, . . . , 20j, . . . , 20N can be obtained as a function of RTZ using different circuitry, for instance if different types of switches are used for 20j11, 20j12, 20j21, 20j22 (N-MOS in the place of P-MOS, just to make an example).

(123) FIGS. 5 and 6 are exemplary (by direct comparison with FIGS. 1 and 2) of embodiments where offset correction is effected in the DAC 30, without the provision of additional circuitry such as OC in FIGS. 1 and 2 with the drawbacks associated therewith as discussed previously.

(124) In one or more embodiments as exemplified in FIGS. 5 to 9, a sensing signal I.sub.SD_IN (to be amplified and converted to digital in the converter 10) can be obtained from a sensor S either directly as a current signal I.sub.SENSE (FIG. 5) or as a result of conversion of a voltage signal V.sub.SENSE via transduction resistors (visible and not explicitly labeled for simplicity in FIG. 6).

(125) As in the case of I.sub.OFF discussed previously in connection with FIGS. 1 and 2, in one or more embodiments as exemplified in FIGS. 5 to 9, an offset component expected to be present in the sensing can be calculated during the calibration phase and subtracted (removed) from I.sub.SD_IN the by DAC 20.

(126) The current integrated by the converter integrator 22 (to be amplified and converted into digital) will thus include only the “useful” signal component (indicative of the physical quantity sensed by the sensor S).

(127) In one or more embodiments as exemplified in FIGS. 5 to 9, correction of the input signal for offset can be effected using the circuitry of the DAC 20. This may be beneficial both in terms of current consumption of the converter 10 as a whole and in terms of semiconductor area occupation (the specific offset correction circuitry OC as illustrated in FIGS. 1 and 2 can be avoided).

(128) As in the case of FIGS. 1 and 2, FIGS. 5 and 6 refer to “current-based” and “voltage-based” implementations of the DAC 20, respectively. The discussion of FIG. 5 (and FIG. 8) can thus be held to extend to FIG. 6 (and FIG. 9), taking into account the possible presence (in the place of current sources as illustrated in FIGS. 5 and 8) of voltage current sources as illustrated in FIGS. 6 and 9 with associated voltage-to-current transduction resistors.

(129) Embodiments as exemplified in FIG. 5 (and FIG. 8) and embodiments as exemplified in FIG. 6 (and FIG. 9) may thus share a same logic control circuitry 40 as exemplified in FIG. 7, which is configured to receive as an input:

(130) a digital “thermometric” word SDout [M−1: 0], which for simplicity can again be assumed to coincide with the digital output from the M-bit converter 28 including bits B.sub.1, B.sub.2, . . . , B.sub.M,

(131) a digital offset correction word OFF [M−1: 0], which is (another) M-bit digital word used to control the value of the I.sub.OFF current to be compensated, that is, the offset correction to be achieved,

(132) t.sub.SET [N−1: 0] and t.sub.RST [N−1: 0], that is, two N-bit words used to define over time the rising edges and the falling edges, respectively (and thus the duty cycle) of the signal RTZ and the negated version thereof namely RTZ.

(133) The circuitry 40 is configured to be clocked by a clock signal CLK with a period T.sub.CLK, generated—like the other signals considered in the foregoing—in any manner known to those of skill in the art.

(134) As exemplified in FIG. 7, the clock signal CLK drives a N-bit counter 41 that generates a count signal which is compared at two comparators 421, 422 (having thresholds set as a function of t.sub.SET [N−1: 0] and t.sub.RST [N−1: 0]) to define the rising/falling edges of RTZ (and, complementarily, RTZ) as discussed previously.

(135) For example, assuming the counter 41 is at N=8 bit counter counting continuously (cyclically) from 0 to 255 (or 2.sup.8−1) with an increase on each edge of the clock period T.sub.CLK of the signal CLK, a sampling period Ts can be selected at 256*T.sub.CLK (for instance).

(136) If (still by way of non-limiting example) t.sub.SET=2 and t.sub.RST=202 are selected as the counts producing rising and falling edges, respectively, then the RTZ signal will go “high” on the second count and “low” on the 202-th count.

(137) Therefore, the signal RTZ will exhibit an “on” state or time over T.sub.GAIN=(202−2)*T.sub.CLK=200*T.sub.CLK and an “off” state or time over T.sub.OFF=56*T.sub.CLK.

(138) That is, the counter 41 in combination with the two N-bit comparators 421, 422 (with thresholds set via the words t.sub.SET [N−1: 0] and t.sub.RST [N−1: 0]) and a Set-Reset (SR) flip-flop 43 may facilitate controlling the duty-cycle of the RTZ signal (and consequently of the signal RTZ which is its negated/binary complementary), that is the duration of the T.sub.GAIN and T.sub.OFF states (time intervals) of the two-level signal RTZ.

(139) As exemplified in FIG. 7:

(140) the Q output of the flip-flop 43 provides the signal RTZ to an AND gate 441 which receives as another input the M-bit word B.sub.1, B.sub.2, . . . , B.sub.M,

(141) the (neg)Q output of the flip-flop 43 provides the signal RTZ to an AND gate 442 which receives as another input the M-bit offset correction word OFF [M−1: 0].

(142) The outputs from the AND gates 441, 442 in turn provide the inputs to an OR gate 45 which produces signals BPN.sub.1, BPN.sub.2, . . . , BPN.sub.M. These signals (together with their negated or logical complementary replicas produced by an inverter 46) are used to drive the DAC cell network of FIG. 8 (current-based implementation) and FIG. 9 (voltage-based implementation).

(143) In the DAC network of FIG. 8, when the signal RTZ=0 (that is, when RTZ=1), namely in the T.sub.OFF time or state of RTZ, and OFF[M−1: 0]=0, . . . 0, then BPN.sub.1, BPN.sub.2, . . . , BPN.sub.M=0, 0, . . . 0 and BPN.sub.1, BPN.sub.2, . . . , BPN.sub.M=1, 1, . . . 1, so that the current from the DAC 20 is equal to I.sub.OFF=(−1−1 . . . −1)*I.sub.LSB=−M*I.sub.LSB.

(144) When RTZ=0 and OFF [M−1: 0]=1, 0, . . . , 0, then BPN.sub.1=1, BPN.sub.2, . . . , BPN.sub.M=0 (BPN.sub.1=0 and BPN.sub.2, . . . , BPN.sub.M=1) and therefore the current output from the DAC 20 is equal to I.sub.OFF=(+1−1 . . . −1)*I.sub.LSB=(−M+2)*I.sub.LSB.

(145) Finally, when RTZ=0 and OFF [M−1: 0]=1, 1, . . . , 1, then BPN.sub.1, BPN.sub.2, . . . , BPN.sub.M=1, 1, . . . , 1 (BPN.sub.1, BPN.sub.2, . . . , BPN.sub.M=0, 0, . . . , 0) and therefore the current from the DAC 20 is equal to I.sub.OFF=(+1+1 . . . +1)*I.sub.LSB=M*I.sub.LSB.

(146) The current I.sub.OFF is integrated (at 22) over a portion T.sub.OFF of the sampling period Ts and the equivalent mean value I.sub.OFF_avg of the offset correction current I.sub.OFF can be expressed as:

(147) $\begin{array}{cc}{I}_{\mathrm{OFF\_avg}}=\frac{T_{OFF}}{T_s}.Math.I_{LSB}.Math.\left(-M+2.Math.\mathrm{OFF}\right)& \left(1\right)\end{array}$

(148) where, in the formula above, OFF denotes a “thermometric” value of OFF [M−1: 0] converted to decimal, that is a number from 0 to M. The average current value set thus depends (only) on the M-bit word OFF [M−1: 0] (trimming word) which, once determined in calibration procedure can be stored in a non-volatile memory (not visible for simplicity).

(149) A DAC 20 as exemplified herein can thus subtract from the current I.sub.SENSE coming from the sensor S in FIG. 5 a dc current value according to the formula (1). This can be regarded as a design equation that indicates the current correction feasible as a function of the trimming word OFF [M−1: 0].

(150) It will be appreciated that in the case of a (conventional) DAC 20 as illustrated in FIG. 4 the average current value given by equation (1) would be dissipated to no advantage.

(151) Conversely, in the case of a DAC 20 according to embodiments as exemplified in FIG. 7 and FIG. 8, that current can be used for offset correction of the input signal, thus making it possible to avoid using an offset correction network OC (see FIG. 1, for instance), which leads to saving in terms of occupation and current consumption.

(152) In the DAC network of FIG. 8, when the signal RTZ=1 (that is, when RTZ=0), namely in the T.sub.GAIN time or state of RTZ, and SD.sub.OUT [M−1: 0]=0, . . . 0, then BPN.sub.1, BPN.sub.2, . . . , BPN.sub.M=0, 0, . . . 0 and BPN.sub.1, BPN.sub.2, . . . , BPN.sub.M=1, 1, . . . 1, so that the current from the DAC 20 is equal to I.sub.DAC=(−1−1 . . . −1)*I.sub.LSB=−M*I.sub.LSB.

(153) When RTZ=1 and SD.sub.OUT [M−1: 0]=1, 0, . . . , 0, then BPN.sub.1=1, BPN.sub.2, . . . , BPN.sub.M=0 (BPN.sub.1=0 and BPN.sub.2, . . . , BPN.sub.M=1) and therefore the current output from the DAC 20 is equal to I.sub.DAC=(+1−1 . . . −1)*I.sub.LSB=(−M+2)*I.sub.LSB.

(154) Finally, when RTZ=1 and SD.sub.OUT [M−1: 0]=1, 1, . . . , 1, then BPN.sub.1, BPN.sub.2, . . . , BPN.sub.M=1, 1, . . . , 1 (BPN.sub.1, BPN.sub.2, . . . , BPN.sub.M=0, 0, . . . , 0) and therefore the current from the DAC 20 is equal to I.sub.DAC=(+1+1 . . . +1)*I.sub.LSB=M*I.sub.LSB.

(155) If one considers that the current I.sub.DAC current is integrated (at 22) over a portion T.sub.GAIN(or T.sub.GAIN) of the sampling period Ts, equivalent mean value I.sub.DAC_avg of the feedback current I.sub.DAC can be expressed as:

(156) $\begin{array}{cc}{I}_{\mathrm{DAC\_avg}}=\frac{T_{\mathrm{GAIN}}}{T_s}.Math.I_{LSB}.Math.\left(-M+2.Math.{\mathrm{SD}}_{\mathrm{out}}\right)& \left(2\right)\end{array}$

(157) where, in the formula above, SD.sub.out denotes a “thermometric” value of SD.sub.OUT [M−1: 0] converted to decimal, that is a number from 0 to M.

(158) In one or more embodiments, the average value of the feedback current obtained as a function of the M-bit word SD.sub.OUT [M−1: 0] is the same as that which can be obtained with a “conventional” DAC 20 as illustrated in FIG. 4.

(159) In addition, in one or more embodiments, the DAC 20 also provides the offset correction current I.sub.OFF as expressed in equation (1) above, which can be used to achieve the offset correction.

(160) FIG. 9 presents a possible voltage-based implementation of a DAC as exemplified of FIG. 8 in a current-based implementation.

(161) In FIG. 8, the signal sources 20A, 20B are implemented as rails of “head” and “tail” current mirror pairs that mirror the current I.sub.LSB/2 onto the bias cells 201, . . . , 20j, . . . , 20M.

(162) Conversely, in FIG. 9, the signal sources 20A, 20B are implemented as opposed “head” and “tail” voltage lines (at voltages V.sub.LSB/2 and −V.sub.LSB/2, respectively) to which the bias cells 201, . . . , 20j, . . . , 20M are coupled via voltage-to-current translator resistors (again shown but not expressly labeled in FIG. 9 for simplicity) providing conversion of V.sub.LSB into I.sub.LSB.

(163) The previous discussion of FIG. 7 in connection with FIG. 8, thus essentially applies FIG. 7 in connection with FIG. 9, with the equivalent average value I.sub.OFF_avg of the offset correction current expressed as:

(164) $\begin{array}{cc}{I}_{\mathrm{OFF\_avg}}=\frac{T_{OFF}}{T_s}.Math.\frac{V_{LSB}}{R}.Math.\left(-M+2.Math.\mathrm{OFF}\right)& \left(3\right)\end{array}$

(165) and the equivalent average value I.sub.DAC_avg of the offset correction current expressed as

(166) $\begin{array}{cc}{I}_{\mathrm{DAC\_avg}}=\frac{T_{\mathrm{GAIN}}}{T_s}.Math.\frac{V_{LSB}}{R}.Math.\left(-M+2.Math.{\mathrm{SD}}_{\mathrm{out}}\right)& \left(4\right)\end{array}$

(167) Whatever the specific implementation details, controlling the durations of the T.sub.GAIN and T.sub.OFF states (time intervals) of the two-level signal RTZ ((via the thresholds set via the words t.sub.SET [N−1: 0] and t.sub.RST [N−1: 0], for instance) may facilitate controlling the duty-cycle of the signals RTZ and RTZ, thus adjusting the (relative) “weight” that the components related to the M-bit words SDout [M−1: 0] and OFF [M−1: 0] have on the feedback signal applied by the DAC 20 at the input port 14 of the analog-to-digital conversion path 12.

(168) For instance, in one or more embodiments a value for the duty cycle of the signal RTZ can be set to achieve a desired performance level in terms of SNR as discussed previously. The duration of the time interval T.sub.OFF can then be used to implement a desired offset correction.

(169) FIG. 10 illustrates an implementation of the DAC control circuitry 40 which includes a block 47 configured to implement (in a manner known to those of skill in the art) a dynamic element matching (DEM) technique.

(170) Parts, elements or signals like parts, elements or signals already discussed in connection with FIG. 7 are indicated in FIG. 10 with like reference symbols and a corresponding detailed description will not be repeated here for brevity.

(171) As exemplified in FIG. 10, the block 47 is arranged intermediate the OR gate 45 and the logical inverter 46 to effect a cyclic rotation (or any other similar alternation) of the control words which are applied as command signals for the cells 201, . . . , 20j, . . . , 20M of the DAC 20 as discussed previously.

(172) The DEM technique is conventionally used in various contexts in order to reduce errors due to mismatch and to reduce the contribution of low frequency noise.

(173) For example, if a bias current ratio of 1:m is generated, then using (m+1) bias branches, each of these (m+1) branches can be used cyclically as a reference branch to generate the current m times bigger. This will result in (m+1) possible combinations, or a cyclic rotation of (m+1) combinations, each of which will have a matching error.

(174) In cases where a decimation filter such as 30 is present downstream of a converter (see FIG. 5 and FIG. 6) which produces output values averaged using multiples of (m+1) converter output data, the effect due to the matching error of the current branches will be averaged for these values.

(175) FIG. 10 is thus exemplary of the possibility of applying DEM processing to one or more embodiments, either current-based or voltage-based. Such DEM processing will have effect on the output signal from the DAC signal both in respect of the feedback signal, which is a function of the converter output from the quantizer 28 (namely a function of SD.sub.OUT [M−1: 0]) and in respect of the offset correction signal (namely a function of OFF [M−1: 0]),

(176) FIGS. 11 and 12 illustrate implementations (current-based in FIG. 11 and voltage-based in FIG. 12) of the DAC control circuitry 40 and the cells 201, . . . , 20j, . . . , 20M aiming at reducing the minimum offset correction step.

(177) Here again, parts, elements or signals like parts, elements or signals already discussed in connection with FIG. 7 (and FIG. 10) are indicated with like reference symbols and a corresponding detailed description will not be repeated here for brevity.

(178) Also, while not illustrated for simplicity, the features discussed in connection with FIGS. 11 and 12 lend themselves to be possibly used in combination with DEM processing discussed in connection with FIG. 10.

(179) Briefly, the implementations exemplified in FIGS. 11 and 12 are based on the recognition that—as shown by the diagrams of FIG. 7 and FIG. 8 and equation (1)—a unitary increase in the “OFF” value produces a variation in the average value of the offset correction current equal to:

(180) $\begin{array}{cc}{I}_{\mathrm{OFF\_avg}\mathrm{\_STEP}}=\frac{T_{OFF}}{T_s}.Math.I_{LSB}.Math.2& \left(5\right)\end{array}$

(181) In FIG. 11 the cells 201, . . . , 20j, . . . , 20M of the DAC 20 have the same general topology exemplified in FIG. 8, with the difference that one of the cells (the cell 201, for instance) is “split” into H branches (sub-cells) each of which produces a current which is 1/H of (that is H times smaller than) the unitary current contribution from the respective cell (the cell 201, for instance) as a whole.

(182) A corresponding DAC control circuitry 40 as proposed in FIG. 11 is essentially the same as exemplified in FIG. 7 (or FIG. 1) with the addition of a fine offset logic block 48 configured to “refine” the logic underlying generation of the control signals.

(183) In embodiments as exemplified in FIG. 7 (and FIGS. 8 and 9) the logic 40 can be based on the scheme reported in Table 1 which follows. This table summarizes possible values of the command bits when RTZ=0 (i.e., during the T.sub.OFF period during which offset correction is performed):

(184) TABLE-US-00001 TABLE 1 generation of logic signals in FIG. 7 M I.sub.LSB T.sub.OFF/Ts 4 1.00E−6 0.5 BPN.sub.4 = BPN.sub.3 = BPN.sub.2 = BPN.sub.1 = OFF[3] OFF[2] OFF[1] OFF[0] I.sub.OFF_avg I.sub.OFF_avg_STEP 0 0 0 0 −2.00E−6 0 0 0 1 −1.00E−6 1.00E−6 0 0 1 1 0 1.00E−6 0 1 1 1   1.00E−6 1.00E−6 1 1 1 1   2.00E−6 1.00E−6

(185) By way of contrast, in embodiments as exemplified in Figure ii the logic 40 can be based on following Table 2 may apply.

(186) TABLE-US-00002 TABLE 2 generation of logic signals in FIG. 11 M H I.sub.LSB T.sub.OFF/Ts 4 3 1.00E−6 0.5 BPN.sub.4 = OFF BPN.sub.3 = OFF BPN.sub.2 = BPN.sub.1_3 = BPN.sub.1_2 = BPN.sub.1_1 = [3] [2] OFF[1] OFF[2] OFF[1] OFF [0] I.sub.OFF_avg I.sub.OFF_avg 0 0 0 0 0 0 −2.00E-6 0 0 0 0 0 1 −1.67E-6 −333.33E−9 0 0 0 0 1 1 −1.33E−6   333.33E−9 0 0 0 1 1 1 −1.00E−6   333.33E−9 0 0 1 0 0 1 −666.67E−9   333.33E−9 0 0 1 0 1 0 −333.33E−9   333.33E−9 0 0 1 1 1 1 0   333.33E−9 0 1 1 0 0 1   333.33E−9   333.33E−9 0 1 1 0 1 1   666.67E−9   333.33E−9 0 1 1 1 1 1   1.00E−6   333.33E−9 1 1 1 0 0 1   1.33E−6   333.33E−9 1 1 1 0 1 1   1.67E−6   333.33E−9 1 1 1 1 1 1   2.00E−6   333.33E−9

(187) The table above shows that embodiments as exemplified in FIG. 11 may implement a H times “finer” correction step equal to:

(188) $\begin{array}{cc}{I}_{\mathrm{OFF\_avg}\mathrm{\_STEP}}=\frac{T_{OFF}}{T_s}.Math.I_{LSB}.Math.2.Math.\frac{1}{H}& \left(6\right)\end{array}$

(189) During the phase with RTZ=1 (that is during the T.sub.GAIN period where the DAC 20 is driven as a function of the signal SDout [M−1: 0] (in the place of the “trimming” word OFF [M−1: 0] for offset compensation) the H sub-cells 2011, . . . , 201H are all driven by the B.sub.1 bit (that is BPN.sub.1_1, BPN.sub.1_2, . . . , BPN.sub.1_H=SDout[0]=B.sub.1).

(190) In other words, during the RTZ=1 phase, the H sub-cells 2011, . . . , 201H are driven “constructively” together to recompose the unit current element expected to be provide by the cell 201.

(191) In that way, operation in the phase RTZ=1 is maintained unchanged, without impacting and without modifying the feedback function of the converter.

(192) The same remarks made in the foregoing in respect of the “current-based” implementation of FIG. 11 also apply to the “voltage-based” implementation of FIG. 12, where the cells 201, . . . , 20j, . . . , 20M (and primarily the cell 201 exemplary of a cell “split” into H sub-cells 2011, . . . , 201H) have the structure previously discussed in connection with FIG. 9.

(193) The exemplary “voltage-based” implementation of FIG. 12, may thus provide a H times “finer” correction step equal to:

(194) $\begin{array}{cc}{I}_{\mathrm{OFF\_avg}\mathrm{\_STEP}}=\frac{T_{OFF}}{T_s}.Math.\frac{V_{LSB}}{R}.Math.2.Math.\frac{1}{H}& \left(7\right)\end{array}$

(195) Finally, FIGS. 13 and 14 illustrate implementations (current-based in FIG. 13 and voltage-based in FIG. 14) of the DAC control circuitry 40 and the cells 201, . . . , 20j, . . . , 20M aiming at increasing the full-scale of offset correction.

(196) Once more, parts, elements or signals like parts, elements or signals already discussed in connection with FIGS. 7 thru 12 are indicated with like reference symbols and a corresponding detailed description will not be repeated here for brevity.

(197) Again, while not illustrated for simplicity, the features discussed in connection with FIGS. 13 and 14 lend themselves to be possibly used in combination with the DEM features discussed in connection with FIG. 10, and in FIGS. 11 (current-based implementation of FIG. 13) and 12 (voltage-based implementation of FIG. 14)).

(198) Briefly, the implementations exemplified in FIGS. 13 and 14 are based on the recognition that—as shown by the diagrams of FIG. 7 and FIG. 8 and equation (1)—varying “OFF” from 0 to M leads to a full-scale variation of the average value of the offset correction current is equal to:

(199) $\begin{array}{cc}{I}_{\mathrm{OFF\_avg}\mathrm{\_Fullscale}}=\pm \frac{T_{\mathrm{OFF}}}{T_s}.Math.I_{\mathrm{LSB}}.Math.M& \left(8\right)\end{array}$

(200) In FIG. 13 the cells 201, . . . , 20j, . . . , 20M of the DAC 20 have the same general topology exemplified in FIG. 8, with however L additional cells 2001, 2002, . . . , 200L each providing a unitary current contribution similar to the contribution of 201, 202, . . . , 200M are added.

(201) These L further cells can be configured and driven according to the technique already discussed in connection with FIG. 4 but using RTZ instead of RTZ.

(202) Therefore, during the phase with RTZ=1 (T.sub.GAIN interval) the additional cells 2001, 2002, . . . , 200L are not used (that is their currents are dissipated towards VDD or towards GND). Conversely, they are used during the phase with RTZ=0 (T.sub.OFF interval) as a function of the value of other L bits OFF[M+L−1:M] added to the M-bit trimming signal for offset compensation OFF[M−1: 0].

(203) In embodiments as exemplified in FIG. 13, the DAC control circuitry can be essentially as illustrated in FIG. 7 for driving the first M bits (cells 201, 202, . . . , 20M), while the further L bits (cells 2001, 2002, . . . , 200L) can be driven as in the case of FIG. 4, with RTZ used in the place of RTZ).

(204) One or more embodiments as exemplified in FIG. 13 may thus implement an “increased” full correction scale, equal to:

(205) $\begin{array}{cc}{I}_{\mathrm{OFF\_avg}\mathrm{\_FullScale}}=\pm \frac{T_{OFF}}{T_s}.Math.I_{LSB}.Math.\left(M+L\right)& \left(9\right)\end{array}$

(206) Also in this case the operation linked to the M-bit feedback word “SDout” is not affected.

(207) One or more embodiments as exemplified in FIG. 13 can thus be regarded as a providing a sort of “hybrid” solution between embodiments as exemplified in FIG. 7 and a conventional solution as presented in FIG. 4.

(208) In terms of area and current consumption, one or more embodiments as exemplified in FIG. 13 may turn out to be less advantageous if compared to embodiments as exemplified in FIG. 7 (and FIG. 8). However, they are more advantageous if compared with a conventional solution as exemplified in FIG. 4 for a same full-scale offset compensation.

(209) In FIG. 14 illustrates a possible “voltage-based” implementation of a DAC 20 for which a “current-based” implementation is illustrated in FIG. 13.

(210) The prior discussion in FIG. 13 thus essentially applies to the implementation illustrated in FIG. 14.

(211) An implementation as illustrated in FIG. 14 can thus provide a full scale value of the equivalent mean value of the offset correction current which can be expressed as:

(212) 0$\begin{array}{cc}{I}_{\mathrm{OFF\_a\nu g}\mathrm{\_FullScale}}=\pm \frac{T_{OFF}}{T_s}.Math.\frac{V_{LSB}}{R}.Math.M& \left(10\right)\end{array}$

(213) and an equivalent mean value of the feedback current which can be expressed as:

(214) $\begin{array}{cc}{I}_{\mathrm{OFF\_avg}\mathrm{\_FullScale}}=\pm \frac{T_{OFF}}{T_s}.Math.\frac{V_{LSB}}{R}.Math.\left(M+L\right).& \left(11\right)\end{array}$

(215) It will be appreciated that, while possibly advantageously sharing the differential architecture (input port 141, 142; differential amplifier 22; bias cells 201, . . . , 20M arranged between sources 20A, 20B; output lines 120, 220, and so on) of conventional converters 10 as discussed in connection with FIGS. 1 to 4, one or more embodiments as exemplified herein need not necessarily rely on such an architecture in order to facilitate offset correction via the M-bit (or M+L-bit) digital word OFF [M−1: 0] (or OFF [M+L−1: 0]) during the second time intervals T.sub.OFF which are interleaved with the first time intervals T.sub.GAIN.

(216) Consequently, while advantageous, such a differential architecture does not represent a mandatory feature of the embodiments.

(217) One or more embodiments as exemplified herein may thus relate to a converter circuit (for instance, a delta-sigma converter such as 10), comprising:

(218) an analog-to-digital signal conversion path (for instance, 12, 22, 24, 26, 28) from an input port (for instance, 14, 141, 142) to an output port (for instance, 16), the input port configured to receive an analog input signal having an offset and the output port configured to deliver a digital output signal quantized (28) over M levels, the digital output signal resulting from conversion to digital of the analog input signal,

(219) a digital-to-analog feedback path (for instance, 18, 20, 120, 220) from the output port to the input port, the feedback path comprising a digital-to-analog converter (for instance, 20) configured to apply (for instance, subtract see 120, 220) to the input port of the analog-to-digital signal conversion path an analog feedback signal produced (for instance, 201, . . . , 20M, 40) as a function of a M-bit digital word (for instance, BPN.sub.1, . . . , BPN.sub.M, possibly in its logic complementary or negated version) under the control of a two-state signal (for instance, return-to-zero RTZ) having alternating first states (for instance, T.sub.GAIN) and second states (for instance, T.sub.OFF) during which the two-state signal has a first value and a second value, respectively.

(220) In one or more embodiments as exemplified herein, the converter circuit may comprise M-bit digital word generation circuitry (for instance, 441, 442, 45, 46) sensitive to the two-state signal and configured to produce the M-bit digital word, alternately:

(221) during the first states, as a first M-bit digital word (for instance, SDout [M−1: 0]) which is a function of the digital output signal quantized over M levels,

(222) during the second states, as a second M-bit digital word (for instance, OFF [M−1: 0]; OFF [M+L−1: 0) which is a function a correction value of the offset in the analog input signal.

(223) In one or more embodiments as exemplified herein the digital word generation circuitry (for instance, 40) may comprise two-state signal generation circuitry (for instance, 41, 421, 422, 43) configured to produce the two-state signal having alternating first states and second states, wherein the two-state signal generation circuitry may comprise:

(224) a counter circuit (for instance, 41) configured to be clocked by a clock signal (for instance, CLK),

(225) a counter threshold circuit (for instance, 421, 422, 43) configured to set the two-state signal to the first state and to the second state at a first count value and a second count value, respectively, of the counter circuit.

(226) In one or more embodiments as exemplified herein the counter circuit may comprise an N-bit counter and the counter threshold circuit may comprise N-bit thresholds (for instance, t.sub.SET [N−1: 0]; t.sub.RST [N−1: 0]), defining the first count value and the second count value, respectively.

(227) In one or more embodiments as exemplified herein the digital-to-analog converter in the digital-to-analog feedback path may comprises a plurality of M bias cells (for instance, 201, . . . , 20j, . . . , 20M) wherein each cell in the plurality of M bias cells is individually switchable, as a function of the logical value of a respective one of the bits in the M-bit digital word (for instance, BPN.sub.1, . . . , BPN.sub.M, possibly in its logic complementary or negated version), to a conductive state during which the bias cell electrically couples at least one output line (for instance, 120, 220) of the digital-to-analog converter to at least one signal source (for instance, I.sub.LSB/2; V.sub.LSB/2, −V.sub.LSB/2).

(228) In one or more embodiments as exemplified herein resorting to a (non-mandatory) differential architecture:

(229) the input port to the analog-to-digital conversion path may comprise a differential input with a first input node (for instance, 141) and a second input node (for instance, 142) configured to receive the analog input signal applied therebetween,

(230) the digital-to-analog converter in the digital-to-analog feedback path may comprise a first output line (for instance, 120) and a second output line (for instance, 220) configured to apply (for instance, subtract) an analog feedback signal between the first input node and the second input node of the input port of the analog-to-digital signal conversion path,

(231) the digital-to-analog converter in the digital-to-analog feedback path may comprise a plurality of M bias cells (that is equal in number to the levels of the quantized output signal, see, for instance, 201, . . . , 20j, . . . , 20M) wherein each cell in the plurality of M bias cells is individually switchable, as a function of the logical value of a respective one of the bits in the M-bit digital word, to a conductive state during which the cell electrically couples the first output line and the second output line of the digital-to-analog converter to a first signal source (for instance, 20A; I.sub.LSB/2; V.sub.LSB/2) and a second signal source (for instance, 20B; I.sub.LSB/2; −V.sub.LSB/2), respectively.

(232) In one or more embodiments as exemplified herein, the M-bit digital word generation circuitry may comprise a dynamic matching circuit (for instance, 47) configured to receive the M-bit digital word (for instance, BPN.sub.1, . . . , BPN.sub.M possibly in its logic complementary or negated version) and to cyclically vary the respective one of the bits in the M-bit digital word as a function of which each cell in the plurality of M bias cells is individually switchable to the conductive state.

(233) In one or more embodiments as exemplified herein:

(234) the M bias cells (for instance, 201, . . . , 20j, . . . , 20M) are configured to provide respective, substantially identical bias contributions to the digital-to-analog converter,

(235) at least one (for instance, 201) of the M bias cells may comprise a set of H bias sub-cells (for instance, 2011, . . . 201H), wherein each sub-cell in the set of H bias sub-cells is configured to provide a bias current contribution to the digital-to-analog converter which is 1/H the substantially identical contribution, and

(236) the H bias sub-cells in the at least one of the M bias cells may be configured to be switched to a conductive state:

(237) identically to one another during the first states (for instance, T.sub.GAIN) as a function of the logical value of the respective one of the bits in the M-bit digital word to provide a respective bias contribution of the at least one of the M bias cells to the digital-to-analog converter,

(238) differently from one another during the second states (for instance, T.sub.OFF) to provide a reduced bias contribution of the at least one of the M bias cells to the digital-to-analog converter, the reduced bias contribution being a function of the number of the sub-cells in the set of H sub-cells that are in a conductive state.

(239) In one or more embodiments as exemplified herein, the digital-to-analog converter in the digital-to-analog feedback path may comprise a set of L supplemental bias cells (for instance, 2001, . . . , 200L) activatable during the second states, as a function of a third digital word (for instance, OFF [M+L−1: 0]), the third digital word comprising the second M-bit digital word (OFF [M−1: 0]) supplemented by a set of L bits of correction value of the offset in the analog input signal.

(240) In one or more embodiments as exemplified herein, the bias cells (for instance, 201, . . . , 20M and possibly comprising the sub-cells 2011, . . . , 201H and/or the supplementary cells 2001, . . . , 200L) may comprise electronic switches, optionally transistors such as MOSFET transistors.

(241) A device as exemplified herein may comprise:

(242) a signal source (for instance, a sensor S), the source producing an analog signal (for instance, I.sub.SENSE, V.sub.SENSE) having an offset,

(243) a converter circuit (for instance, a delta-sigma converter 1o) as exemplified herein, the converter circuit having the input port (for instance, 14, 141, 142) coupled to the signal source to receive therefrom the analog signal and to deliver at the output port (16) a digital output signal quantized over M levels, the digital output signal resulting from conversion to digital of the analog signal from the signal source.

(244) A method as exemplified herein may comprise:

(245) receiving at an input port of an analog-to-digital signal conversion path an analog input signal having an offset,

(246) delivering at an output port a digital output signal quantized over M levels, the digital output signal resulting from conversion to digital of the analog input signal,

(247) providing a digital-to-analog feedback path from the output port to the input port, the feedback path comprising a digital-to-analog converter configured to apply (for instance, subtract) at the input port an analog feedback signal produced as a function of an M-bit digital word,

(248) wherein the method may comprise producing the M-bit digital word, alternately:

(249) during first time intervals (for instance, T.sub.GAIN), as a first M-bit digital word (for instance, SDout [M−1: 0]) which is a function of the digital output signal quantized over M levels,

(250) during second time intervals (for instance, T.sub.OFF) interleaved with first time intervals, as a second M-bit digital word (for instance, OFF [M−1: 0] or OFF [M+L−1: 0]) which is a function a correction value of the offset in the analog input signal.

(251) Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only without departing from the extent of protection.

(252) The extent of protection is determined by the annexed claims.

(253) While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.