Device having a membrane and method of manufacture

Abstract

In an embodiment a device includes a substrate including an upper substrate surface and a lower substrate surface and a membrane-layer suspended above the upper substrate surface, wherein the substrate includes a recess penetrating the substrate between the lower substrate surface and the upper substrate surface, wherein the membrane-layer spans the recess, wherein the recess includes an upper recess region, an intermediate recess region, and a lower recess region, wherein the upper recess region is a part of the recess in direct vicinity to the upper substrate surface, the intermediate recess region is a part of the recess directly below the upper recess region, and the lower recess region is a part of the recess other than the upper recess region and the intermediate recess region, and wherein a cross-sectional area of the upper recess region determined parallel to the upper substrate surface is larger than a respective cross-sectional area of the intermediate recess region.

Claims

1. A device comprising: a substrate comprising an upper substrate surface and a lower substrate surface, wherein the lower substrate surface is a surface of the substrate opposite to the upper substrate surface; a membrane-layer suspended above the upper substrate surface, wherein the substrate comprises a recess penetrating the substrate between the lower substrate surface and the upper substrate surface, wherein the membrane-layer spans the recess, wherein the recess comprises: an upper recess region, an intermediate recess region, and a lower recess region, wherein the upper recess region is a part of the recess in direct vicinity to the upper substrate surface, the intermediate recess region is a part of the recess directly below the upper recess region, and the lower recess region is a part of the recess other than the upper recess region and the intermediate recess region, and wherein a cross-sectional area of the upper recess region determined parallel to the upper substrate surface is larger than a respective cross-sectional area of the intermediate recess region; and a first insulation layer arranged between the upper substrate surface and the membrane-layer, wherein the first insulation layer comprises an opening framed by a lower etch stopper and the lower etch stopper is positioned at a distance outward from an edge of the upper recess region, and wherein the lower etch stopper has a higher tensile strength than a main component of the first insulation layer.

2. The device according to claim 1, further comprising a silicon nitride layer arranged directly on the upper substrate surface, and wherein an opening in the silicon nitride layer is at least as wide as the opening of the recess in the upper substrate surface and at maximum as wide as the opening in the first insulation layer.

3. The device according to claim 1, further comprising a second insulation layer arranged directly above the membrane-layer, wherein an opening in the second insulation layer is framed by an upper etch stopper, and wherein the upper etch stopper has a higher tensile strength than a main component of the second insulation layer.

4. The device according to claim 3, wherein a material of the substrate is silicon, wherein a material of the second insulation layer and the first insulation layer comprises silicon oxide, and wherein a material of the lower etch stopper and of the upper etch stopper comprises at least one substance selected from silicon or silicon nitride.

5. The device according to claim 1, wherein the device is a MEMS microphone.

6. A method for forming a device, the method comprising: providing a substrate comprising an upper substrate surface and a lower substrate surface that are opposing each other; forming a continuous, self-contained trench with a width and a depth in the upper substrate surface by a first structuring technique; filling the trench with a filling material; forming a membrane-layer above the upper substrate surface comprising the filled trench; forming a preliminary recess in the substrate by a second etching technique applied from a side of the lower substrate surface, wherein the preliminary recess comprises a preliminary upper recess region extending from the upper substrate surface to the depth, and the preliminary upper recess region is framed by the filling material of the trench, wherein an intermediate recess region is a region of the preliminary recess directly below the preliminary upper recess region, wherein sidewalls of the intermediate recess region lie within a spatial volume perpendicularly below the trench, wherein a lower recess region is a part of the preliminary recess other than the preliminary upper recess region and the intermediate recess region, forming a recess by removing the filling material with a third etching technique; and wherein the recess comprises the intermediate recess region, the lower recess region, and an upper recess region, and wherein the upper recess region is formed by a combined volume of the trench and the preliminary upper recess region.

7. The method according to claim 6, wherein the width of the trench is at least twice a tolerance of the second etching technique in forming the intermediate recess region.

8. The method according to claim 6, wherein the filling material comprises a lower etching rate than the substrate in the second etching technique.

9. The method according to claim 6, wherein the first structuring technique applied to the upper substrate surface has a lower tolerance than the second etching technique applied to the substrate.

10. The method according to claim 6, wherein a tolerance of the first structuring technique applied to the upper substrate surface is at least 10 times smaller than a tolerance of the second etching technique applied to the substrate.

11. The method according to claim 6, wherein a tolerance of the first structuring technique applied to the upper substrate surface is ±1 μm or less, and wherein a tolerance of the second etching technique applied to the substrate is ±1 μm or less.

12. The method according to claim 6, wherein a material of the substrate is silicon, wherein the filling material is at least one selected from the group consisting of silicon oxide, phosphosilicate glass, and borophosphosilicate glass, wherein the first structuring technique is a slow deep reactive ion etching technique applied from the side of the upper substrate surface, wherein the second etching technique is a fast deep reactive ion etching technique applied from the side of the lower substrate surface, and wherein the third etching technique is a buffered oxide etching technique.

13. The method according to claim 6, further comprising applying chemical mechanical polishing to the upper substrate surface and the filled trench, directly after filling the trench with the filling material.

14. The method according to claim 6, wherein the filling material comprises a higher etching rate than the substrate in the third etching technique.

15. The method according to claim 14, further comprising: forming a first insulation layer between the upper substrate surface and the membrane-layer; and forming a lower etch stopper in the first insulation layer, wherein the lower etch stopper is positioned at a distance e away from an outward rim of the trench, and wherein a material of the lower etch stopper has a lower etching rate in the third etching technique than at least an inner portion of the first insulation layer, which is framed by the lower etch stopper.

16. The method according to claim 15, further comprising: forming a silicon nitride layer directly on the upper substrate surface, before forming the first insulation layer; and removing the silicon nitride layer in a section arranged perpendicularly above the upper recess region.

17. The method according to claim 15, further comprising: forming a second insulation layer above the membrane-layer; and forming an upper etch stopper in the second insulation layer, wherein a material of the upper etch stopper has a lower etching rate in the third etching technique than at least an inner portion of the second insulation layer, which is framed by the upper etch stopper.

18. The method according to claim 17, wherein an inner portion of the first insulation layer framed by the lower etch stopper and the inner portion of the second insulation layer framed by the upper etch stopper are removed during the third etching technique.

19. The method according to claim 17, wherein the material of the second insulation layer and the first insulation layer comprises silicon oxide, and wherein the material of the lower etch stopper and the upper etch stopper comprises at least one substance selected from silicon and silicon nitride.

20. The method according to claim 6, wherein the device is a MEMS microphone.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In the following the invention is explained in greater detail on the basis of exemplary embodiments and the associated figures.

(2) The figures serve solely for elucidating the invention and are therefore illustrated only schematically and not in a manner true to scale. Individual parts may be illustrated in an enlarged manner or in a distorted manner in terms of the dimensions. Therefore, neither absolute nor relative dimensional specifications can be inferred from the figures. Identical or identically acting parts are provided with identical reference signs.

(3) In the figures:

(4) FIGS. 1 and 2 show a first step of a first embodiment of a method for forming a MEMS microphone in schematic top view and schematic cross section, respectively;

(5) FIGS. 3 and 4 show a second step of a first embodiment of a method for forming a MEMS microphone in schematic top view and schematic cross section, respectively;

(6) FIGS. 5 and 6 show a third step of a first embodiment of a method for forming a MEMS microphone in schematic top view and schematic cross section, respectively;

(7) FIG. 7 shows a fourth step of a first embodiment of a method for forming a MEMS microphone in schematic cross section;

(8) FIGS. 8 and 9 show a fifth step of a first embodiment of a method for forming a MEMS microphone in schematic top view and schematic cross section, respectively;

(9) FIG. 10 shows a sixth step of a first embodiment of a method for forming a MEMS microphone in schematic cross section;

(10) FIGS. 11 and 12 show a seventh step of a first embodiment of a method for forming a MEMS microphone in schematic top view and schematic cross section, respectively;

(11) FIG. 13 shows an eighth step of a first embodiment of a method for forming a MEMS microphone in schematic cross section;

(12) FIG. 14 shows a ninth step of a first embodiment of a method for forming a MEMS microphone in schematic cross section;

(13) FIG. 15 shows a detailed excerpt of the ninth step of a first embodiment of a method for forming a MEMS microphone in schematic cross section;

(14) FIG. 16 shows first embodiment of a MEMS microphone in schematic cross section;

(15) FIG. 17 shows a second step of a second embodiment of a method for forming a MEMS microphone in schematic top view; and

(16) FIG. 18 shows third embodiment of a MEMS microphone in schematic cross section.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(17) In the following a first embodiment of a method for forming a MEMS microphone is described in reference to figures showing intermediate steps during the process in schematic views.

(18) FIG. 1 shows a schematic top view on an upper substrate surface 21 of a substrate 2.

(19) FIG. 2 shows a schematic cross-section of the substrate 2 along the line A-B indicated in FIG. 1.

(20) A lower substrate surface 22 is the surface of the substrate 2 opposite to the upper substrate surface 21.

(21) The material of the substrate 2 is silicon. For example, the substrate 2 is a silicon wafer.

(22) As shown in FIGS. 3 (top view) and 4 (cross section), a trench 3 is formed in the upper substrate surface by a first structuring method.

(23) In the first embodiment, the trench 3 is ring shaped. The trench 3 has a depth d and width w between an inner rim of the trench 31 and an outer rim of the trench 32.

(24) The width w of the trench 3 is chosen to compensate for the tolerance of an etching technique for forming a preliminary recess, as is described below.

(25) For example, the width may be 30 μm. For example, the depth d of the trench 3 may be 2-8 μm.

(26) Preferably, the trench has a rectangular cross section, as indicated in FIG. 4.

(27) The first structuring method can be any method suitable for forming a ring shaped trench 3 into a silicon substrate 2. Preferably, the first structuring method has a tolerance of ±1 μm or below.

(28) For example, a sputtering method can be applied to form the trench.

(29) Preferably, a slow DRIE etching technique is applied from the front side, i.e. the side of the upper substrate surface 21. The slow DRIE etching technique comprises application of a photolithographic step with a precision/tolerance of below ±1 μm. Subsequently, the trench 3 is etched into the substrate and masks from the photolithography are removed.

(30) For example the slow DRIE method has etching rates in the order of below 1 μm/min and up to 4 μm/min.

(31) Next, the trench 3 is filled with a filling material 4, as shown in FIGS. 5 (top view) and 6 (schematic cross-section).

(32) The filling material 4 comprises silicon oxide. The filling material 4 can be pure silicon oxide, or preferably, doped silicon oxide, such as phosphosilicate glass or borophosphosilicate glass.

(33) The doped silicon oxide has the advantage that it can be etched more efficient in a subsequent buffered oxide etching step than pure silicon oxide.

(34) The silicon oxide or doped silicon oxide can be deposited by any suitable means. Preferably, it is deposited by a plasma enhanced chemical vapor deposition (PECVD) method using tetraethyl orthosilicate (TEOS)

(35) Preferably, a chemical mechanical polishing step is applied after filling of the trench 3, to level the upper surface of the filling material 4 and the upper substrate surface 21.

(36) As shown in FIG. 7 in schematic cross section a silicon nitride layer 5 is formed on the upper substrate surface 21 comprising the filled trench 3.

(37) The material of the silicon nitride layer 5 is preferably low stress silicon nitride that shows comparatively low tensile stress in the order of 250 MPa or below. Preferentially, the low stress silicon nitride has a tensile stress of 135 MPa or below.

(38) The silicon nitride layer 5 can be deposited by any suitable means. Preferably, the silicon nitride layer 5 is deposited by low pressure chemical vapor deposition (LPCVD).

(39) The thickness of the silicon nitride layer 5 can be in the range of 0.1 μm to 1 μm and preferably in the range of 0.1 μm to 0.3 μm.

(40) As shown in FIGS. 8 (top view) and 9 (schematic cross section) a first insulation layer 6 is arranged on the silicon nitride layer 5.

(41) The material of the first insulation layer 6 is silicon oxide, which can be deposited by any suitable means. Preferably, it is deposited a PECVD method using TEOS.

(42) A thickness of the first insulation layer 6 may be 0.5 μm.

(43) A fraction of the first insulation layer 6 is removed to form a trench-shaped notch in the first insulation layer 6 at which bottom the silicon nitride layer 5 is exposed.

(44) This trench-shaped notch is ring-shaped in the present embodiment.

(45) The trench-shaped notch can be formed by any suitable method, for example lithography-based methods or etching techniques.

(46) Subsequently the trench-shaped notch is filled with silicon nitride, and more preferably with low-stress silicon nitride to form the lower etch stopper 61. The silicon nitride of the lower etch stopper 61 can be deposited by any suitable means. Preferably, the silicon nitride is deposited by LPCVD.

(47) The lower etch stopper 61 is ring-shaped and frames an inner portion 62 of the first insulation layer 6.

(48) The ring formed by the lower etch stopper 61 is co-centered with the ring-shaped trench 3. The lower etch stopper 61 is positioned at a distance e from the outer rim 32 of the trench 3. The distance e can be 1-5 μm, for example.

(49) Next, as shown in FIG. 10 in schematic cross section, a membrane-layer 7 is arranged on the first insulation layer 6.

(50) The membrane-layer 7 comprises silicon, which can be deposited for example by LPCVD. The membrane-layer 7 can, for example, comprise doped poly-silicon.

(51) The thickness of the membrane-layer 7 can be in the order of 0.5 μm.

(52) At this process step the membrane-layer 7 can be structured, for example by photo-lithographic methods.

(53) As shown in FIGS. 11 (top view) and 12 (schematic cross section) a second insulation layer 8 is arranged on the membrane-layer 7.

(54) The material of the second insulation layer 8 is silicon oxide, which can be deposited by any suitable means. Preferably, it is deposited a PECVD method using TEOS.

(55) The thickness of the second insulation layer 8 may be in the order of 2.35 μm.

(56) A fraction of the second insulation layer 8 is removed to form a trench-shaped notch in the second insulation layer 8 at which bottom the membrane-layer 7 is exposed.

(57) This trench-shaped notch is ring-shaped.

(58) The trench-shaped notch can be formed by any suitable method, for example lithography-based methods or etching techniques.

(59) Subsequently the trench-shaped notch is filled with silicon nitride, and preferably with low-stress silicon nitride, to form the upper etch stopper 81. The silicon nitride upper etch stopper 81 can be deposited by any suitable means. Preferably, the silicon nitride upper etch stopper 81 is deposited by LPCVD.

(60) The upper etch stopper 61 is ring-shaped and frames an inner portion 82 of the second insulation layer 8.

(61) The ring formed by the upper etch stopper 81 is co-centered with the ring-shaped trench 3 and with the ring formed by the lower etch stopper 61. The ring of the upper etch stopper 81 has a smaller diameter than the ring of the lower etch stopper 61.

(62) The lateral distance between the upper etch stopper 81 and the lower etch stopper 61 is defined as lateral membrane suspension distance, and it is measured parallel to the upper substrate surface 21. The lateral membrane suspension distance equals half the diameter difference between the rings of the upper etch stopper 81 and the lower etch stopper 61.

(63) Preferably, the lateral membrane suspension distance is in the range of 3-10 μm.

(64) As shown in the schematic cross section in FIG. 13, next a back plate layer 9 is formed on the second insulation layer 8.

(65) The back plate layer 9 comprises silicon, which can be deposited for example by LPCVD. The back plate layer 9 can, for example, comprise doped poly-silicon.

(66) The thickness of the back plate layer 9 can be in the order of 1 μm to 5 μm.

(67) Electrical contacts can be applied to the as assembled layered stack, after forming of the back plate layer 9 (not shown).

(68) At this process step the back plate layer 9 can be structured laterally, similar as the membrane 7, for example to comprise venting holes. This can be performed, for example, by photo-lithographic methods.

(69) As shown in the schematic cross section in FIG. 14, next a preliminary recess 10′ is formed in the substrate 2 by a second etching technique.

(70) The second etching technique may be any suitable method for forming a preliminary recess 10′ into a silicon substrate 2. Preferably, the preliminary recess 10′ is formed by a fast DRIE method applied from the back side, i.e. the side of the lower substrate surface 22.

(71) The substrate 2 is etched from the lower substrate surface 22 up to the upper substrate surface 21.

(72) The preliminary recess 10′ comprises the preliminary upper recess region 101′.

(73) The preliminary upper recess region 101′ is the portion of the preliminary recess 10′ in closest proximity to the membrane-layer 7.

(74) The preliminary upper recess region 101′ extends from the upper substrate surface 21 to the depth d. It is framed by the inner rim 31 of the filling material 4 of the trench 3.

(75) In other words, the second etching technique removes the substrate material until at least the inner rim 31 of the filling material 4 is exposed completely.

(76) The preliminary upper recess region 101′ is of cylindrical shape, with walls of the preliminary upper recess region 101′ (=inner rim 31) being perpendicular to the upper substrate surface 21.

(77) The region of the preliminary recess 10′ directly below the preliminary upper recess region 101′ is defined as intermediate recess region 102.

(78) The diameter of the intermediate recess region 102 is at least the diameter of the preliminary upper recess region 101′.

(79) Typically, the diameter of the intermediate recess region 102 is larger than the diameter of the preliminary upper recess region 101′.

(80) At maximum, the diameter of the intermediate recess region equals the diameter of the outer rim 32 of the trench.

(81) The region of the preliminary recess 10′, which is not the preliminary upper recess region 101′ or the intermediate recess region 102, is defined as lower recess region.

(82) Preferentially, the diameter of the lower recess region 103 is at least the diameter of the preliminary upper recess region 101′.

(83) For example, the diameter of the lower recess region 103 is larger than the diameter of the preliminary upper recess region 101′.

(84) Preferentially, at maximum, the diameter of the lower recess region equals the diameter of the outer rim 32 of the trench.

(85) FIG. 15 shows an enlarged excerpt of the intermediate structure during formation of a MEMS microphone shown in FIG. 14, after forming of the preliminary recess 10′.

(86) The second etching technique in general and a fast DRIE method in particular have a limited tolerance in forming the side walls of the preliminary recess 10′.

(87) In the preliminary upper recess region 101′, the side walls are defined with the tolerance of the first structuring method, as the filling material 4 has a considerably lower etching rate in the second etching technique than the silicon substrate 2.

(88) In particular, fast DRIE causes notches and bulges in the wall of the intermediate recess region 102 around an intended position x of the wall.

(89) However, these notches and bulges, i.e. the entire wall of the intermediate recess region 102 must not extend beyond the spatial volume perpendicularly below the filling material 4 of the trench 3. This volume has the width w of the trench and is a semi-infinite cylindrical shell extending below the filling material 4 of the trench 3.

(90) This means, that the width w of the trench 3 is chosen dependent on the tolerance of the second etching technique. The lateral dimension of the trench 3 extends with the given tolerance of the etching step from an intended position x of the sidewall in both directions that is the width w is two times the tolerance.

(91) For example, a fast DRIE method has a tolerance of ±15 μm. Therefore, the width w is chosen to be at least 15 μm.

(92) Preferentially, the width w is chosen to be exactly 15 μm. Thus, the trench 3 can compensate for the tolerance of the second etching technique, but the outer rim 32 of the trench, and with it the rim of the upper recess region in the as assembled device (compare below) is as close as possible to the average diameter of the recess.

(93) Preferentially, the lower recess region fulfills the same conditions, as the intermediate recess region.

(94) FIG. 16 shows the as assembled MEMS microphone 1.

(95) It is formed from the intermediate structure shown in FIG. 14 by applying a third etching technique.

(96) By the third etching technique, the inner portion 82 of the second insulation layer 8 is removed creating the opening 82′ in the second insulation layer 8 between the back plate layer 9 and the membrane-layer 7. The opening 82′ is framed by the upper etch stopper 81.

(97) Further, the inner portion 62 of the first insulation layer 6 is removed by the third etching technique, creating the opening 62′ in the first insulation layer 6 directly below the membrane. The opening 62′ is framed by the lower etch stopper 61.

(98) Further, the filling material 4 is removed by the third etching technique. Thereby, the upper recess region 101 forms as a combined volume of the preliminary upper recess region and the volume of the trench 3.

(99) Thus, the recess 10 is formed from the upper recess region 101, the intermediate recess region 102, and the lower recess region 103.

(100) At maximum, the diameter of the intermediate recess region 102, is as large as the diameter of the upper recess region 101, i.e. the diameter of the outer rim 32 of the trench 3.

(101) Preferably, the diameter of the intermediate recess region 102, is smaller than the diameter of the upper recess region 101, i.e. the diameter of the outer rim 32 of the trench 3.

(102) Thereby, the step 104 between the upper recess region 101 and the intermediate recess region 102 is formed in the substrate 2.

(103) During application of the third etching technique an opening is also etched into the silicon nitride layer 5. The opening in the silicon nitride layer 5 has approximately the diameter of the upper recess region 101 and connects the recess 10 to the opening 62′ in the first insulation layer 6, thereby forming a sound channel towards the membrane-layer.

(104) The mean diameter of the sound channel can be in the range of 500-1700 μm.

(105) The overall dimensions of the MEMS microphone can be for example, 0.8 mm×2 mm×2 mm.

(106) The third etching technique, can be any suitable technique to etch silicon oxide or doped silicon oxide efficiently, while silicon and silicon nitride are less affected by the etching.

(107) In other words, the etching rates of silicon oxide or doped silicon oxide in the third etching technique are greater than those of silicon and silicon nitride.

(108) For example, the third etching step may be a buffered oxide etching step based on hydrogen-fluoride etching.

(109) The third etching technique can comprise either one common etching step or two sub-steps.

(110) In the case of one common etching step, the buffered oxide etching solution can be applied via the recess 10. Thereby, the etching solution first dissolves the filling material 4, and slowly etches through the thin nitride layer 5. Then the solution again etches fast through the silicon oxide of the inner portion 62 of the first insulation layer 6. The lower etch stopper prevents over etching of the first insulation layer 6.

(111) Through pores in the membrane-layer 7, the etching solution can reach the inner portion 82 of the second insulation layer and dissolve it.

(112) If the third etching technique comprises two sub-steps, first the etching solution is applied through the recess to dissolve the filling material 4. The silicon nitride layer 5 stops the etching. The inner portions 82 and 62 of the second and the first insulation layer 8 and 6 are etched in an independent sub-step from the front side, i.e. through pores in the back plate layer 9 and in the membrane-layer 7.

(113) The opening in the silicon nitride layer 5 is formed by the combined etching of both sub-steps.

(114) In the as assembled MEMS device, the area of the membrane-layer 7 being freestanding over the sound channel is the active membrane area.

(115) The lower and the upper etch stoppers 62 and 82 act as the lower and the upper membrane suspension, respectively. As they are of low-stress silicon nitride, they feature high tensile strength. Therefore, the membrane suspension can resists high deflections.

(116) FIG. 17 shows a schematic top view of a second embodiment of a fabrication method of a MEMS microphone.

(117) FIG. 17 shows the formation of a trench 3 in a substrate 2.

(118) In the second embodiment, the sound channel in general, and therefore the trench 3 and the recess 10 (not shown) and all other openings (not shown) have oval shape instead of circular shape.

(119) Otherwise, both concerning method and final device, the second embodiment is equivalent to the first embodiment, as described above.

(120) FIG. 18 shows a schematic cross section of a third embodiment of MEMS microphone.

(121) The third embodiment resembles the first or the second embodiment, except for the following properties.

(122) The membrane-layer 7 and the back plate layer 9 are both multi-layered.

(123) The membrane-layer 7 comprises a lower membrane-layer 71, a central membrane-layer 72 and an upper membrane-layer 73, directly arranged one upon another. This means, the central membrane-layer 72 is sandwiched by the upper and the lower membrane-layers 71 and 73.

(124) The upper and the lower membrane-layers 71 and 73 are low-stress silicon nitride layers, and the central membrane-layer 72 is a doped poly-silicon layer. Both can be deposited by LPCVD methods

(125) The doped poly-silicon provides conductivity to the membrane 7. The low stress silicon nitride enhances the resistivity and also insulates the central membrane-layer 72.

(126) Furthermore, the lower etch stopper 61 is formed as a part of the membrane-layer 7.

(127) To this end, a V-shaped notch is formed in the first insulation layer 6 and the membrane-layers 71, 72, 73 are deposited onto the as formed structure without individually forming an etch stopper. By this, the V-shape is transferred into the membrane-layer 7, forming the lower etch stopper 61.

(128) Equivalently, also the back plate layer 9 is multi-layered. The back plate layer 9 comprises a lower back plate layer 91, a central back plate layer 92 and an upper back plate layer 93, directly arranged one upon another. This means, the central back plate layer 92 is sandwiched by the upper and the lower back plate layers 91 and 93.

(129) The lower and the upper back plate layers 91 and 93 are low-stress silicon nitride layers, and the central back plate layer 92 is a doped poly-silicon layer. Both can be deposited by LPCVD methods.

(130) The doped poly-silicon provides conductivity to the membrane. The low stress silicon-nitride insulates the central back plate layer 92.

(131) Furthermore, the upper etch stopper 81 is formed as a part of the back plate layer 9.

(132) To this end, a V-shaped notch is formed in the second insulation layer 8 and the back plate layers 91, 92, 93 are deposited onto the as formed structure without individually forming an etch stopper. By this, the V-shape is transferred into the back plat layer 9, whereby the upper etch stopper 81 is formed.

(133) By forming the etch stoppers 61 and 81 from the membrane-layer and the back plate layer, additional formation steps can be avoided, making the production process more efficient.

(134) Furthermore, FIG. 18 explicitly shows a structured inner region 94 of the back plate 9.

(135) Although the invention has been illustrated and described in detail by means of the preferred embodiment examples, the present invention is not restricted by the disclosed examples and other variations may be derived by the skilled person without exceeding the scope of protection of the invention.