ANALOGUE VOLTAGE PROGRAMMING

Abstract

An analog circuit arrangement (1) to variably set a voltage U.sub.out, within defined voltage limits, has a non-inverting adder (10) with a positive input (11). A voltage divider (20), with at least a first stage (21) and a second stage (22), is connected to the positive input (11) of the adder (10). At least one stage has a parallel circuit of n resistors (R1, R2, . . . , Rn) that are each connected in series in a conduction path (L1, L2, . . . , Ln) to an overcurrent protection device (F1, F2, . . . , Fn). At least one device (30) actively changes one or more of the overcurrent protection devices (F1, F2, . . . , Fn) into a state that interrupts the respective affected conduction path (L1, L2, . . . , Ln).

Claims

1.-10. (canceled)

11. An analog circuit arrangement for variably setting a voltage U.sub.out within defined voltage limits, comprising a non-inverting adder with a positive input; a voltage divider, including at least a first stage and a second stage, is connected to the positive input of the adder, at least one stage includes a parallel circuit of n resistors, each resistor is connected in series in a conduction path to an overcurrent protection device, and at least one device for actively changing one or more of the overcurrent protection devices into a state that interrupts the respective affected conduction path.

12. The analog circuit arrangement according to claim 11, wherein the overcurrent protection devices are configured as fuses.

13. The analog circuit arrangement according to claim 11, wherein the first stage of the voltage divider includes a fixed resistor.

14. The analog circuit arrangement according to claim 11, wherein the device is implemented as an emitter circuit with negative current feedback by an NPN transistor (NPN) and a PNP transistor (PNP), the base of the PNP transistor is connected to the collector of the NPN transistor via an intermediate tap of a voltage divider comprising at least two resistors.

15. The analog circuit arrangement according to claim 14, wherein the base of the NPN transistor (NPN) is driven by a microcontroller, preferably via a series resistor.

16. The analog circuit arrangement according to claim 15, wherein the NPN transistor base is connected to the emitter of the NPN transistor via a pull-down resistor R.sub.DP, intended to prevent uncontrolled switching on of the transistor, and the base of the NPN transistor is connected to a signal port (LOCK) which, in turn, is connected to the interlock circuit which is intended to execute the locking of that state of one or more overcurrent protection device(s) that have not yet been brought into the disconnected state.

17. The analog circuit arrangement according to claim 14, wherein a collector of the PNP transistor of the device can be or is connected to the overcurrent protection devices, respectively, in order to selectively bring the respective connected overcurrent protection device into a state interrupting the respective conduction path.

18. The analog circuit arrangement according to claim 11 further comprising a circuit for deactivating the at least one device is provided for locking that state of one or more overcurrent protection device(s) that have not yet been brought into the disconnecting state.

19. A method for variably setting a voltage U.sub.out within defined voltage limits using a circuit arrangement according to claim 1, comprising the step(s) of: selectively energizing one or more of the overcurrent protection devices with an overcurrent generated with the device; bringing the respective conduction path into the electrically isolated state in each case; changing the voltage, as intended, of the voltage divider at the input of the adder.

20. The method according to claim 19, wherein after selectively energizing one or more of the overcurrent protection devices with an overcurrent, deactivating the respective at least one device for actively changing one or more of the one or more of the overcurrent protection devices by a circuit.

Description

DRAWINGS

[0030] The drawings described herein are for illustrative purposes only of selected embodiments and not all possible implementations, and are not intended to limit the scope of the present disclosure.

[0031] FIG. 1 is a schematic view of a circuit arrangement for adjustable voltage generation;

[0032] FIG. 2 is a schematic view of a circuit arrangement for tripping an overcurrent protection device or fuse,

[0033] FIG. 3 is a schematic view of a diagram of the time sequence of a fuse tripping operation,

[0034] FIG. 4 is a schematic view of a circuit arrangement for locking the circuit arrangement for triggering an overcurrent protection device according to FIG. 2, and

[0035] FIG. 5 is a schematic view of an exemplary view of the time sequence for setting a desired voltage.

DETAILED DESCRIPTION

[0036] FIG. 1 is a circuit arrangement 1 according to the disclosure. The analog circuit arrangement 1 is configured to variably set a voltage U.sub.out within defined voltage limits at the non-inverting adder 10 shown.

[0037] The adder 10 has a positive input 11 and a negative input 12. The analog ground reference potential is designated AGND. A two-stage voltage divider 20 is connected to the positive input 11 of the adder 10. The voltage divider 20 includes a first stage 21, with a fixed resistor R.sub.f, and a second stage 22. The second stage 22 includes a parallel circuit of 4 resistors R1, R2, R3, and R4. Each resistor R1, R2, R3, R4 is arranged in a parallel conduction path L1, L2, L3, and L4, respectively, between the ground reference potential and the center tap 23 on the voltage divider 20.

[0038] Each resistor R1, R2, R3, and R4 is connected in series to an overcurrent protection device F1, F2, F3, F4 in the respective line path L1, L2, L3, and L4. A resistor R.sub.X is provided in the conduction path running from the analog ground reference potential to the negative input 12 of adder 10. Another resistor R.sub.y is provided in the connection to the output at adder 10. The voltage U.sub.out to be set is present at the output of the adder 10. Thus, this depends on which of the overcurrent protection devices F1, F2, F3, F4 have been tripped as intended.

[0039] FIG. 2 shows a device 30 according to the disclosure for tripping an overcurrent protection device F1, F2, F3, F4. The device 30 is formed as an emitter circuit with current feedback by an NPN transistor and a PNP transistor, where the base is designated by B, the emitter is designated by E, and the collector is designated by C, respectively.

[0040] The base B.sub.1 of the PNP transistor is connected to the collector C2 of the NPN transistor via the intermediate tap 31 of the voltage divider 33. formed by the two resistors R.sub.20, R.sub.30.

[0041] The base B.sub.2 of the NPN transistor is connected to a microcontroller μC via the series resistor RB. Thus, the base can be controlled by the microcontroller μC. A series resistor RB can be used to adjust the current flow into the base of the NPN transistor as desired.

[0042] Base B2 is further connected to a signal port (LOCK), that is connected to the interlock circuit shown in FIG. 4. The purpose of this is to cause a possibly desired “fading out” or “deactivation” of the control signals in such a way that the overcurrent protection devices F1, F2, F3, F4, which have not yet been tripped as intended, are locked against tripping for any other than the intended purpose. The pull-down resistor R.sub.DP prevents uncontrolled switching on of the NPN transistor. Another resistor R.sub.E is provided upstream of the PNP transistor. This resistor is used to limit the current flow through the PNP transistor and the voltage drop across the PNP transistor.

[0043] Current flow into the NPN transistor causes it to become conductive. This results in current flow across both resistors R.sub.20 and R.sub.30. The required current flow into the base B.sub.1 of the PNP transistor can be set accordingly if these two resistors R.sub.20 and R.sub.30. are dimensioned accordingly. This now results in the current flow via fuse F1, that must be dimensioned such that the fuse blows in the desired time. FIG. 3 shows a diagram of the time sequence of a fuse tripping operation.

[0044] For this purpose, the voltage that drops across the fuse was metrologically recorded. The current flow generated by the transistor first causes a potential rise at the fuse. The destruction process is underway. After about 11 ms, the fuse is completely blown and the entire voltage applied, minus the saturation voltage of the PNP transistor across the fuse, drops.

[0045] FIG. 4 shows a circuit arrangement for locking the circuit arrangement from tripping an overcurrent protection device according to FIG. 2.

[0046] The circuit 40 is also an emitter circuit with negative current feedback. In this embodiment, the fuse F1 is used to keep the other NPN transistor in the disabled state. As soon as fuse F1 has been tripped, as intended or has blown, the base of the NPN transistor is pulled to a higher potential. Thus, the transistor becomes conductive.

[0047] All control signals of the device 30 for tripping the fuses, except the signal for interlocking, are conducted to the collector of this NPN transistor via the diodes D shown. This leads to the fact that the respective affected devices 30 can no longer be activated. The “setting process” of the reference voltage is therefore irrevocably terminated after the fuse for locking has blown.

[0048] FIG. 5 shows an exemplary view of the time sequence for setting a desired voltage U.sub.out.

[0049] The reference voltage to be set (U.sub.out=upper curve) is at the potential of approx. 1100 mV before the tripping of a fuse F1. Now the first fuse F1 is blown first. After a trip from the first fuse F1, the reference voltage is at the voltage level of approx. 1300 mV. After that, the second fuse F2 is blown. The reference voltage U.sub.out has now reached the desired voltage level of about 1600 mV. After that, the interlock is activated to fix the obtained state.

[0050] Execution of the disclosure is not limited to the preferred exemplary embodiments mentioned above. Instead, a number of variants are conceivable which make use of the solution presented, even with fundamentally different designs.

[0051] The foregoing description of the embodiments has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but, where applicable, are interchangeable and can be used in a selected embodiment, even if not specifically shown or described. The same may also be varied in many ways. Such variations are not to be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure.