MEASUREMENT METHOD WITH SYNCHRONOUS SUBSAMPLING
20220185247 · 2022-06-16
Inventors
Cpc classification
G01R19/2509
PHYSICS
B64C25/46
PERFORMING OPERATIONS; TRANSPORTING
International classification
B60T8/17
PERFORMING OPERATIONS; TRANSPORTING
B60T8/32
PERFORMING OPERATIONS; TRANSPORTING
B64C25/46
PERFORMING OPERATIONS; TRANSPORTING
Abstract
An electronic circuit (12) connected to a variable-excitation sensor (24) and comprising: a digital envelope detector (20) arranged to acquire signal that is produced by the sensor in response to an excitation signal, the detector comprising: an analog-to-digital converter (22) arranged to sample the measurement signal in such a manner as to produce sample points during successive observation windows of duration T that comprise a number N.sub.S of sample points, the sample points being spaced apart by a sampling period T.sub.S, the sampling period T.sub.S and the duration T being such that:
T.sub.S=N.sub.P.Math.T.sub.0+(N.sub.T/N.sub.S).Math.T.sub.0 and T=N.sub.S.Math.T.sub.S,
where T.sub.0 is one excitation period of the excitation signal, where N.sub.P, N.sub.T, and N.sub.S are non-zero natural integers, and where N.sub.T is not a multiple of N.sub.S.
Claims
1. An electronic circuit arranged to be connected to a variable-excitation sensor for measuring a parameter, the electronic circuit comprising: synthesizer components arranged to use the same clock signal to produce both an excitation frequency (f.sub.0) and also a sampling frequency, together with an excitation signal at the excitation frequency, the excitation signal being applied as input to the sensor; and a digital envelope detector receiving as input a measurement signal that is produced by the sensor in response to the excitation signal, the digital envelope detector comprising: an analog-to-digital converter arranged to sample the measurement signal at the sampling frequency in such a manner as to produce sample points during successive observation windows, each observation window having a duration T and comprising a number N.sub.S of sample points, the sample points being spaced apart by a sampling period T.sub.S, the sampling period T.sub.S and the duration T being such that:
T.sub.S=N.sub.P.Math.T.sub.0+(N.sub.T/N.sub.S).Math.T.sub.0 and T=N.sub.S.Math.T.sub.S, where T.sub.0 is one excitation period of the excitation signal, where N.sub.P, N.sub.T, and N.sub.S are non-zero natural integers, and where N.sub.T is not a multiple of N.sub.S; and at least one processor component arranged to implement a synchronous demodulator arranged to produce, for each observation window, an output signal value on the basis of which the parameter is estimated.
2. The electronic circuit according to claim 1, wherein the number of sample points N.sub.S is defined so as to maximize elimination of harmonics of the excitation frequency and so as to maximize noise reduction in the digital envelope detector, while conserving a processing time allocated to each sample point that is acceptable given performances of the analog-to-digital converter and of the at least one processor component.
3. The electronic circuit according to claim 1, wherein N.sub.T=1.
4. The electronic circuit according to claim 1, wherein N.sub.T≠1.
5. The electronic circuit according to claim 1, wherein the excitation signal is a sinewave signal.
6. The electronic circuit according to claim 1, wherein the excitation signal is a squarewave signal.
7. The electronic circuit according to claim 1, wherein the digital envelope detector (20) comprises two processor components comprising both an FPGA arranged to carry out the multiplication-accumulation operations performed in the synchronous demodulator and also a microcontroller arranged to carry out the other operations performed in the synchronous demodulator.
8. The electronic circuit according to claim 1, further comprising an amplifier located upstream from the analog-to-digital converter, the amplifier including resistors forming part of a resistor network.
9. The electronic circuit according to claim 1, wherein the sensor has a plurality of output channels, and wherein the analog-to-digital converter comprises a single converter block together with a number of sample-and-hold circuits equal to the number of output channels of the sensor.
10. A method of designing an electronic circuit according to claim 1, the method comprising the steps of: defining an optimized value for the number of sample points N.sub.S, said optimized value maximizing elimination of harmonics of the excitation frequency and maximizing noise reduction in the digital envelope detector, while conserving a processing time that is allocated to each sample point that is acceptable given the performance of the analog-to-digital converter and given the processor component(s); and configuring the electronic circuit by conferring said optimized value to the number of sample points N.sub.S.
11. An electronic unit including an electronic circuit according claim 1.
12. A device comprising an electronic unit according to claim 11 and a variable-excitation sensor.
13. The device according to claim 12, the variable-excitation sensor being a tachometer arranged to measure the angular position and/or the angular speed of the wheel and comprising a first printed circuit and a second printed circuit that are adapted to be mounted facing each other, the first printed circuit being adapted to be mounted secured to an axle carrying the wheel, the second printed circuit being adapted to be mounted secured to the wheel, the first printed circuit comprising first tracks defining at least one transmitter winding and at least one measurement winding, the second printed circuit comprising second tracks defining at least one receiver winding and at least one target winding, and the electronic circuit being arranged to apply the excitation signal to the transmitter winding and to acquire the measurement signal from the measurement winding.
14. An aircraft braking system comprising a wheel fitted with a brake and with a device according to claim 13.
15. An aircraft including a braking system according to claim 14.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0040] Reference is made to the accompanying drawings, in which:
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DETAILED DESCRIPTION OF THE INVENTION
[0053] In this example, the invention is implemented in the braking system of an aircraft. The aircraft has undercarriages, each of which includes a plurality of so-called “braked” wheels.
[0054] The speed of each braked wheel is measured by means of a tachometer similar to the tachometer shown in
[0055] The electronic unit 10 includes an electronic circuit card having mounted thereon the components that form the electronic circuit 12 of
[0056] The electronic circuit 12 includes a clock component 14, synthesizer components comprising a first synthesizer 15 for synthesizing frequencies and a second synthesizer 16 for synthesizing a signal, a first amplifier 17, a second amplifier 18, and a digital envelope detector 20.
[0057] The clock component 14 is a local oscillator.
[0058] The first amplifier 17 is a single-channel power amplifier. The second amplifier 18 is a six-channel small-signal amplifier of gain G.
[0059] The digital envelope detector 20 comprises an input filter 21, an analog-to-digital converter 22 having six channels, and a signal processor module 23. It should be observed that the input filter 21 is optional, since the intrinsic passband of the second amplifier 18 may suffice to maintain performance. The second amplifier 18 may be an inverting amplifier or anon-inverting amplifier, a differential amplifier, or an instrumentation amplifier.
[0060] The signal processor module 23 comprises one or more processor components that are adapted to execute instructions of a program for acting as a synchronous quadrature demodulator.
[0061] The program is stored in one or more memories connected to or incorporated in the processor component. By way of example, the processor component(s) may be a processor, a digital signal processor (DSP), a microcontroller, or indeed a programmable logic circuit such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).
[0062] The electronic circuit 12 is connected to the tachometer 24.
[0063] The first synthesizer 15 acquires a clock signal produced by the local oscillator 14, and from the clock signal it generates both a pilot frequency f.sub.P that is a multiple of the excitation frequency f.sub.0 and also a sampling frequency f.sub.S. The second synthesizer 15 acquires the pilot frequency f.sub.P, generates the excitation frequency f.sub.0 from the pilot frequency f.sub.P, and generates an excitation signal having the excitation frequency f.sub.0. In this example, the excitation signal is a sinewave signal and the excitation frequency f.sub.0 is equal to 1 MHz.
[0064] The excitation signal is amplified by the first amplifier 17, and is then applied as input to the tachometer 24, specifically to the transmitter winding 6 of the first printed circuit 1. The electronic circuit 12 then acquires measurement signals output by the tachometer 24.
[0065] The angular position θ of the second printed circuit 2, from which the angular position and the angular speed of the wheel 4 are determined, satisfies the following equation:
where A and B are respectively the voltage levels of the measurement signals Va and Vb output by the two active measurement windings 7 of the first printed circuit 1 in the angular sector in question, and where O is the angular spacing between the measurement windings 7. The voltage levels of the measurement signals Va and Vb are obtained by the digital envelope detector 20 that includes the synchronous quadrature demodulator.
[0066] Each measurement signal is applied as input to a respective channel of the second amplifier 18 and is amplified, and is then applied as input to the digital envelope detector 20 and is filtered by the input filter 21.
[0067] Each filtered measurement signal is then digitized by a respective one of the channels of the analog-to-digital converter 22, thereby producing sample points. The digitized measurement signal is applied as input to the synchronous quadrature demodulator, which generates an output signal. The angular position of the second printed circuit 2 is estimated from the output signals.
[0068] The sample points belong to successive observation windows of duration T, each including a certain number of sample points. The synchronous quadrature demodulator produces one output signal value for each observation window on the basis of the sample points in said observation window.
[0069]
[0070] In a first branch, the measurement signal v(t), made up of the above-mentioned sample points, is multiplied by a first reference signal of the form cos(ω0t), in order to obtain a first intermediate signal X, which is squared in order to obtain a first result signal Z1.
[0071] In a second branch, the measurement signal v(t) is multiplied by a second reference signal of the form sin(ω0t), in order to obtain a second intermediate signal Y, which is squared in order to obtain a second result signal Z2.
[0072] The first result signal Z1 and the second result signal Z2 are summed in order to obtain a sum signal Z, and a square root of the sum signal Z is calculated in order to obtain a value for the output signal S for each observation window.
[0073] The measurement signal v(t), at the input of the synchronous quadrature demodulator 25, is a signal of the form v(t)=ΣV.sub.n.Math.cos(nω0t+φ), where n is the order of the harmonic under consideration. The offset of the first intermediate signal X is zero, the fundamental of the first intermediate signal X is equal to 0.5.Math.cos(φ).Math.V.sub.1, and the harmonics of the first intermediate signal X are zero from order 2 (included). Likewise, The offset of the second intermediate signal Y is zero, the fundamental of the second intermediate signal Y is equal to −0.5.Math.sin(φ).Math.V.sub.1, and the harmonics of the second intermediate signal Y are zero from order 2 (included). The offset of the output signal S is zero, and the fundamental of the output signal S is equal to 0.5.Math.V.sub.1, and the harmonics of the output signal S are zero from order (included).
[0074] The input filter 21, located upstream from the analog-to-digital converter 22 (i.e. beside the input of the measurement signal), presents a frequency response that needs to be as flat as possible in the working band, so as to minimize the influence of component temperature drifts on the amplitude of the measurement signal that is transmitted after being digitized in the synchronous quadrature demodulator 25. By way of example, the input filter 21 may be a Butterworth filter.
[0075] Attention is now given more particularly to the sampling of the measurement signal.
[0076] The measurement signal is sampled at the sampling frequency f.sub.S, i.e. the operation of the analog-to-digital converter 22 is clocked at the sampling frequency f.sub.S.
[0077] In this example, the sampling is subsampling, i.e. the condition of Shannon's theorem is not satisfied. The subsampling is synchronous with the excitation frequency f.sub.0 of the excitation signal: the same oscillator is used to generate both the excitation frequency f.sub.0 and also the sampling frequency f.sub.S.
[0078] The sampling of all of the channels needed for measurement must be simultaneous or almost simultaneous relative to the passband of the physical phenomenon being observed (rotation of the wheel 4).
[0079] In this example, the analog-to-digital converter 22 comprises the same number of sample-and-hold circuits as there are output channels from the sensor (i.e. the number of measurement windings 7 of the first printed circuit 1, which is equal to six) together with a single converter block, which serves to maximize conversion performance.
[0080] The subsampling leads to spectrum folding, which is shown in
[0081] It can be seen that the apparent frequency f.sub.U of a signal sampled as a function of the sampling frequency is such that:
[0082] It is generally preferred to use a sampling frequency that is high relative to the frequency of the measurement signal in order to avoid spectrum folding.
[0083] Nevertheless, as mentioned above, in order to be effective, conventional digital demodulators require a sampling frequency that is much higher than the frequency of the measurement signal. Thus, for high accuracy applications, it is generally considered that at least 32 sample points are needed within one period of the measurement signal in order to achieve sufficient effectiveness. For a 1 MHz signal, that would lead to a sampling frequency 32 MHz. Such a sampling frequency also makes it possible to eliminate harmonics up to order 8, but the associated electronics is then expensive to make since it requires analog-to-digital converters that are fast together with processor capacity that is considerable.
[0084] As used herein, subsampling that is synchronous with the generation of the excitation signal serves to mitigate this drawback.
[0085] Each measurement signal is sampled at the sampling frequency during successive observation windows. Each observation window has a duration T and contains a number of samples N.sub.S. The samples are spaced apart at a sampling period T.sub.S. In this example, the sampling period T.sub.S (T.sub.S=1/f.sub.S) and the duration T are such that:
where T.sub.0 is the excitation period of the excitation signal (T.sub.0=1/f.sub.0), where N.sub.P, N.sub.T, and N.sub.S are non-zero natural integers, and where N.sub.T is not a multiple of N.sub.S. N.sub.T represents a scale factor.
[0086] In this example, each sampling point is thus shifted by an integer number N.sub.P of periods of the excitation signal plus a fraction thereof, with periodicity N.sub.S corresponding to the number of points defined for integration over each observation window of duration T.
[0087] From this approach, it follows that:
T'P.Math.T.sub.0,
where P is a non-zero natural integer such that:
P=N.sub.S.Math.N.sub.P.Math.+N.sub.T.
[0088] Thus giving:
[0089] It is thus possible to calculate possible values for N.sub.P and for N.sub.T:
[0090] The values of N.sub.S imply that N.sub.T of zero value or multiples of N.sub.S are excluded. Specifically, they correspond to a folding frequency of zero.
[0091] The output signal S from the singular quadrature demodulator, having a value that is calculated for each observation window of duration T, is such that:
[0092] In this formula, i is the index of the sample points,
represents time in the observation window and, as mentioned above, N.sub.S is the number of sample points per observation window. The instant 0 is taken as being the instant of the first sample among the N.sub.S samples in the observation window.
[0093] Attention is now given more particularly to the way in which the value of N.sub.S is defined.
[0094] The duration T of the observation window is defined first. This duration depends on the application in which the invention is implemented and, more particularly, on the refresh time of the measurement parameter that is required in the application.
[0095] In this example, operation of the antiskid loop is based on providing new speed data once every 400 microseconds (μs). The duration T of the observation window needs to be synchronized with the supply of speed data, and the duration T must therefore be equal to no more than 400 μs. If the duration T is selected to be less than 400 μs, it should preferably be a sub-multiple of 400 μs in order to the coherent with the rate of measurement.
[0096] In this example, the duration T is selected to be equal to 400 μs.
[0097] Since the excitation frequency f.sub.0 is equal to 1 MHz, this gives:
P=400.
[0098] The number of sample points N.sub.S is defined so as to maximize elimination of harmonics of the excitation frequency f.sub.0 and so as to maximize noise reduction in the digital envelope detector 20, while conserving a processing time for each sample point that is acceptable, given the performance of the analog-to-digital converter 22 and of the processor module 23.
[0099] Thus, the design of the electronic circuit 12 comprises the steps of: [0100] defining an optimized value for the number of sample points Ns, said the optimized value maximizing elimination of harmonics of the excitation frequency f.sub.0 and maximizing noise reduction in the digital envelope detector 20, while conserving a processing time that is allocated to each sample point that is acceptable given the performance of the analog-to-digital converter 22 and given the processor component(s) 23; and [0101] configuring the electronic circuit by comparing said optimized value to the number of sample points Ns.
[0102] Attention is given initially to filtering the harmonics.
[0103] The table of
[0104] For each value of N.sub.S, the table also gives the associated sampling frequency and the order of the harmonics (included) up to which the value of N.sub.S enables the measurement signal to be filtered.
[0105]
[0106] Appropriately selecting Ns (i.e. the optimized value of Ns) enables the spectrum folding problem to be handled and can lead to selecting sampling frequencies that are not obvious a priori. Certain values of N.sub.S give N.sub.T=1 and make it possible to produce sampling points such that the first intermediate signal X of the first branch of the synchronous quadrature demodulator 25 and the second intermediate signal Y of the second branch (sine channel) comprise sample points that follow one another in time in such a manner as to form two sinewaves in quadrature.
[0107] For example, the sample points of the two reference sine waves in quadrature cos(ω0t) and sin(ω0t) are shown in
[0108] The sample points of the two reference sinewaves in quadrature cos(ω0t) and sin(ω0t) are shown in
[0109] For the other values, the two reference sinewaves in quadrature comprise sample points that do indeed take their values on a sinewave but that do not follow one another in such a manner as to form two sinewave signals in quadrature and that appear to follow one another randomly.
[0110] The sample points of the two reference sinewaves in quadrature cos(ω0t) and sin(ω0t) are shown in
[0111] The sample points of the two reference sinewaves in quadrature cos(ω0t) and sin(ω0t) are shown in
[0112] Attention is now given to measurement accuracy and to noise in the digital envelope detector 20.
[0113] Attention is given initially to the error associated with thermal noise in the acquisition system. This is error of random type.
[0114] At the output from the synchronous quadrature demodulator 25 there is a useful component relating to the amplitude of the fundamental:
S=0.5.Math.V.sub.1, and
a noise component of root mean square (rms) value:
there follows a half-normal relationship; with
σ.sub.E=√{square root over (ENB.sub.E)}.Math.N.sub.E;
where N.sub.E is the noise spectral density expressed in volts per root hertz (V/Hz.sup.1/2) and ENB.sub.E is the effective noise bandwidth satisfying the definition:
[0115] When considering a tachometer application, this gives rise to the following angle measurement error:
where M is the level of the signal that is obtained at the output from the detector when the measurement winding 7 in question of the first printed circuit 1 (stator) is in alignment with the target winding 9 of the second printed circuit 2 (rotor).
[0116] For the tachometer configuration shown in
[0117] Attention is now given to the error associated with quantization noise. This is error of pseudo-random type.
[0118] Assuming infinite resolution for the reference sinewave, introducing quantization (on N code bits together with a sign bit) of the useful signal is represented as follows in the calculation of S:
[0119]
[0120] As expected theoretically, the rms value of the noise is established approximately as follows:
[0121] The rms value of the noise is independent of the amplitude of the useful signal, and is equal to about 24.Math.10.sup.−6 FS rms for N.sub.S=33 and an analog-to-digital converter operating on 11 code bits plus a sign bit (±FS).
[0122] When considering a tachometer application, this gives rise to the following angle measurement error:
where M is expressed in FS units.
[0123] For the tachometer configuration shown in
[0124] Attention is now given to the error associated with inaccuracy in the components of the acquisition system.
[0125] This error is of deterministic type and is proportional to the useful signal.
[0126] Differentiating the expression for the angle θ enables the position error dθ to be associated with the relative measurement errors at the output from the detector
dθ is at a maximum for θ=0° and
and it then takes the value:
[0127] The value O=40° leads to relative measurement accuracy for A and B that is better than 5.Math.10.sup.−4 for complying with the required performance of 0.01°.
[0128] Deterministic measurement error is associated mainly with unbalanced gain for the two amplifiers used for measuring A and B. This error depends on the type of amplifier used: an inverting amplifier, a non-inverting amplifier, and instrumentation amplifier, etc.
[0129] It is possible to reduce the error by having accurately controlled resistances in the two channels used for the radiometric measurement. It is therefore advantageous to make use of resistors forming part of a resistor network.
[0130] The deterministic measurement error is also associated with the input filter that is used. The measurement error depends in particular on the order of the filter.
[0131] The input filter comprises resistors and capacitors. Once again, it is advantageous to make use of resistors belonging to a resistor network and capacitors belonging to a capacitor network. Since the dispersion between components is greater for a capacitor network than for a resistor network, it is advantageous to arrange the above-described solution in such a manner as to push the cut-off frequency of the filter well above the working frequency f.sub.0, or even so as to eliminate the filter, while having recourse solely to the intrinsic passband of the acquisition system (the amplifier 18 plus the analog-to-digital converter 22).
[0132] It is therefore logically preferable to select Ns to be as high as possible in order to reduce noise in the digital envelope detector 20 and in order to improve the accuracy of the measurements. It is also advantageous to select a value for N.sub.S that gives a local minimum in the quantization noise, as shown in
[0133] Nevertheless, the higher N.sub.S, the shorter the amount of processor time that can be allocated to each sample point.
[0134] For example, for N.sub.S=33, the electronic circuit 12 has 12 μs (N.sub.P=12 and f.sub.0=1 MHz) for acquiring the six channels of the tachometer, and also for performing the two multiply-accumulate operations performed in the synchronous quadrature demodulator 25 and required for each of the channels (i.e. about 1 μs for each multiplication-accumulation). For N.sub.S=57, the electronic circuit has only 7 μs for performing acquisition and signal processing (i.e. about 500 ns for each multiplication-accumulation).
[0135] The value of N.sub.S that is selected is thus the result of a compromise serving both to maximize the elimination of harmonics of the excitation frequency and also to reduce noise in the digital envelope detector 20, but without that excessively reducing the processing time allocated to each sample point.
[0136] There are several technical solutions for implementing the synchronous quadrature demodulator 25.
[0137] By way of example, the processor module 23 may include both an FPGA that carries out the multiplication-accumulation operations performed in the synchronous quadrature demodulator 25, and also a microprocessor for carrying out the other operations performed in the synchronous quadrature demodulator 25 (and in particular for the final calculation). It is also possible to use a single microcontroller or microprocessor (with greater computation resources) for carrying out all of the operations performed in the synchronous quadrature demodulator 25.
[0138] At present, it is the second option that is easier to certify for application to a tachometer used in the antiskid function of an aircraft braking system.
[0139] In a configuration where N.sub.S=33, T=400 μs, and f.sub.0=1 MHz, the data rate between the analog-to-digital converter 21 and the processor module 23 is 6 times 16 bits, i.e. 96 bits, for transferring every 12 μs, which gives an average data rate of 8 megabits per second (Mbps), which is accessible for a serial peripheral interface (SPI) bus.
[0140] The sampling rate then becomes 82.5 thousand samples per second (ksps), which remains within the capabilities of many multichannel analog-to-digital converters with simultaneous sampling. The essential constraint remains the small signal passband, which is desired to be greater than 10 MHz. Assuming a maximum data rate of 20 Mbps on an SPI bus, the maximum possible number of samples N.sub.S is 79.
[0141] Naturally, the invention is not limited to the embodiment described, but covers any variant coming within the ambit of the invention as defined by the claims.
[0142] The above description relates to an excitation signal in the form of a sinewave, but that is naturally not essential. By way of example, the excitation signal could be a squarewave signal, which would require smaller computation resources.
[0143] The electronic unit is not necessarily connected to a single tachometer. By way of example, it is possible to have an architecture in which each undercarriage that has braked wheels includes one or two WRDCs connected to the tachometers of all of the wheels of said undercarriage.
[0144] Naturally, the sensor use is not necessarily a tachometer. The invention can be performed with any type of variable-excitation sensor, as for example with a rotary variable differential transformer (RVDT), with a resolver, with a proximity sensor, etc.