Gate driving circuit and display apparatus having the same

Abstract

A liquid crystal display apparatus including a gate driving circuit disposed on a liquid crystal display is provided. The apparatus further includes a data driving chip, disposed on the liquid crystal display panel, to apply data driving signals to data lines. The gate driving circuit includes a plurality of stages connected to one another in parallel. The odd-numbered stages of the stages each apply gate driving signals to odd-numbered gate lines of the gate lines, in response to a first clock signal and the even-numbered stages of the stages each apply the gate driving signals to even-numbered gate lines of the gate lines, in response to a second clock signal having an opposite phase from a phase of the first clock signal.

Claims

1. A display apparatus comprising: a first display panel including a plurality of first gate lines and a plurality of first data lines; a first gate driving circuit configured to supply first gate signals to the plurality of first gate lines; a second display panel including a plurality of second gate lines and a plurality of second data lines; a second gate driving circuit configured to supply second gate signals to the plurality of second gate lines; and a data driving circuit configured to supply first data signals to the plurality of first data lines and to supply second data signals to the plurality of second data lines wherein first signals and first voltages are supplied to the first gate driving circuit through the data driving circuit, and wherein the data driving circuit includes: a plurality of first terminals electrically connected to the plurality of first data lines; and a plurality of second terminals electrically connected to the first gate driving circuit.

2. The display apparatus of claim 1, wherein the plurality of first terminals are disposed adjacent to the first display panel and the plurality of second terminals.

3. The display apparatus of claim 2, wherein the plurality of first terminals are disposed directly between a plurality of pixels included in the first display panel and the plurality of second terminals.

4. The display apparatus of claim 1, wherein the plurality of first terminals and the plurality of second terminals are electrically isolated from each other.

5. The display apparatus of claim 1, wherein the data driving circuit supplies the first signals and the first voltages to the first gate driving circuit through the plurality of second terminals.

6. The display apparatus of claim 5, wherein the first signals include a first clock signal, a second clock signal and a start signal, and wherein the first voltages include a driving voltage and a ground voltage.

7. The display apparatus of claim 1, wherein second signals and second voltages are supplied to the second gate driving circuit through the data driving circuit.

8. The display apparatus of claim 7, wherein the data driving circuit further includes: a plurality of third terminals electrically connected to the second gate driving circuit.

9. The display apparatus of claim 1, wherein the plurality of first data lines and the plurality of second data lines are electrically connected to each other.

10. The display apparatus of claim 9, wherein the second data signals are transmitted from the data driving circuit to the plurality of second data lines through the plurality of first data lines.

11. The display apparatus of claim 1, wherein the first display panel includes a display area and a peripheral area located adjacent to the display area, and wherein the first gate driving circuit and the data driving circuit are located onto the peripheral area.

12. The display apparatus of claim 11, wherein the peripheral area comprises a first peripheral area where the first gate driving circuit is located and a second peripheral area where the data driving circuit is located, and wherein the second peripheral area is substantially perpendicular to the first peripheral area.

13. The display apparatus of claim 1, wherein the first gate driving circuit comprises a series of stages arranged along a first direction.

14. The display apparatus of claim 13, wherein a first stage and a last stage among the series of stages receive a start signal simultaneously.

15. The display apparatus of claim 13, wherein a first clock signal and a second clock signal reversed from the first clock signal are input from the data driving circuit to a first stage and a second stage among the series of stages, respectively.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The above and other advantages of the present invention will become readily apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:

(2) FIG. 1 is a schematic plan view showing an LCD apparatus according to an exemplary embodiment of the present invention;

(3) FIG. 2 is a circuit diagram of the gate driving circuit shown in FIG. 1;

(4) FIG. 3 is a timing diagram of the gate driving circuit shown in FIG. 2;

(5) FIG. 4 is a circuit diagram of each stage of the gate driving circuit shown in FIG. 2;

(6) FIG. 5 is a schematic plan view showing the data diving chip connected to the gate driving circuit shown in FIG. 1;

(7) FIG. 6 is a schematic plan view showing an organic electro-luminescent display device according to another exemplary embodiment of the present invention;

(8) FIG. 7 is a schematic plan view showing an LCD apparatus according to another exemplary embodiment of the present invention;

(9) FIG. 8 is a circuit diagram showing the first gate driving circuit shown in FIG. 7;

(10) FIG. 9 is a circuit diagram showing the second gate driving circuit shown in FIG. 7;

(11) FIG. 10 is a timing diagram of the first and second gate driving circuits shown in FIGS. 8 and 9, according to an exemplary embodiment of the present invention;

(12) FIG. 11 is a timing diagram of the first and second gate driving circuits shown in FIGS. 8 and 9, according to another exemplary embodiment of the present invention; and

(13) FIG. 12 is a schematic plan view showing an LCD apparatus with dual display screen according to further exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

(14) FIG. 1 is a schematic plan view showing an LCD apparatus according to an exemplary embodiment of the present invention. An LCD apparatus 500 includes an LCD panel 300, a gate driving circuit 350, a data driving chip 370 and a Flexible Printed Circuit Board (FPC) 400. The LCD panel 300 includes a first substrate 100, a second substrate 200 facing the first substrate 100 and a liquid crystal layer (not shown) interposed between the first and second substrates 100 and 200.

(15) The LCD panel 300 includes a display area DA to display an image and first to third peripheral areas PA.sub.1-PA.sub.3 adjacent to the display area DA. The display area DA includes pixel matrix having a plurality of gate line GL.sub.n arranged in a first direction D.sub.1, a plurality of data line DL.sub.m arranged in a second direction D.sub.2 substantially perpendicular to the first direction D.sub.1 and insulated from the gate line GL.sub.n, and a plurality of thin film transistors (TFT) 110 connected between the gate lines GL.sub.n and data lines DL.sub.m. In the exemplary embodiment, “n” and “m” are an integer identical to or greater than one. Each TFT 110 includes a gate electrode connected to each gate line GL, a source electrode (a first current electrode) connected to each data line DL and a drain electrode (or a second current electrode) connected to a liquid crystal capacitor Clc.

(16) The gate driving circuit 350 is disposed on the first peripheral area PA.sub.1 and outputs gate driving signals to the gate lines GL.sub.n. The data driving chip 370 is mounted onto the third peripheral area PA.sub.3 and outputs a data signal to the data lines DL.sub.m. The FPC 400 is further mounted on the third peripheral area PA.sub.3, in order to connect an external device (not shown) for driving the LCD panel 300 to the data driving chip 370. The FPC 400 provides a data signal, a data control signal and a gate control signal with the data driving chip 370. The data driving chip 370 outputs the data signal to the data lines DL.sub.m as well as provides the gate control signals to the gate driving circuit 350. In response to the gate control signal, the gate driving circuit 350 outputs the gate driving signals to the gate lines GL.sub.n.

(17) FIG. 2 is a circuit diagram showing the gate driving circuit shown in FIG. 1. The gate driving circuit 350 includes a shift register having a plurality of stages SRC.sub.1-SRC.sub.n+1 connected to one other in parallel. The stages include an N number of driving stages SRC.sub.1-SRC.sub.n and one dummy stage SRC.sub.n+1. Each of the stages SRC.sub.1 to SRC.sub.n+1 includes a clock signal terminal CK, a first output terminal GOUT, a second output terminal SOUT, an input terminal IN and a control terminal CT. In this case, N in an integer identical to or greater than one.

(18) First and second clock signals CK and CKB, having an opposite phase to each other, are alternatively applied to the clock signal terminals CK of the stages. For example, the first clock signal CK is applied to the odd-numbered stages SRC.sub.1, SRC.sub.3, . . . , SRC.sub.n+1 of the stages. The second clock signal CKB is applied to the even-numbered stages SRC.sub.2, SRC.sub.4, . . . , SRC.sub.n of the stages. In response to the first or second clock signal CK or CKB, the first output terminal GOUT outputs the first or second clock signal CK or CKB as a gate driving signal, which is applied to a corresponding one of the gate lines GL.sub.n, and the second output terminal SOUT outputs the first or second clock signal CK or CKB as a stage driving signal.

(19) The input terminal IN receives the stage driving signal output from the second output terminal SOUT of a previous stage, and the control terminal CT receives the stage driving signal output from the second output terminal SOUT of a next stage. The input terminal IN of the first driving stage SRC.sub.1 receives a start signal ST because there is no previous stage with respect to the first driving stage SRC.sub.1. Also, the control terminal CT of the dummy stage SRC.sub.n+1 receives the start signal ST because there is no next stage with respect to the dummy stage SRC.sub.n+1. Each of the stages SRC.sub.1 to SRC.sub.n+1 further includes a ground voltage terminal VSS and a driving voltage terminal VDD that receive a ground voltage and a driving voltage, respectively.

(20) FIG. 3 is a timing diagram of the gate driving circuit of FIG. 2. The first and second clock signals CK and CKB have the opposite phase to each other, for example, a high state or a low state. The first driving stage SRC.sub.1 is activated in response to the high state of the start signal ST, and outputs a first gate driving signal G_OUT.sub.1 of a high state through the first output terminal GOUT. Since a first gate line GL.sub.1 connected to the first output terminal GOUT, and the TFT 110 and liquid crystal capacitor Clc connected to the first gate line GL.sub.1 operate as a load, the first gate driving signal G_OUT.sub.1 is delayed.

(21) The first driving stage SRC.sub.1 outputs a first stage driving signal S_OUT.sub.1 of a high state through the second output terminal SOUT. The first stage driving signal S_OUT.sub.1 is outputted without delay because the load of the second output terminal SOUT of the first driving stage SRC.sub.1 is relatively small. The first stage driving signal S_OUT.sub.1 is provided to the input terminal IN of a second driving stage SRC.sub.2, so that the second driving stage SRC.sub.2 is operated regardless of the delay of the first gate driving signal G_OUT.sub.1.

(22) The second driving stage SRC.sub.2 outputs a second gate driving signal G_OUT.sub.2 of a high state and a second stage driving signal S_OUT.sub.2 of a high stage through a first output terminal GOUT and a second output terminal SOUT thereof, respectively. The second stage driving signal S_OUT.sub.2 is provided to the control terminal CT of the first driving stage SRC.sub.1 and to the input terminal IN of a third driving stage SRC.sub.3. Therefore, the first gate driving signal G_OUT.sub.1 and the first stage driving signal S_OUT.sub.1 respectively output from the first and second output terminals GOUT and SOUT of the first driving stage SRC.sub.1 are transitioned into a low state in response to the second stage driving signal S_OUT.sub.2.

(23) The third driving stage SRC.sub.3 outputs a third gate driving signal G_OUT.sub.3 and a third stage driving signal S_OUT.sub.3 having a high stage through first and second output terminals GOUT and SOUT, respectively, while the second gate driving signal G_OUT.sub.2 and second stage driving signal S_OUT.sub.2 output from the first and second output terminals GOUT and SOUT of the second driving stage SRC.sub.2 transition from a high stage to a low state. By repeatedly performing the foregoing operations, the gate driving signal in a high state is sequentially output from the driving stages SRC.sub.1 to SRC_O.sub.n.

(24) FIG. 4 is a circuit diagram showing each stage of FIG. 2. Each stage of the stages of the gate driving circuit 350 includes a first pull-up part 351, a second pull-up part 352, a first pull-down part 353, a second pull-down part 354, a pull-up driving part 355 and a pull-down driving part 356.

(25) The first pull-up part 351 transmits the first clock signal CK or the second clock signal CKB from the clock signal terminal CK to the first output terminal GOUT. The second pull-up part 352 transmits the first clock signal CK or the second clock signal CKB from the clock signal terminal CK to the second output terminal SOUT.

(26) The first pull-up part 351 includes a first NMOS transistor NT1 having a gate electrode connected to a first node N1, a source electrode connected to the clock signal terminal CK and a drain electrode connected to the first output terminal GOUT. The second pull-up part 352 includes a second NMOS transistor NT2 having a gate electrode connected to the gate electrode of the first NMOS transistor NT1, a source electrode connected to the clock signal terminal CK and a drain electrode connected to the second output terminal SOUT. The first and second NMOS transistors NT1 and NT2 each have a channel length of about 3.5 micrometers. The first NMOS transistor NT1 has a channel width of about 1110 micrometers and the second NMOS transistor NT2 has a channel width of about 100 micrometers. The channel width ratio of the first NMOS transistor NT1 to the second NMOS transistor NT2 is approximately 10:1.

(27) The first pull-down part 353 is activated in response to the inactivation of the first pull-up part 351, and discharges the first clock signal CK or second clock signal CKB output from the first output terminal GOUT. The second pull-down part 354 is activated in response to the inactivation of the second pull-up part 352, and discharges the first clock signal CK or second clock signal CKB output from the second output terminal SOUT.

(28) The first pull-down part 353 includes a third NMOS transistor NT3 having a gate electrode connected to a second node N2, a drain electrode connected to the first output terminal GOUT and a source electrode connected to the ground voltage terminal VSS. The second pull-down part 354 includes a fourth NMOS transistor NT4 having a gate electrode connected to the gate electrode of the third NMOS transistor NT3, a drain electrode connected to the second output terminal SOUT and a source electrode connected to the ground voltage terminal VSS. The third and fourth NMOS transistors NT3 and NT4 each have a channel length of about 3.5 micrometers. The third NMOS transistor NT3 has a channel width of about 2035 micrometers and the fourth NMOS transistor NT4 has a channel width of about 100 micrometers, so that a channel width ratio of the third NMOS transistor T3 to the fourth NMOS transistor T4 is approximately 20:1.

(29) The pull-up driving part 355 includes fifth, sixth and seventh NMOS transistors NT5, NT6 and NT7 and activates the first and second pull-up parts 351 and 352. The fifth NMOS transistor NT5 includes a gate electrode connected to the input terminal IN, a drain electrode connected to the driving voltage terminal VDD and a source electrode connected to the first node N1. The sixth NMOS transistor NT6 includes gate and drain electrodes commonly connected to the driving voltage terminal VDD, and a source electrode connected to the third node N3. The seventh NMOS transistor NT7 includes a gate electrode connected to the first node N1, a drain electrode connected to the third node N3 and a source electrode connected to the ground voltage terminal VSS. The fifth, sixth and seventh NMOS transistors NT5, NT6 and NT7 each have a channel length of about 3.5 micrometers. The fifth NMOS transistor NT5 has a channel width of about 300 micrometers, and the sixth and seventh NMOS transistors NT6 and NT7 each have a channel width of about 50 micrometers.

(30) The pull-down driving part 356 includes eighth, ninth, tenth and eleventh NMOS transistors NT8, NT9, NT10 and NT11 and inactivates the first and second pull-up parts 351 and 352. Further, the pull-down driving part 356 activates the first and second pull-down part 353 and 354.

(31) The eighth NMOS transistor NT8 includes a gate electrode connected to a third node N3, a drain electrode connected to the driving voltage terminal VDD and a source electrode connected to the second node N2. The ninth NMOS transistor NT9 includes a gate electrode connected to the first node N1, a drain electrode connected to the second node N2 and a source electrode connected to the ground voltage terminal VSS. The tenth NMOS transistor NT10 includes a gate electrode connected to the second node N2, a drain electrode connected to the first node N1 and a source electrode connected to the ground voltage terminal VSS. The eleventh NMOS transistor NT11 includes a gate electrode connected to the control terminal CT, a drain electrode connected to the first node N1 and a source electrode connected to the ground voltage terminal VSS.

(32) The pull-down driving part 356 further includes a twelfth NMOS transistor NT12 includes a gate electrode connected to the input terminal IN, a drain electrode connected to the second node N2 and a source electrode connected to the ground voltage terminal VSS. The eighth, ninth, tenth, eleventh and twelfth NMOS transistors NT8, NT9, NT10, NT11 and NT12 have a channel length of about 3.5 micrometers. The eight and twelfth NMOS transistors NT8 and NT12 have a channel width of about 100 micrometers. The ninth, ten and eleventh NMOS transistors NT9, NT10 and NT11 have a channel width of about 150 micrometers, about 100 micrometers and about 150 micrometers, respectively.

(33) When the input terminal IN receives a stage driving signal from the second output terminal SOUT of a previous stage, the fifth NMOS transistor NT5 is activated to raise an electric potential at the first node N1. In response to the electric potential of a high level at the first node N1, the first and second NMOS transistors NT1 and NT2 are activated to output the gate driving signal and the stage driving signal via the first output terminal GOUT and the second output terminal SOUT, respectively. Further, the seventh NMOS transistor NT7 is activated in response to the electric potential of a high level at the first Node N1. Since the seventh NMOS transistor NT7 is activated and the sixth NMOS transistor NT6 maintains an activation state, an electric potential falls down at the third node N3.

(34) In response to the electric potential of a low level at the third note N3, the eighth NMOS transistor T8 is inactivated, and thus, the second node N2 does not receive the driving voltage VDD. The ninth NMOS transistor NT9 is activated in response to the electric potential of a high level at the first node N1 so that the electric potential at the second node N2 is maintained in the ground voltage VSS. In response to the electric potential of the second node N2 of a low level, the third and fourth NMOS transistors NT3 and NT4 are inactivated.

(35) When the control terminal CT receives the stage driving signal from the second output terminal SOUT of a next stage, the eleventh NMOS transistor T11 is activated to discharge the electric potential at the first node N1 to the ground voltage VSS. In response to the electric potential of a low level at the first note N1, the seventh and ninth NMOS transistors NT7 and NT9 are inactivated. Thus, the electric potential at the second node N2 is gradually raised in response to the activation of the eighth NMOS transistor NT8, and the third and fourth NMOS transistors NT3 and NT4 are activated to discharge the gate driving signal output from the first and second output terminals GOUT and SOUT to the ground voltage VSS. In response to the electric potential of a high level at the second node N2, the twelfth and tenth NMOS transistors NT12 and NT10 are activated so that the electric potential at the first node N1 is discharged rapidly. Thus, each stage may output the gate and stage driving signals, which maintain a high state during a predetermined period.

(36) FIG. 5 is a diagram showing the data driving chip 370 connected to the gate driving circuit 350. The data driving chip 370 includes a start signal input terminal STT to receive a start signal ST, a first clock signal input terminal CKT to receive a first clock signal CK, a second clock signal input terminal CKBT to receive a second clock signal CKB, a ground voltage input terminal VSST to receive a ground voltage VSS and a driving voltage input terminal VDDT to receive a driving voltage VDD.

(37) The start signal input terminal STT is electrically connected to the first driving stage SRC.sub.1 and dummy stage SRC.sub.n+1 of the gate driving circuit 350. The first clock signal input terminal CKT is electrically connected to the clock signal terminal CK of the odd numbered stages SRC.sub.1, SRC.sub.3, . . . , SRC.sub.n+1, and the second clock signal input terminal CKBT is electrically connected to the clock signal terminal CK of the even numbered stages SRC.sub.2, SRC.sub.4, . . . , SRC.sub.n. The ground voltage input terminal VSST is electrically connected to the ground voltage terminal VSS of the stages SRC.sub.1, . . . , SRC.sub.n+1. The driving voltage input terminal VDDT is electrically connected to the driving voltage terminal VDD of the stages SRC_O1, . . . , SRC_O.sub.n+1. Thus, the data driving chip 370 provides the start signal ST, the first and second clock signals CK and CKB, the ground voltage CSS and the driving voltage VDD with the gate driving circuit 350.

(38) FIG. 6 is a schematic plan view showing an organic electro-luminescent display apparatus, according to another exemplary embodiment of the present invention. An organic electro-luminescent (EL) display apparatus 700 includes an organic electro-luminescent display panel 600 having a first substrate 100, a second substrate 200 facing the first substrate 100 and an organic electro-luminescent device (EL) interposed between the first and second substrates 100 and 200.

(39) The organic electro-luminescent display panel 600 includes a display area DA for displaying an image and first and third peripheral areas PA.sub.1 to PA.sub.3 adjacent to the display area DA. The display area DA includes a plurality of pixels formed in a matrix configuration, an N number of gate lines GLs arranged in a first direction D.sub.1 and an M number of data lines DL arranged in a second direction D.sub.2 substantially perpendicular to the first direction D.sub.1 and insulated from the gate lines GLs. In this exemplary embodiment, “N” and “M” are an integer identical to greater than one.

(40) Each of the pixels is defined by the gate line GL, the data line DL and a power supply line PSL, and includes a switching transistor 110, a driving transistor 120, an organic electro-luminescent device (EL). The switching transistor 110 includes a source electrode connected to the data line DL, a gate electrode connected to the gate line GL and a drain electrode connected to both a liquid crystal capacitor Clc and the gate electrode of the driving transistor 120. The driving transistor 120 includes a source electrode electrically connected to the power supply line PSL, a drain electrode connected to the organic electro-luminescent device (EL) and a gate electrode connected to the drain electrode of the switching transistor 110. The liquid crystal capacitor Clc is electrically connected between the drain electrode of the switching transistor 110 and the source electrode of the driving transistor 120. The organic electro-luminescent device (EL) includes a grounded cathode electrode and an anode electrode connected to the drain electrode of the driving transistor 120 so as to receive the driving current provided from the power supply line PSL. The power supply line PSL receives a direct current signal from an external power supply device (not shown).

(41) A gate driving circuit 350 is disposed onto the first peripheral area PA.sub.1 to sequentially output gate driving signals to the gate lines GL. A data driving chip 370 is mounted onto the third peripheral area PA.sub.3 to output a data signal to the data lines DL. An external device (not shown) for driving the LCD panel 300 and a Flexible Printed Circuit board (FPC) 400 for electrically connecting the external device to the LCD panel 300 may be further mounted onto the third peripheral area PA.sub.3. The FPC 400 is electrically connected to the data driving chip 370 to output a data signal, a data control signal and a gate control signal. Thus, the gate control signal is applied to the gate driving circuit 350 through the data driving chip 370.

(42) The gate driving circuit 350, as described above, includes a plurality of stages. Each stage includes a clock signal terminal to receive a clock signal, a first output terminal to output the clock signal as a gate driving signal, a second output terminal to output the clock signal as a stage driving signal, an input terminal and a control terminal to receive the stage driving signal. Thus, in the gate driving circuit 350, the stage driving signal is provided to the input and control terminals of the adjacent stages without distorting. Thus, the operational properties of the gate driving circuit 350 and the display properties of the display apparatus 700 are improved.

(43) FIG. 7 is a schematic plan view showing an LCD apparatus according to another exemplary embodiment of the present invention. The same reference numerals are used to refer the same or like parts those described in FIG. 1 and any further explanation is omitted.

(44) An LCD apparatus 800 includes an LCD panel 300, first and second gate driving circuits 350 and 360, a data driving chip 370 and a Flexible Printed Circuit board (FPC) 400. The LCD panel 300 includes a first substrate 100, a second substrate 200 facing the first substrate 100 and a liquid crystal layer (not shown) interposed between the first and second substrates 100 and 200.

(45) The first gate driving circuit 350 is disposed on the first peripheral area PA.sub.1 and outputs gate driving signals to the odd numbered gate lines of the gate lines GL.sub.2n−1. The second gate driving circuit 360 is disposed on the second peripheral area PA.sub.2, which is opposite the first peripheral area PA.sub.1, and outputs the gate driving signals to the even numbered gate lines of the gate lines GL.sub.2n. The data driving chip 370 is mounted onto the third peripheral area PA.sub.3 and outputs a data signal to the data lines DL.sub.m. On the third peripheral area PA.sub.3, the FPC 400 is further mounted. The FPC 400 electrically connects an external device (not shown) for driving the LCD panel 300 and the data driving chip 370. The data driving chip 370 outputs a data signal and first and second gate control signals to the data lines DL.sub.m and the first and second gate driving circuits 350 and 360 through the FPC 400. Therefore, the first and second gate driving circuits 350 and 360 apply the gate driving signals to the odd numbered and even numbered gate lines of the gate lines, respectively.

(46) FIG. 8 is a circuit diagram showing the first gate driving circuit shown in FIG. 7. The first gate driving circuit 350 includes a first shift register having a plurality of odd stages SRC_O.sub.1-SRC_O.sub.n+1 connected to one another in parallel. Each odd stage includes the same structure to that of the stage shown in FIG. 4. The odd stages include an N number of driving stages SRC_O.sub.1-SRC_O.sub.n and one dummy stage SRC_O.sub.n+1. Each of the odd stages SRC_O.sub.1 to SRC_O.sub.n+1 includes a clock signal terminal CK, a first output terminal GOUT, a second output terminal SOUT, an input terminal IN and a control terminal CT.

(47) First and second clock signals CK_O and CKB_O are alternatively applied to the clock signal terminals CK of the odd stages. For example, the first clock signal CK_O is applied to the odd-numbered stages SRC_O.sub.1, SRC_O.sub.3, . . . , SRC_O.sub.n+1 of the odd stages, and the second clock signal CKB_O is applied to the even-numbered stages SRC_O.sub.2, SRC_O.sub.4, . . . , SRC_O.sub.n of the odd stages.

(48) The first clock signal CK_O is outputted as a first gate driving signal through the first output terminal GOUT of the odd-numbered stages SRC_O.sub.1, SRC_O.sub.3, . . . , SRC_O.sub.n−1 of the driving stages, and the second clock signal CKB_O is outputted as the first gate driving signal through the first output terminal GOUT of the even-numbered stages SRC_O.sub.2, SRC_O.sub.4, . . . , SRC_O.sub.n of the driving stages. The first output terminal GOUT of the dummy stage SRC_O.sub.n+1 is maintained in a floating state because there is no gate line corresponding to the first output terminal GOUT of the dummy stage SRC_O.sub.n+1. The first output terminal GOUT of the odd stages SRC_O.sub.1 to SRC_O.sub.n is electrically connected to a corresponding one of the odd-numbered gate lines GL.sub.1, GL.sub.3, . . . , GL2.sub.n−1 formed at a display area DA. Therefore, the first gate driving signals output from the first output terminals GOUT of the odd stages SRC_O.sub.1 to SRC_O.sub.n are sequentially applied to the odd-numbered gate lines GL.sub.1, GL.sub.3, . . . , GL.sub.2n−1.

(49) The first clock signal CK_O is outputted as a first stage driving signal through the second output terminal SOUT of the odd-numbered stages SRC_O.sub.1, SRC_O.sub.3, . . . , SRC_O.sub.n+1 of the odd stages, and the second clock signal CKB_O is outputted as the first stage driving signal through the second output terminal SOUT of the even stages SRC_O.sub.2, SRC_O.sub.4, . . . , SRC_O.sub.n. The input terminal IN receives the first stage driving signal output from the second output terminal SOUT of a previous odd stage, and the control terminal CT receives the first stage driving signal output from the second output terminal SOUT of a next odd stage. The input terminal IN of the first driving stage SRC_O.sub.1 receives a first start signal ST because there is no previous odd stage with respect to the first driving stage SRC_O.sub.1. Also, the control terminal CT of the dummy stage SRC_O.sub.n+1 receives the first start signal ST because there is no next odd stage with respect to the dummy stage SRC_O.sub.n+1. Each of the odd stages SRC_O.sub.1 to SRC_O.sub.n+1 further includes a ground voltage terminal VSS and a driving voltage terminal VDD that receive a ground voltage and a driving voltage, respectively.

(50) Referring to FIG. 9, a second gate driving circuit 360 includes a second shift register having a plurality of even stages SRC_E.sub.1 to SRC_E.sub.n+1 connected to one another in parallel. The even stages SRC_E.sub.1 to SRC_E.sub.n+1 include a plurality of driving stages SRC_E.sub.1 to SRC_E.sub.n and one dummy stage SRC_E.sub.n+1. Each even stage includes the same structure to that of the stage shown in FIG. 4. Each of the even stages SRC_E.sub.1 to SRC_E.sub.n+1 includes a clock signal terminal CK, a first output terminal GOUT, a second output terminal SOUT, an input terminal IN and a control terminal CT.

(51) The clock signal terminal CK receives a third clock signal CK_E or a fourth clock signal CKB_E. For example, the clock signal terminal CK at the odd-numbered stages SRC_E.sub.1, SRC_E.sub.3, . . . , SRC_E.sub.n+1 of the even stages receives the third clock signal CK_E, and the clock signal terminal CK at the even-numbered stages SRC_E.sub.2, SRC_E.sub.4, . . . , SRC_E.sub.n of the even stages receives the fourth clock signal CKB_E.

(52) The third clock signal CK_E is outputted as a second gate driving signal through the first output terminal GOUT of the even-numbered stages SR_E.sub.1, SRC_E.sub.3, . . . , SRC_E.sub.n−1 of the driving stages, and the second clock signal CKB_E is outputted as the second gate driving signal through the first output terminal GOUT of the even-numbered stages SRC_E.sub.2, SRC_E.sub.4, . . . , SRC_E.sub.n of the driving stages. The first output terminal GOUT of the even stages SRC_E.sub.1 to SRC_E.sub.n is electrically connected to a corresponding one of the even-numbered gate lines GL.sub.2, GL.sub.4, . . . , GL.sub.2n formed at a display area DA. Therefore, the second gate driving signals output from the first output terminals GOUT of the even stages SRC_E.sub.1 to SRC_E.sub.n are sequentially applied to the even-numbered gate lines GL.sub.2, GL.sub.4, . . . , GL.sub.2n.

(53) The third clock signal CK_E is outputted as a second stage driving signal through the second output terminal SOUT of the even-numbered stages SRC_E.sub.1, SRC_E.sub.3, . . . , SRC_E.sub.n+1 of the even stages, and the fourth clock signal CKB_E is outputted as the second stage driving signal through the second output terminal SOUT of the even-numbered stages SRC_E.sub.2, SRC_E.sub.4, . . . , SRC_E.sub.n of the even stages. The second stage driving signal output from the second output terminal SOUT of a previous even stage is inputted to the input terminal IN, and the second stage driving signal output from the second output terminal SOUT of a next even stage is inputted to the control terminal CT. The input terminal IN of the first even stage SRC_E.sub.1 receives a second start signal ST_E because there is no previous even stage with respect to the first even stage SRC_E.sub.1. Also, the control terminal CT of the dummy stage SRC_E.sub.n+1 receives the second start signal ST_E since there is no next even stage with respect to the dummy stage SRC_E.sub.n+1.

(54) FIG. 10 is a timing diagram of the first and second gate driving circuits shown in FIGS. 8 and 9. The first, second, third and fourth clock signals CK_O, CKB_O, CK_E and CKB_E each have a high state or a low state during a predetermined period T such that only one clock signal of a high state exists during a quarter period ¼T. Therefore, each of the first, second, third and fourth clock signals CK_O, CKB_O, CK_E and CKB_E has a high state during a first quarter period ¼T and a low state during the last periods, that is, three quarter period ¾T. In order to that only one clock signal has a high state during one quarter period ¼T, the second to third clock signals CKB_O, CK_E and CKB_E are delayed with respect to the first clock signal CK_O. Particularly, the second clock signal CKB_O is delayed by a half period ½T with respect to the first clock signal CK_O, the third clock signal CK_E is delayed by a quarter period ¼T with respect to the first clock signal CK_O, and the fourth clock signal CKB_E is delayed by a three quarter period ¾T with respect to the first clock signal CK_O.

(55) In response to the transition of a first start signal ST_O from a high state to a low state, a first odd stage SRC_O.sub.1 outputs the first clock signal CK_O of a high state as a first gate driving signal, which is applied to a first gate line GL.sub.1. The second start signal ST_E is delayed by a quarter period ¼T with respect to the first start signal ST_O, but is ahead by a quarter period ¼T with respect to the third clock signal CK_E. When the second start signal ST_E is transitioned from a high state to a low state, a first even stage SRC_E.sub.1 outputs the third clock signal CK_E of a high state as a second gate driving signal, which is applied to a second gate line GL.sub.2. Thus, the second gate driving signal is applied to the even-numbered gate line GL.sub.2, after the first gate driving signal applied to the odd-numbered gate line GL.sub.1 is transitioned from a high state to a low state.

(56) When the second clock signal CKB_O of a high state is applied to the first gate driving circuit 350 in response to the transition of the first clock signal CK_O from a high state to a low state, a second odd stage SRC_O.sub.2 outputs the second clock signal CKB_O of a high state as the first gate driving signal in response to the first stage driving signal output from the first odd stage SRC_O.sub.1. The first gate driving signal output from the second odd stage SRC_O.sub.2 is applied to a third gate line GL.sub.3. Since the second odd stage SRC_O.sub.2 outputs the first gate driving signal after the first gate driving signal output from the first odd stage SRC_O.sub.1 is transitioned from a high state to a low state, a first blank interval BL.sub.1 exists after the first odd stage SRC_O.sub.1 outputs the first gate driving signal of a high state and before the second odd stage SRC_O.sub.2 outputs the first gate driving signal of a high state.

(57) When the fourth clock signal CKB_E of a high state is applied to a second even stage SRC_E.sub.2 after the third clock signal CK_E is transitioned from a high state to a low state, the second even stage SRC_E.sub.2 outputs the fourth clock signal CKB_E of a high state as the second gate driving signal in response to the second stage driving signal output from the first even stage SRC_E.sub.1. The second gate driving signal output from the second even stage SRC_E.sub.2 is applied to the fourth gate line GL.sub.4. Since the second even stage SRC_E.sub.2 outputs the second gate driving signal after the first gate driving signal output from the second odd stage SRC_O.sub.2 is transitioned from a high state to a low state, a second blank interval BL.sub.2 exists after the first even stage SRC_E.sub.1 outputs the second gate driving signal having a high state and before the second even stage SRC_E.sub.2 outputs the second gate driving signal having a high state. Thus, the N number of odd stages SRC_O.sub.1 to SRC_O.sub.n and the N number of even stages SRC_E.sub.1 to SRC_E.sub.n are alternately activated to output the first and second gate driving signals, which are alternatively applied to the gate lines GL.sub.1 to GL.sub.2n.

(58) FIG. 11 is a timing diagram of the first and second gate driving circuits according to another exemplary embodiment of the present invention. The first to fourth clock signals CK_O, CKB_O, CK_E and CKB_E each have a high state or a low state during a predetermined period T. For example, the clock signals each have a high state during a first half period ½T and a low state during the last half period ½T. The second clock signal CKB_O is delayed by a half period ½T with respect to the first clock signal CK_O, and thus the first and second clock signals CK_O and CKB_O have the opposite phase to each other during the predetermined period T. The third clock signal CK_E is delayed by a quarter period ¼T with respect to the first clock signal CK_O and the fourth clock signal CKB_E is delayed by a half period ½T with regard to the third clock signal CK_E. Thus, the third and fourth clock signals CK_E and CKB_E have the opposite phase to each other during the predetermined period T.

(59) A first start signal ST_O has a high state during a half period ½T and is transitioned from a high state to a low state before the first clock signal CK_O of a high state is applied to a first odd stage SRC_O.sub.1. The first odd stage SRC_O.sub.1 outputs the first clock signal CK_O having a high state as a first gate driving signal, which is applied to a first gate line GL.sub.1. When the second clock signal CKB_O is applied to a second odd stage SRC_O.sub.2 after the first clock signal CK_O is transitioned from a high state to a low state, the second odd stage SRC_O.sub.2 outputs the second clock signal CKB_O of the high state as the first gate driving signal, in response to the first stage driving signal output from the first odd stage SRC_O.sub.1, which is applied to a third gate line GL.sub.3.

(60) A second start signal ST_E is delayed by a quarter period ¼T with the first start signal ST_O and has a high state during a half period ½T. When the second start signal ST_E is transitioned from a high state to a low state, a first even stage SRC_E.sub.1 outputs the third clock signal CK_E of a high state as a second gate driving signal, which is applied to a second gate line GL.sub.2. When the fourth clock signal CKB_E of a high state is applied to a second even stage SRC_E.sub.2 after the third clock signal CK_E is transitioned from a high state to a low state, the second even stage SRC_E.sub.2 outputs the fourth clock signal CKB_E of a high state as the second gate driving signal in response to a second stage driving signal output from the first even stage SRC_E.sub.1. The second gate driving signal output from the second even stage SRC_E.sub.2 is applied to a fourth gate line GL.sub.4.

(61) As shown in FIG. 11, the first gate driving signal output from the first or second odd stage SRC_O.sub.1 or SRC_O.sub.2 has a first dummy interval D.sub.1 during a quarter period ¼T and a first active interval A.sub.1 following the first dummy interval D.sub.1 during a quarter period ¼T. The second gate driving signal output from the first or second even stage SRC_E.sub.1 or SRC_E.sub.2 has also a second dummy interval D.sub.2 during a quarter period ¼T and a second active interval A.sub.2 following the second dummy interval D.sub.2 during a quarter period ¼T. Since the second gate driving signal applied to the second gate line GL.sub.2 is delayed by a quarter period ¼T with respect to the first gate driving signal applied to the first gate line GL.sub.1, the active interval A.sub.1 of the first gate driving signal applied to the first gate line GL.sub.1 is overlapped with the dummy interval D.sub.2 of the second gate driving signal applied to the second gate line GL.sub.2. Further, the first gate driving signal applied to the third gate line GL.sub.3 is delayed by a quarter period ¼T with respect to the second driving signal applied to the second gate line GL.sub.2, and thus, the active interval A.sub.2 of the second gate driving signal applied to the second gate line GL.sub.2 is overlapped with the dummy interval D.sub.1 of the first gate driving signal applied to the third gate line GL.sub.3.

(62) The driving chip 370 outputs a data driving signal during the first or second active period A.sub.1 or A.sub.2. For example, the driving chip 370 outputs a first data driving signal DATA1 at the first active interval A.sub.1 of the first gate driving signal applied to the first gate line GL.sub.1 and outputs a second data driving signal DATA2 at the second active interval A.sub.2 of the second gate driving signal applied to the second gate line GL.sub.2. Thus, the gate lines GL.sub.1 to GL.sub.2n alternately receive the first and second gate driving signals.

(63) Since the first gate driving circuit 350 outputting the first gate driving signal to the odd gate lines and the second gate driving circuit 360 outputting the second gate driving signal to the even gate lines are independently operated, the first and second gate driving circuits 350 and 360 are not subordinately connected to each other. Thus, the LCD apparatus 800 prevents the first and second gate driving signals from distorting due to a line resistance of the gate lines. Therefore, the LCD apparatus 800 improves its operational properties. Further, since the first and second gate driving circuits 350 and 360 are disposed on the LCD panel such that the LCD panel has a symmetric structure and the LCD panel is formed with a single chip, the LCD apparatus 800 has a reduced BM width and improved display property.

(64) FIG. 12 is a plan view showing an LCD apparatus with dual display screen according to further exemplary embodiment of the present invention. The same reference numerals are used to refer the same or like parts those described in FIG. 1 and any further explanation is omitted. An LCD apparatus with a dual display screen 1000 includes a first LCD panel 300, a second LCD panel 900, a driving chip 370, a first FPC 400 and a second FPC 450.

(65) The first LCD panel 300 includes a first display area DA.sub.1 for displaying a first image and first, second, third and fourth peripheral areas PA.sub.1, PA.sub.2, PA.sub.3 and PA.sub.4 surrounding the first display area DAL The first LCD panel 300 includes a 2N number of first gate lines GL.sub.1-1 to GL.sub.1-2n and an M number of first data lines DL.sub.1-1 to DL.sub.1-m substantially perpendicular to the first gate lines GL.sub.1-1 to GL.sub.1-2n, at the first display area DA.sub.1.

(66) A first gate driving circuit 350 is formed on the first peripheral area PA.sub.1 and a second gate driving circuit 360 is formed on the second peripheral area PA.sub.2. The first gate driving circuit 350 outputs first gate driving signals to odd-numbered gate lines of the first gate lines GL.sub.1-1 to GL.sub.1-2n−1, and the second gate driving circuit 360 outputs second gate driving signals to even-numbered gate lines of the first gate lines GL.sub.1-1 to GL.sub.1-2n.

(67) The driving chip 370 is mounted on the third peripheral area PA.sub.3, to which the first FPC 400 is attached. The first FPC 400 is electrically connected to the driving chip 370 to apply external signals to the driving chip 370. The driving chip 370 outputs the first data signal to the first data lines DL.sub.1-1 to DL.sub.1-m, and outputs first and second gate control signals to the first and second gate driving circuits 350 and 360, respectively. In response to the first and second gate control signals, the first and second gate driving circuits 350 and 360 output first and second gate driving signals to the first gate lines GL.sub.1-1 to GL.sub.1-2n.

(68) The second LCD panel 900 includes a second display area DA.sub.2 for displaying a second image, and fifth and sixth peripheral areas PA.sub.5 and PA.sub.6 adjacent to the second display area DA.sub.2. On the sixth peripheral area PA.sub.6, a third gate driving circuit 910 is formed. The second LCD panel 900 includes a I number of second gate lines GL.sub.2-1 to GL.sub.2-i and a J number of second data line DL.sub.2-1 to DL.sub.2-j substantially perpendicular to the second gate lines GL.sub.2-1 to GL.sub.2-1, at the second display area DA.sub.2. The driving chip 370 outputs the second data signal to the second LCD panel 900 and a third gate control signal to the third gate driving circuit 910. The third gate driving circuit 910 sequentially outputs a third gate driving signal to the second gate lines GL.sub.2-1 to GL.sub.2-i in response to the third gate control signal. The data signal is applied to second data lines DL.sub.2-1 to DL.sub.2-j, and the third gate driving signal is applied to the second gate lines GL.sub.2-1 to GL.sub.2-i. The “I” and “N” are an integer identical to or greater than two, and the “I” is equal to or less than the “N”. Also, the “J” and “M” are an integer identical to or greater than two, and the “J” is equal to or less than the “M”.

(69) The first and second LCD panels 300 and 900 are electrically connected to each other by means of the second FPC 450. The second FPC 450 includes a first end portion attached to the fourth peripheral area PA.sub.4 of the first LCD panel 300 and a second end portion attached to the fifth peripheral area PA.sub.5 of the second LCD panel 900. Thus, although the first driving chip 400 is mounted onto the first peripheral area PA.sub.1, the driving chip 370 is electrically connected to the second LCD panel 900 by means of the second FPC 450. One end of the first data lines DL.sub.1-1 to DL.sub.1-j is electrically connected to the second data line DL.sub.2-1 to DL.sub.2-j via a connection line CL.sub.1-1 to CL.sub.1-j formed at the second FPC 450. Thus, the second data signal output from the driving chip 370 is applied to the second data line DL.sub.2-1 to DL.sub.2-j via the connection line CL.sub.1-1 to CL.sub.1-j.

(70) Although FIG. 12 shows an LCD apparatus in which two gate driving circuits 350 and 360 are connected to the first LCD panel 300, the LCD apparatus may include one gate driving circuit to output gate driving signals to the first gate lines of the first LCD panel 300.

(71) Although the exemplary embodiments of the present invention have been described, it is understood that the present invention should not be limited to these exemplary embodiments but various changes and modifications can be made by one ordinary skilled in the art within the spirit and scope of the present invention as hereinafter claimed.