Event-based vision sensor

Abstract

According to the present invention there is provided a vision sensor comprising, an array of pixels (101) comprising rows and columns of pixels, wherein each pixel has an address assigned thereto which represents the position of the pixel in the array, wherein each pixel in the array of pixels comprises a photodiode (103) which can receive light, and which can output current having an amplitude proportional to the intensity of the received light; a photoreceptor circuit (104) which is electronically connected to the photodiode, and which is configured to convert current which it receives from the photodiode into a voltage; a first storage capacitor (105), and at least a first switch which (106) is positioned between the first storage capacitor and an output of the photoreceptor circuit, wherein the first switch can be selectively closed to electronically connect the output of the photoreceptor circuit to the first storage capacitor, or selectively opened to electronically disconnect the output of the photoreceptor circuit from the first storage capacitor; and a circuit (102, 201) which is configured so that it can he selectively electronically connected to a pixel in the array, and to determine if the difference between the voltage output from the photoreceptor circuit and the voltage across the first storage capacitor is greater than a predefined threshold voltage, and to output the address of the pixel to a receiver only if the difference between the voltage output from the photoreceptor circuit and the voltage across the first storage capacitor is greater than a predefined threshold voltage. There is further provided a corresponding method of vision sensing using the vision sensor.

Claims

1. A vision sensor comprising, an array of pixels, wherein each pixel in the array comprises: a photodiode for receiving light, a photoreceptor circuit electronically connected to the photodiode, and a storage capacitor; and a circuit for determining if a difference between the voltage output from the photoreceptor circuit of each of the pixels and the voltage across the storage capacitor of each of the pixels is greater than a predefined threshold voltage, wherein the circuit comprises a plurality of column circuits, the number of column circuits corresponding to at least the number of columns of pixels in the array of pixels, wherein each column circuit comprises a comparator that is configured to determine if, in pixels of the corresponding column, the difference between the voltage output from the photoreceptor circuit and the voltage across the storage capacitor of those pixels, is greater than the predefined threshold voltage.

2. The vision sensor of claim 1, further comprising a switch positioned between the storage capacitor and an output of the photoreceptor circuit of each of the pixels.

3. The vision sensor of claim 1, wherein the circuit outputs addresses of the pixels based the difference between the voltage output from the photoreceptor circuit of the pixels and the voltage across the storage capacitor of the pixels.

4. The vision sensor according to claim 1, wherein the circuit outputs an indication of the voltage output from the photoreceptor circuit.

5. The vision sensor according to claim 1, wherein said circuit comprises, a row selection circuit configured so that it can selectively connect all of the pixels in a row to a respective column circuit so that all of the pixels in the row are simultaneously connected to said plurality of column circuits, so that for each of the pixels in the row, the difference between the voltage output from the photoreceptor circuit and the voltage across the storage capacitor of each of those pixels, can be determined.

6. The vision sensor according to claim 1, wherein the circuit comprises a read-out circuit for transmitting the address of a pixel to the receiver if the difference between the voltage output from the photoreceptor circuit and the voltage across the storage capacitor is greater than the predefined threshold voltage.

7. The vision sensor according to claim 1, wherein the circuit transmits addresses of the pixels in which differences between a voltage output from the photoreceptor circuit and a voltage across the storage capacitor was greater than the predefined threshold voltage.

8. The vision sensor according to claim 1, wherein each of the pixels in the array further comprises a second storage capacitor.

9. The vision sensor according to claim 1, wherein each of the pixels in the array further comprises switches between the storage capacitors and the photoreceptor circuits.

10. A method for a vision sensor, the vision sensor comprising, an array of pixels, wherein each pixel in the array comprises: a photodiode for receiving light, a photoreceptor circuit electronically connected to the photodiode, and a storage capacitor; wherein the method comprises: a circuit determining if a difference between a voltage output from the photoreceptor circuit of each of the pixels and the voltage across the storage capacitor of each of the pixels is greater than a predefined threshold voltage, wherein the circuit comprises a plurality of column circuits, the number of column circuits corresponding to at least the number of columns of pixels in the array of pixels, wherein each column circuit comprises at least a comparator that is configured to determine if, in pixels of the corresponding column, the difference between the voltage output from the photoreceptor circuit and the voltage across the storage capacitor of those pixels, is greater than the predefined threshold voltage; and the circuit further outputting an indication of the voltage output from the photoreceptor circuit.

11. The method of claim 10, further comprising selectively connecting with a switch the storage capacitor and an output of the photoreceptor circuit of each of the pixels.

12. The method of claim 10, further comprising the circuit outputting addresses of the pixels based the difference between the voltage output from the photoreceptor circuit of the pixels and the voltage across the storage capacitor of the pixels.

13. The method of claim 10, further comprising the circuit determining if, in a pixel, the difference between the voltage output from the photoreceptor circuit and the voltage across the storage capacitor of that pixel, is greater than the predefined threshold voltage.

14. The method of claim 10, further comprising transmitting the address of a pixel to the receiver if the difference between the voltage output from the photoreceptor circuit and the voltage across the storage capacitor is greater than the predefined threshold voltage.

15. The method of claim 10, further comprising transmitting addresses of the pixels in which differences between a voltage output from the photoreceptor circuit and a voltage across the storage capacitor was greater than the predefined threshold voltage.

16. The method of claim 10, wherein each of the pixels in the array further comprises a second storage capacitor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention will be better understood with the aid of the description of an embodiment given by way of example and illustrated by the figures, in which:

(2) FIG. 1 shows an embodiment of the proposed vision sensor.

(3) FIG. 2 shows an alternative embodiment of the proposed vision sensor.

(4) FIG. 3 shows a further embodiment of the proposed vision sensor.

(5) FIG. 4 shows a pixel implementation for a vision sensor such as shown in FIG. 2a or FIG. 3a.

(6) FIG. 5 shows a pixel implementation with global shutter for a vision sensor such as shown in FIG. 2a or FIG. 3a.

(7) FIGS. 6 to 10 show different implementation of pixel front-end circuits.

(8) FIG. 11 shows a pixel circuit with more details about the pixel back-end implementation with respect to FIG. 4.

(9) FIG. 12 shows a pixel circuit with more details about the pixel back-end implementation with respect to FIG. 5.

(10) FIG. 13 shows an alternative pixel circuit with more details about the pixel back-end implementation with respect to FIG. 4.

(11) FIG. 14 shows the implementation of a row selection circuit.

(12) FIG. 15 shows the implementation of a column circuit and how it is connected to the pixels.

(13) FIG. 16 shows the implementation of an SC circuit, which is part of the column circuit.

(14) FIG. 17 shows a first implementation of an LC circuit, which is part of the column circuit.

(15) FIG. 18 shows a second implementation of an LC circuit, which is part of the: column circuit.

(16) FIG. 19 shows the implementation of a data readout circuit.

(17) FIG. 20 shows a token-based data readout circuit.

(18) FIG. 21 shows the state transition diagram for a control state machine.

(19) FIG. 22 shows the wave-forms of the control signals used to control the sensor.

DETAILED DESCRIPTION OF THE POSSIBLE EMBODIMENTS IN THE INVENTION

(20) An embodiment of the proposed sensor is illustrated in FIG. 1a; the vision sensor comprises: an array of pixels comprising rows and columns of pixels 101, wherein each pixel has an address assigned thereto which represents the position of the pixel in the array, wherein each pixel (illustrated in FIG. 1b) in the array of pixels comprises,

(21) a photodiode 103 which can receive light, and which can output current having an amplitude proportional to the intensity of the received light;

(22) a photoreceptor circuit 104 which is electronically connected to the photodiode, and which converts current which it receives from the photodiode into a voltage;

(23) a first storage capacitor 105,

(24) and at least a first switch 106 which is positioned between the first storage capacitor and an output of the photoreceptor circuit.

(25) The vision sensor further comprises at least one circuit 102 which is configured so that it can be selectively electronically connected to a pixel in the array, and to determine if the difference between the voltage output from the photoreceptor circuit (Vpr) and the voltage across the first storage capacitor (Vpr_last) is greater than a predefined threshold voltage, and to output the address of the pixel to a receiver only if the difference between Vpr and Vpr_last is greater than a predefined threshold voltage.

(26) In the following description, the term ‘event’ shall mean that the light intensity falling on a pixel has changed by an amount greater than or equal to a predefined threshold amount. To transmit an event, the address of the corresponding pixel is transmitted. This is then called an addressed event.

(27) The vision sensor may output an image if the Vpr voltages are converted to a digital value using an analog-to-digital converter (ADC) and then output to a receiver.

(28) There are Two Options:

(29) (1) a first option the digital values may be read out for all pixels, which would be like a conventional image sensor. Thus the proposed sensor would have the option to run in change detection mode or in image sensor mode.

(30) (2) the second option is to convert only the Vpr values of those pixels where an event has happened, and then transmit these values along with the address of the pixels. This would mean the sensor runs in video camera mode with on-sensor video compression.

(31) The vision sensor may comprise calibration circuits to improve image quality. One option of a calibration method is to subtract a reference frame.

(32) An alternative embodiment of the vision sensor according to the present invention is illustrated in FIG. 2a. The vision sensor of FIG. 2a comprises an array of pixels organized in row and columns, where each pixel 101 has a unique address that encodes the position of the pixel in the array, wherein each pixel 101, illustrated in FIG. 2b, in the array of pixels comprises, a photodiode which can receive light, and which can output current having an amplitude proportional to the intensity of the received light; a photoreceptor circuit which is electronically connected to the photodiode, and which converts current which it receives from the photodiode into a voltage; a first storage capacitor, and at least a first switch which is positioned between the first storage capacitor and an output of the photoreceptor circuit.

(33) The vision sensor of FIG. 2a further comprises a circuit 201 that is repeated for each column of pixels (this circuit shall be called column circuit) and shared between all pixels in one column. This column circuit can be selectively connected to a pixel in the corresponding column, and it is configured to be able to detect if the difference between Vpr and Vpr_last exceeds a predefined threshold (which means an event has happened in the currently selected pixel). The column circuit may also be able to operate the first switch 106 between the photoreceptor output and the storage capacitor. Optionally the column circuit can contain an analog-to-digital converter (ADC) to convert Vpr to a digital number.

(34) The vision sensor of FIG. 2a further comprises a circuit for selecting one or multiple rows 202, called row selection circuit, where selection means selectively connecting the pixels in this row to the corresponding column circuit.

(35) The vision sensor of FIG. 2a further comprises a circuit 203 for transmitting the addresses of those pixels where the difference between Vpr and Vpr_last exceeds a predefined threshold (and optionally the digital number representing Vpr) to some kind of receiver which can be external to the sensor chip. This circuit for transmitting data shall be called data readout circuit.

(36) Further Embodiment

(37) A further embodiment of a vision sensor according to the present invention is illustrated in FIG. 3a. The vision sensor of FIG. 3a comprises, an array of pixels organized in row and columns, where each pixel 101 has a unique address that encodes the position of the pixel in the array, wherein each pixel 101, illustrated in FIG. 3b, in the array of pixels comprises,

(38) a photodiode 103 which can receive light, and which can output current having an amplitude proportional to the intensity of the received light;

(39) a photoreceptor circuit 104 which is electronically connected to the photodiode, and which converts current which it receives from the photodiode into a voltage;

(40) a first storage capacitor 105,

(41) and at least a first switch 106 which is positioned between the first storage capacitor and an output of the photoreceptor circuit.

(42) The vision sensor of FIG. 3a further comprises a circuit 201 that is repeated for each column of pixels ((his circuit shall be called column circuit) and shared between all pixels in one column. This column circuit can be selectively connected to a pixel in the corresponding column, and it is configured to be able to detect if the difference between Vpr and Vpr_last exceeds a predefined threshold (which means an event has happened in the currently selected pixel). The column circuit may also be able to operate the switch between the photoreceptor output and the storage capacitor. Optionally the column circuit can contain an analog-to-digital converter (ADC) to convert Vpr to a digital number.

(43) The vision sensor of FIG. 3a further comprises a circuit 202 for selecting one or multiple rows (called row selection circuit), where selection means selectively connect the pixels in this row to the corresponding column circuit; and a circuit 203 for transmitting the addresses of those pixels where the difference between Vpr and Vpr_last exceeds a predefined threshold (and optionally the digital number representing Vpr) to some kind of receiver which can be external to the sensor chip. This circuit for transmitting data shall be called data readout circuit.

(44) The vision sensor of FIG. 3a further comprises a finite state machine (FSM) 301 for controlling the sensor; and a first-in-first-out (FIFO) memory buffer 302 for a more efficient readout of the addressed events.

(45) The FSM controls the readout and the writing of the addresses into the FIFO, while the receiver can read the addresses from the FIFO at its own pace.

(46) To improve readout speed, the pixel array could be split into a lower and upper half with separate column and readout circuits, which allows reading two rows in parallel and thus allows operating the sensor at twice the frame rate.

(47) Pixel Circuit

(48) Referring to FIG. 4, there is illustrated an exemplary configuration for a pixel 101 provided in any of the vision sensor embodiments; preferably each pixel 101 provided in the vision sensor of will be configured as is illustrated in FIG. 4.

(49) The pixel 101 may comprise, a photodiode 103 to convert light into a current Iphoto that is proportional to the light intensity; a photoreceptor circuit 104 that converts said current into a voltage Vpr (for example with a linear or logarithmic relation between Iphoto and Vpr); a storage capacitor 105 to store a past value of Vpr called Vpr last; at least a first switch 106 that allows setting the voltage on capacitor 105 to the current photoreceptor output voltage Vpr.

(50) The pixel 101 comprises a circuit 401 that allows to selectively connect the pixel to the circuit that determines if the difference between Vpr and Vpr_last exceeds a threshold. This circuit 401 is called PRO and allows reading out the voltages Vpr and Vpr_last, PRO can be either reading both quantities in parallel or sequentially. PRO is enabled by a RowSelect signal coming from the row selection circuit. If PRO is enabled, the output of PRO is connected to the input of the column circuit. PRO may contain a buffer to read out Vpr and Vpr_last without affecting the voltages themselves. The buffer provides an electrical impedance transformation.

(51) In the present description the ensemble of photodiode and photoreceptor shall be called pixel front-end; the ensemble of storage capacitor 105, the reset circuit and PRO 401 shall be called pixel back-end.

(52) Each pixel stores a voltage representing the illumination at the time of the last event emitted at this pixel, the illumination at the time of the last event shall be called illum_last. This representation is stored on a capacitor 105.

(53) The operable electronical connections (switches) used in the circuit may be implemented with a multitude of circuits: simple CMOS gates, full transmission gates or buffered, directed connections that establish an electronical connection without sharing charges.

(54) Alternative Pixel Circuit with Global Shutter

(55) Referring to FIG. 5, there is illustrated an exemplary configuration for a pixel 101 provided in any of vision sensors embodiments. Preferably each pixel 101 provided in the vision sensor of will have configured illustrated in FIG. 5.

(56) The pixel 101 comprises,

(57) a photodiode 103 to convert light into a current Iphoto that is proportional to the light intensity;

(58) a photoreceptor circuit 104 that converts said current into a voltage Vpr (for example with a linear or logarithmic relation between Iphoto and Vpr),

(59) a storage capacitor 105 to store a past value of Vpr called Vpr_last,

(60) at least a first switch 106 that allows setting the voltage on capacitor 105 to the current photoreceptor output voltage Vpr, a circuit 401 that allows to selectively connect the pixel to the circuit that determines if the difference between Vpr and Vpr_last exceeds a threshold,

(61) a second storage capacitor 501 and

(62) at least a second switch 502 that allows to electronically connect the output of the photoreceptor 104 to the second storage capacitor 501. This second switch 502 is operated simultaneously for all pixels.

(63) The circuit 401 is called PRO and allows to read out the voltages Vpr and Vpr_last. PRO can be either reading both quantities in parallel or sequentially. PRO is enabled by a RowSelect signal corning from the row selection circuit. If PRO is enabled, the output of PRO is connected to the input of the column circuit. PRO may contain a buffer to read out Vpr and Vpr_last without affecting the voltages themselves. The buffer provides an electrical impedance transformation.

(64) To avoid motion artefacts caused by changes in the scene between comparison of Vpr and Vpr_last of one pixel and the next pixel, it can be beneficial to simultaneously sample Vpr for all pixels before sequentially comparing Vpr to Vpr_last. To do simultaneous sampling for all pixels, an additional, second storage capacitor 501, another switch 502 and a global signal to control the switch 502 are needed.

(65) The additional switch 502 is used to sample Vpr for all pixels simultaneously on their corresponding second storage capacitor 501. The voltage on the second storage capacitor 501 then represents the illumination at the time of sampling. PRO 401 is configured to read either the voltage stored on the first storage capacitor 105 or the voltage on the second storage capacitor 501.

(66) In an embodiment of the vision sensor as shown in FIG. 3a, the additional switch 502 is controlled by the FSM 301.

(67) Pixel Sub-Blocks:

(68) Photoreceptor:

(69) It should be understood that the photoreceptor provided in each pixel of the pixel array of the vision sensor of FIG. 1a, may take any suitable configuration. FIGS. 6 to 10 provide exemplary implementations of the photoreceptor in each pixel.

(70) The pixel may use a logarithmic photoreceptor to allow for high dynamic range and sensitivity to temporal contrast instead of temporal difference. If a negative feedback circuit is employed, a fast response to illumination changes can be achieved.

(71) A basic logarithmic photoreceptor with feedback, illustrated in FIG. 6, consists of a photodiode 103, an inverting amplifier 602 and a circuit element with logarithmic current-to-voltage relation 601 that is connected between the input and the output of the inverting amplifier. The inverting amplifier ensures that the voltage over the photodiode remains almost constant. The output of the photoreceptor 603 is given by the output of the inverting amplifier.

(72) In the preferred photoreceptor with feedback implementation, illustrated in FIG. 7, the inverting amplifier is formed by an NMOS transistor 701 and a PMOS transistor 702. The source of the NMOS 701 is connected to ground, the gate is connected to the photodiode 103 and the drain is connected to the drain of the PMOS 702, forming the output of the inverting amplifier 603. The source of the PMOS 702 is connected to the power supply, and the gate is connected to a constant bias voltage 704. A second NMOS feedback transistor 703 is used for the logarithmic current-to-voltage conversion, the source of the second NMOS transistor 703 is connected to the photodiode, the gate is connected to the output of the inverting amplifier 603 and the drain is connected to the power supply.

(73) Alternative Logarithmic Photoreceptor with Feedback with more Conversion Gain:

(74) Referring to FIG. 8 there is illustrated a logarithmic pixel front-end with increased gain compared to the pixel front-end illustrated in FIG. 7. To increase the pixel gain (higher change of the photoreceptor output voltage Vpr for a given light intensity change) an additional NMOS transistor 801 is added to the photoreceptor in between the photodiode 103 and the source of the feedback transistor 703.

(75) Alternative Logarithmic Photoreceptor with Feedback with PMOS Feedback Transistor:

(76) An alternative implementation of the photoreceptor, illustrated in FIG. 9 uses a PMOS transistor 901 instead of an NMOS transistor as feedback element. The drain of the PMOS transistor 901 is connected to the photodiode 103, the gate is connected to a bias voltage 902 and the source is connected to the output of the inverting amplifier 603. This improves the speed of the response as well as the noise performance. The speed of the response is improved because there is less parasitic capacitance between the photodiode voltage and the output of the photoreceptor. The noise performance is improved because PMOS transistors tend to have lower flicker noise than NMOS transistors.

(77) Implementation of Logarithmic Front-End without Feedback:

(78) To further reduce the size of the pixel, it is possible to use a photoreceptor without feedback circuit. Then the photoreceptor consists of a photodiode and one transistor. The transistor used can be either an NMOS or a PMOS.

(79) Illustrated in FIG. 10 is a photoreceptor with NMOS transistor 1001, where the drain of the transistor is connected to the power supply, the gate is connected to a bias voltage 1002 and the source, which is the output 1001 of the photoreceptor, is connected to the photodiode 103. Using an NMOS transistor in this photoreceptor, it is possible to have a complete pixel without PMOS transistor, which allows more compact layout.

(80) The disadvantage of an implementation without feedback is that the pixel response to a light intensity change is slower because the voltage swing over the photodiode capacitance is bigger.

(81) Preferred Pixel Back-End Implementation:

(82) It should be understood that the pixel back-end provided in each pixel of the pixel array of the vision sensor of FIG. 1a, 2a or 3a, may take any suitable configuration. FIGS. 11 to 13 provide exemplary implementations of each pixel for the embodiment of the vision sensor illustrated in FIG. 2a.

(83) Referring to FIG. 11, the implementation of the pixel includes an output buffer in the form of a source follower NMOS transistor 1101 and corresponding switch (implemented as NMOS transistor) 1102, a storage capacitor 105, which may be (implemented likely as a Moscap, and four switches 106, 1103, 1104 and 1105. The two switches 1105 and 106 in series, one controlled by the row selection circuit 202 and the other one the column circuit 201, allow to set the voltage on the storage capacitor 105 to the output voltage of the photoreceptor 104. This series of two switches ensures that not only a pixel where the corresponding row select signal is active, can be reset (which means setting the voltage on the storage capacitor 105 to the output of the photoreceptor) by a column circuit.

(84) For the column circuit 201 to determine if the difference between Vpr and Vpr_last exceeds a predefined threshold, the row select circuit 202 closes switch 1102 and 1105, and then the switch 1104 is closed while switch 1103 is open. This allows the column circuit to read the output of the photoreceptor. Then switch 1104 is opened and switch 1103 is closed and the column circuit can read the voltage stored on the capacitor 105. When the column circuit has read both voltages, it determines if the difference between Vpr and Vpr_last exceeds a predefined threshold, and if it does, the column circuit can close switch 106 to set the voltage on the capacitor 105 to the voltage of the photoreceptor output.

(85) It is preferably to have the storage capacitor 105 much larger than the parasitic capacitor of the source follower input transistor Msf 1101.

(86) Pixel Implementation with ‘Global Shutter’:

(87) To avoid motion artefacts caused by changes in the scene during the scanning of one frame, for some applications it can be beneficial to globally sample the photoreceptor output voltage Vpr for each pixel at the same instant. In FIG. 12 is illustrated a pixel that allows globally sampling Vpr. Compared to the pixel illustrated in FIG. 11, this pixel contains a second storage capacitor C2 501 and a further switch 502. The further switch is placed between C2 and the photoreceptor circuit 104 and it is controlled by a global signal called Sample_now. Preferably this further switch 502 is operated in all pixels simultaneously.

(88) Pixel with Additional Switch to Reduce the Effect of Charge-Sharing:

(89) When the voltage stored on the storage capacitor 105 is read out using the source follower input transistor Msf 1101 an effect called charge sharing can affect the result. Whatever charge stored on Msf before connecting the storage capacitor 105 will influence the resulting voltage on the gate of Msf.

(90) If it is necessary to minimize the effect of charge sharing, it is beneficial to reset the parasitic capacitor of Msf 1101 to a known reference voltage before selecting one of the storage capacitors. Referring to FIG. 13, this can he done by adding an additional switch 1302 that allows to connect the gate of Msf to a voltage source 1301. The additional switch 1302 is closed for a short time, and then reopened before Msf is connected to the storage capacitor 105 by closing switch 1103.

(91) Row Selection Circuit:

(92) It should be understood that the row selection circuit 202 of the vision sensor of FIG. 2a or 3a, may take any suitable configuration. FIG. 14 illustrates an example implementation of a row selection circuit. The row selection circuit selectively connects a row of pixels to the corresponding column circuit 201 by means of a set of RowSelect signals. The output of the row selection circuit is a set of RowSelect signals, one for each row of pixels. Selecting a row means the the RowSelect signal for this row is active, while the RowSelect signals for all other rows are inactive. The row selection circuit may consist of a set of Flip-Flops 1400 connected in series to form a shift-register scan circuit.

(93) The row selection circuit has a clock input which allows moving from one row to the next row, which means the currently active RowSelect signals is changes to inactive, while the next RowSelect signal changes its state to active.

(94) The row selection circuit contains a circuit 1401 that encodes the address 1402 of the currently selected row and outputs this address to the data readout circuit 203.

(95) The row selection circuit may contain the possibility to be configured in a way to skip rows during scanning. This feature is used to implement a so-called region-of-interest (ROI) readout.

(96) In an embodiment of the vision sensor such as shown in FIG. 3a, the control signals for the shift register (Bitin, Reset and Clock) may be controlled by the FSM 301.

(97) Column Circuit:

(98) Referring to FIG. 15 there is show a possible implementation for the column circuit which can be used in any of the vision sensor embodiments. The column circuit comprises,

(99) a switched capacitor circuit SC 1501 which allows taking the difference between Vpr and Vpr_last of the currently selected pixel 101 in this column. The circuit SC may amplify this difference creating a voltage Vdiff 1500;

(100) a first comparator CP1 1502 with the first input connected to a first threshold voltage 1503 and the second input connected to Vdiff 1500 and a second comparator CP2 1504 with the first input connected to Vdiff 1500 and the second input connected to a second threshold voltage 1505;

(101) a logic circuit LC 1506: Based on the outputs of the comparators CPI 1502 and CP2 1504, an event is considered to have occurred if one of the comparator outputs indicates that the difference between the photoreceptor 104 output voltage and the voltage stored on the capacitor 105 is larger than one of the thresholds. In the case of an event, LC activates the switch 106 by means of a reset signal 1508, and actives the ‘event’ output signal 1507.

(102) Optionally an ADC may be provided in the column circuit to convert the photoreceptor 104 output Vpr of the currently selected pixel to a digital number.

(103) Switched Capacitor Circuit SC:

(104) Referring to FIG. 16, there is illustrated an SC circuit 1501 based on a correlated double sampling (CDS) circuit such as is used in image sensors. CDS circuits are well known.

(105) The SC circuit consists of a current source 1600 that is connected to the PRO 401 circuit in the pixel 101, an amplifier 1601, two capacitors CS1 1602 and CS2 1603 and three switches which controlled by the signal Phi1, Phild and Phi2.

(106) With this implementation, the difference 1500 between Vpr and Vpr_last is amplified by the capacitor ratio

(107) $\frac{CS1}{\mathrm{CS}2}.$

(108) While the pixel is configured to output Vpr, Phi1 and Phild are active and the corresponding switches are closed, while Phi2 is inactive and the corresponding switch open. Then Phi1 is made inactive and the corresponding switch is opened. Afterwards Phild is made inactive and the corresponding switch is opened. Then Phi2 is activated and the corresponding switch is closed. Then the pixel is configured to output Vpr_last. After a settling time, the output 1500 of the circuit will correspond to the amplified difference between Vpr and Vpr_last.

(109) In an embodiment of the vision sensor such as shown in FIG. 3a, the waveforms of Phi1, Phild and Phi2 (shown in the lower left part of FIG. 16) may be controlled by the FSM 301.

(110) Logic Circuit LC Implementation:

(111) A basic implementation of the LC circuit 1506, as illustrated in FIG. 17 consists of an OR-gate 1700 to combine the outputs of the two comparators CP1 1502 and CP2 1504. The output of the OR is high if one of the comparators signals that the difference between Vpr and Vpr_last is bigger than the corresponding threshold. The output of the OR gate is stored in a Flip-Flop 1701 at the rising edge of a Latch signal. The Flip-Flop may be reset with a signal called Reset. The output of the Flip-Flop indicates an event 1507 and goes to the data readout circuit 203, and it is also ANDed 1702 with a control signal ResPix_FSM to generate the pixel reset signal 1508 which goes to the pixels in this column and controls the first switch 106.

(112) In an embodiment of the vision sensor such as shown in FIG. 3a, the waveforms of the control signal Latch, Reset and ResPix_FSM may be controlled by the FSM 301.

(113) Logic Circuit LC Implementation with Polarity Output:

(114) If it is desired that the sensor outputs the polarity of the illumination changes (whether the light intensity increased or decreased), the LC circuit illustrated in FIG. 18 may be used. The circuit consists of two Flip-Flops 1801, 1802 to store the outputs of the comparators CP1 1502 and CP2 1504 on the rising edge of a latch signal. The outputs of the Flip-Flops define the output 1507 of this LC circuit implementation, which thus consists of two signals going to the data readout circuit 203. One of these signals (EventOn) indicates increasing light intensity, the other one (EventOff) indicates decreasing light intensity. There is an OR-gate 1803 with its inputs connected to the outputs of the Flip-Flop and its output connected to an AND-gate 1804. The second input of the AND-gate is a global control signal ResPix_FSM. The output 1508 of the AND-gate controls the first switch 106 in the pixels of the corresponding column.

(115) Data Readout Circuit:

(116) It should be understood that the data readout circuit 203 provided in the vision sensor of FIG. 2a or 3a, may take any suitable configuration. FIGS. 19 and 20 provide exemplary implementations of a data readout circuit for the embodiment of the vision sensor illustrated in FIG. 2a or 3a.

(117) The data readout circuit allows reading out the addresses of those pixels where an event has happened. For this, row after row, the address of the corresponding row is output, as well as the addresses of all the columns where an event is latched.

(118) As illustrated in FIG. 19, a data readout circuit may comprise a communication bus 1900; a column address encoder circuit 1903 that encodes the column address; a switch 1904 that allows to connects the encoder circuit 1903 to the communication bus; a switch 1905 that allows to connects the row address 1402 to the communication bus.

(119) The data read out circuit further comprises, for each column circuit 201 an arbitration logic circuit (hereinafter referred as arblogic circuit) 1901 that, in case of an event 1507 in this column, by means of a request signal requests to the arbitration circuit 1902 for transmitting its address on the communication bus. Once it has transmitted the address, this circuit will disable its request signal. An arbitration circuit 1902 that arbitrates between all the arblogic circuits 1901 wanting to transmit an event.

(120) To transmit all the events in a row of pixels, first the row address 1402 is connected to the communication bus 1900 by means of switch 1905. Once the row address has been transmitted, the column address encoder 1903 is connected to the communication bus 1900 by means of switch 1904. Now all the active event bits (outputs 1507 of the column circuits 201) are stored in the arblogic circuits 1901. The arblogic circuits with active event bits request to the arbitration circuit 1902 for access to the communication bus. The arbitration circuit sequentially grants access to all requesting arblogic circuits by means of an acknowledge signal, until no more arblogic circuit are requesting and all event column addresses have been transmitted.

(121) Then event transmission for the next row can start.

(122) Like the row selection circuit, the arbitration circuit may contain the possibility to skip columns to allow for ROI readout.

(123) Token-Based Readout Circuit:

(124) An alternative implementation of the data readout circuit may be a token-readout circuit, such as illustrated in FIG. 20.

(125) The token-readout is a circuit for the reading of the active event bits in an assembly of column circuits connected to a communication bus, for the transmission of this information via the communication bus, comprising means for reading the values contained in at least a part of the column circuits of this assembly having a value to transmit, and an arbitration circuit for the successive transmission of the values read via the communication bus, characterized in that the arbitration circuit comprises at least one plurality of processing blocks X0, X1, X2, X3 allocated respectively to each of the said column circuits, and in that the processing blocks X0, X1, X2, X3 of each of the said pluralities of processing blocks are arranged such that, in the course of a transmission of the said values, they transfer from one block to the following block of this plurality a unique authorization signal for the transmission of the read value, the said authorization signal being capable, when passing from one processing block to the following block, of detecting those among the said column circuits associated with the said plurality of processing blocks which have an item of information (event) to transmit and of causing, where applicable, the successive transmission of the said information to the said communication bus.

(126) As shown on the left side of the FIG. 20, a j_in signal indicating according to its value 1 or 0, the availability or unavailability of the token for a given processing block, is switched either to bypass a corresponding D flip-flop 30, and send the input j_in directly to the output j_out of the D flip-flop 30 using logic gates 32 and an inverter 34, depending on the value 1 or 0 of a stop signal, depending on whether the column circuit has a value to be transmitted.

(127) When j_in signal is 1, this token to the input of the D flip-flop 30 is stored in the D flip-flop at the rising edge of a clock signal CK is also supplied to the latch D. The entry of the D flip-flop may also be used as the corresponding pixel selection signal. Thus, a selection signal sel is directly connected to the input of the D flip-flop 30.

(128) The sel and the output signal Q of the D flip-flop 30 are input to an AND gate 36 which outputs a signal j_stop. This j_stop signal goes to 1 when the token is present at the input of the D flip-flop and returns to 0 when the chip was sampled, that is to say updated in the D flip-flop memory 30.

(129) The right part of the FIG. 20 illustrates how a shift register, wherein the token is propagated, can be achieved by the cascading of blocks X0 to X3 such as that shown in the left part of this same FIG. 20.

(130) The block X0 has its input j_in connected to the Q output of a D flip-flop used to inject the token in the shift register.

(131) To initialize the shift register, a reset signal 1 is transmitted to a corresponding input of each D flip-flop of the shift register, so that they may be reset and a token to be placed at the input of the first D flip-flop.

(132) In the example shown in FIG. 20, the column circuits corresponding respectively to the blocks X0, X1 and X3 have a value to be transmitted (corresponding signals stop0, stop1, and stop3 are 1). The column circut corresponding to X2 has nothing to transmit (stop2 is 0).

(133) When a token is placed at the input of block X0, since the stop0 signal is 1, the sel0 signal goes to 1. At the first rising edge of the clock signal ck sent to all the D flip-flops of the shift register, the corresponding pixel in block X0 sends its value via the communication bus and sel0 signal goes to 0 and passing the token at the entrance of the block X1. Sel1 signal then goes to 1 as stop1 is 1. In the next rising edge of the clock signal ck, the pixel corresponding to the block X1 transmits its value via the communication bus and sell signal goes to 0 and passing the token directly to the input of the X3 block as the stop2 signal is 0. Sel3 signal then passes to 1. More generally, when the sel_i signal is 1, the communication bus is then available to the column circuit corresponding to the block Xi.

(134) Control FSM:

(135) As illustrated in FIG. 3a, an embodiment of the proposed vision sensor may include a finite state machine (FSM) 301 that controls the sensor. This means that the FSM will control the row selection circuit 202; control the column circuits 201 and also the data readout circuit 203. The FSM will control the writing of the event addresses to a FIFO 302 on the sensor chip. Specifically the FSM will control all the signals that operate the switches in the pixel and in the column circuits.

(136) An FSM is a mathematical model of computation used to design both computer programs and sequential logic circuits. It is conceived as an abstract machine that can be in one of a finite number of states. The machine is in only one state at a time; the state it is in at any given time is called the current state. It can change from one state to another when initiated by a triggering event or condition; this is called a transition. A particular FSM is defined by a list of its states, and the triggering condition for each transition.

(137) The implementation of an FSM is a set of registers and logic gates that implement the equations defined in the list of states and the triggering conditions.

(138) FIG. 21 shows in an abstract way the states and transitions of the control FSM that may be used in an embodiment of the proposed vision sensor.

(139) Referring to FIG. 22 there is illustrated the timeline of the different signals coming from the control FSM. The signal Row Scan Clock controls the row selection circuit 202, Sel_last controls the switch 1103, Sel_now controls the switch 1104. The signals Latch, Reset and ResPix_FSM go to the LC circuit 1506, and the signal Data readout enables the data readout circuit 203.

(140) Sampling and comparing the pixel voltages and event bit readout can be pipelined, which means that while the voltages from the currently selected rows are sampled, the event bits from the last row are read out. It means the ‘event’ bits (output from the column circuits) have to be stored in the data readout circuit.

(141) FIFO:

(142) As illustrated in FIG. 3a, an embodiment of the proposed vision sensor may include a first-in-first-out (FIFO) memory buffer 302. A first-in-first-out (FIFO) memory buffer is a memory where the data is read out in exactly the same sequence as it has been written into the memory. This mean a data word that is written first is also read first when the receiver enables a memory read request.

(143) FIFOs are commonly used in electronic circuits for buffering and flow control between hardware and software. In its hardware form, a FIFO primarily consists of a set of read and write pointers, storage and control logic. Storage may be static random access memory (SRAM), flip-flops, latches or any other suitable form of storage. For FIFOs of non-trivial size, a dual-port SRAM is usually used, where one port is dedicated to writing and the other to reading.

(144) Sensor Concept and Operation:

(145) The proposed sensor will be used in a machine vision context, meaning that the output of the sensor will go (directly or indirectly) to some kind of processor, where some kind of algorithm runs, for example to calculate the position and movement of the sensor system.

(146) The proposed sensor does not output images like a conventional image sensor. The pixel value (meaning a value representing the light intensity of this pixel) may optionally be output to the processor; instead the addresses of those pixels where a change is detected are transmitted. To detect changes between now and a previous moment in time, each pixel stores a representation of the light intensity at this previous moment in time (called illum_last).

(147) The sensor consists of an array of pixels, organized in rows and columns. To detect events, one row of pixels shall be selected and for each pixel in this row, voltages representing illum_last and the current illumination are transferred to peripheral circuits, where the difference between the voltages representing illum_last and the current illumination is computed. If the difference between these voltages exceeds a threshold, the address of this pixel (and optionally a value representing the current illumination) is output and illum_last is set to the current illumination for this pixel. If this process is finished for the currently selected row, this row is unselected, and the next row is selected. Like this the whole sensor is scanned. A single complete scan of the sensor shall be called a frame. The rate at which a complete frame is scanned is called the frame rate.

(148) Reading of the pixel voltages representing illumination and comparing them against the thresholds as well as resetting the pixels in case of an event happen in a row-parallel way. This means all pixels in a row are selected by the row selection circuit, and connected to their corresponding column circuits. All the column circuits simultaneously compute the difference of the voltages and finally they do the comparison against the thresholds and the pixel reset.

(149) The sequence can also be pipelined to achieve higher frame rate. Pipelined here means that while sampling and computing the difference for the pixels in a row happens, the addresses (and potentially the values) from the previous row are read out and the corresponding pixels are reset. The potential ADC conversion can be an additional pipeline step between sampling and readout.

(150) Because this proposed sensor strongly reduces redundancy of the output data, the load of the processing stage is reduced. And because this sensor does not need to convert pixel level voltages with a multi-bit analog-to-digital converter (ADC) for each pixel and each frame, the amount of data to be transmitted is reduced. The sensor can thus run at a higher frame rate than a conventional image sensor at the same resolution and the same power budget. This also facilitates post processing because the movement between two frames is smaller and thus matching visual landmarks is easier.

(151) Mathematical Formulation:

(152) To better illustrate the sensor concept; in the following a few basic equations describing the sensor are given. The voltage representing the illumination at time t is given by
Vpr(t)=f(Int(t))   (4)
where Int(t) is the illumination at time t and f(.) is a function that depends on the implementation of the pixel photoreceptor circuit 104. The voltage is sampled at discrete times
Vpr(tn)=f(Int(tn))   (5)
tn=n*tframe   (6)
to denotes the sampling time of the n-th frame, tframe is the inverse of the frame rate. In each frame, we compute the difference of the current Vpr and Vpr at the time of the last event, this time is called tl. The difference is called Vdiff, and it is potentially amplified by a factor A:

(153) $\begin{array}{cc}\mathrm{Vdiff}\left(\mathrm{tn}\right)=A*\left(\mathrm{Vpr}\left(\mathrm{tn}\right)-\mathrm{Vpr}\left(\mathrm{tl}\right)\right)=A*\left(f\left(\mathrm{Int}\left(\mathrm{tn}\right)\right)-f\left(\mathrm{Int}\left(\mathrm{tl}\right)\right)\right)& \left(7\right)\\ \mathrm{Vdiff}\left(\mathrm{tn}\right)=A{\int }_{\mathrm{tl}}^{\mathrm{tn}}{f}^{\prime }\left(\mathrm{Int}\left(\mathrm{tn}\right)\right)*\frac{d\mathrm{Int}\left(t\right)}{\mathrm{dt}}\mathrm{dt}& \left(8\right)\end{array}$
This means that Vdiff is an integral over the derivative of the light intensity, meaning it accumulates changes in the light intensity. An event is generated if Vdiff is bigger than the threshold:
Vdiff(tn)>VthresOn.fwdarw.EventOn=1, Vdiff(tn)<VthresOn.fwdarw.EventOn=0   (9)
Vdiff(tn)<VthresOff.fwdarw.EventOff=1,Vdiff(tn)>VthreOff.fwdarw.EventOff=0   (10)
VthresOn is bigger than zero, VthresOff is smaller than zero. If EventOn or EventOff equals 1, the pixel is reset and Vpr(tn) is stored for comparison in future frames.

(154) Example Equations for Logarithmic Photoreceptor:

(155) As an example for better understanding, for the following equations it is assumed that the sensor stores a quantity that is proportional to the logarithm of the light intensity, because this is the preferred implementation.

(156) A voltage encoding the light intensity is read at discretized times:
Vpr(tn)=k1+k2*log (Int(tn)),   (11)
where k1 and k2 are constants. To decide if an event has happened, we compute the difference between Vpr(tn) and Vpr at the time of the last event tl:

(157) $\begin{array}{cc}\mathrm{Vdiff}\left(\mathrm{tn}\right)=A\left(\mathrm{Vpr}\left(\mathrm{tn}\right)-\mathrm{Vpr}\left(\mathrm{tl}\right)\right)=A*k2(\log \left(\mathrm{Int}\left(\mathrm{tn}\right)\right)-\log \left(\mathrm{Int}\left(\mathrm{tl}\right)\right)& \left(12\right)\\ \mathrm{Vdiff}\left(\mathrm{tn}\right)=A*k2*\log \frac{\mathrm{Int}\left(\mathrm{tn}\right)}{\mathrm{Int}\left(\mathrm{tl}\right)}& \left(13\right)\end{array}$ We see that for a logarithmic intensity encoding, the sensor reacts to relative changes in the intensity, which is useful because it means the sensor reacts to scene reflectance changes independent of the illumination level which is the reason for being the preferred embodiment. From equation (5), we see that

(158) $\begin{array}{cc}\mathrm{Vdiff}\left(\mathrm{tn}\right)=A{\int }_{\mathrm{tl}}^{\mathrm{tn}}{f}^{\prime }\left(\mathrm{Int}\left(t\right)\right)*\frac{d\mathrm{Int}\left(t\right)}{\mathrm{dt}}\mathrm{dt}=A{\int }_{\mathrm{tl}}^{\mathrm{tn}}k2*\frac{1}{\mathrm{Int}\left(t\right)}*\frac{d\mathrm{Int}\left(t\right)}{\mathrm{dt}}\mathrm{dt}& \left(14\right)\end{array}$ Thus, Vdiff is the derivative of the light intensity normalized by the light intensity and then integrated between the time of the last event and now. If we solve the integral, we again have equation (9). Vdiff being bigger than a threshold VthresON means that

(159) $\begin{array}{cc}\frac{\mathrm{Int}\left(\mathrm{tn}\right)}{\mathrm{Int}\left(\mathrm{tl}\right)}>\exp \left(\frac{\mathrm{VthresON}}{A*k2}\right)=\mathrm{const}& \left(15\right)\end{array}$ So, the sensor generates an event if there is a sufficient relative change in the light intensity. The equation for VthresOff is similar. In the following, for the sake of illustrating the sensor concept in an even simpler way, we assume that the light intensity is changing with a constant derivative. This means that

(160) $\begin{array}{cc}\mathrm{Int}\left(\mathrm{tn}\right)=\mathrm{Int}\left(\mathrm{tl}\right)+\frac{d\mathrm{Int}}{\mathrm{dt}}*\left(n-l\right)*\mathrm{tframe}& \left(16\right)\\ \mathrm{Vdiff}\left(\mathrm{tn}\right)=A*k2*\log \frac{\mathrm{Int}\left(\mathrm{tl}\right)+\left(n-l\right)*\mathrm{tframe}*\frac{d\mathrm{Int}}{\mathrm{dt}}}{\mathrm{Int}\left(\mathrm{tl}\right)}& \left(17\right)\end{array}$ An event is generated if the value of Vdiff(n) is bigger than VthresOn (for positive derivatives of the intensity).

(161) $\begin{array}{cc}\frac{\mathrm{Int}\left(\mathrm{tl}\right)+\left(n-l\right)*\mathrm{tframe}*\frac{d\mathrm{Int}}{\mathrm{dt}}}{\mathrm{Int}\left(\mathrm{tl}\right)}>\exp \left(\frac{\mathrm{VthresON}}{A*k2}\right)=\mathrm{const}& \left(18\right)\end{array}$

(162) The left side of equation (15) is monotonously increasing with increasing n at a rate given by

(163) $\frac{d\mathrm{Int}}{dt}.$
This means tor large derivatives of the intensity the threshold can be reached within few frames, while for small derivatives a larger number of frames is required to reach the threshold, the small changes from one frame to the next frame are accumulated until the threshold is reached.