Method for characterization of standard cells with adaptive body biasing

Abstract

A method for an improved characterization of standard cells in a circuit design process is disclosed. Adaptive body biasing is considered during the design process by using simulation results of a cell set, a data-set for performance of the cell set, and a data-set for a hardware performance for a slow, typical and fast circuit property. Static deviations in a supply voltage are considered by determining a reference performance of a cell and a reference hardware performance monitor value at a PVT corner. A virtual regulation and adapting of body bias voltages of the cell set is performed such that the reference performance of the cell or the reference hardware performance monitor value will be reached at each PVT corner and for compensating the static deviation in the supply voltage. The results are provided in a library file.

Claims

1. Method for characterization of a standard cell with adaptive body biasing, wherein the standard cell comprises a plurality of nmos transistors, pmos transistors, n-wells and p-wells, wherein the characterization of the standard cell is defined by a specified operating range of a fabrication process delay time dependency P of the standard cell, a specified operating range of a supply voltage V of the standard cell and a specified operating range of an operating temperature T of the standard cell, wherein the fabrication process delay time dependency P is a function of a minimum and a maximum switching time of the nmos and pmos transistors of the standard cell, the method comprising the following steps: simulating a standard cell data-set over the specified operating ranges of P, V and T, and generating a data-set for an operating range of a performance value F of a circuit characteristic of the standard cell with F being a function of V, T, P, VNW and VPW, wherein VNW is an adaptive body biasing voltage applied to the n-wells and VPW is an adaptive body biasing voltage applied to the p-wells; simulating a hardware performance monitor circuit data-set over the specified operating ranges of P, V and T, wherein the hardware performance monitoring circuit monitors the performance value F of the standard cell, and generating a data-set for an operating range of a hardware performance monitor value C of a characteristic of the performance monitor circuit, with C being a function of V, T, P, VNW and VPW; considering static deviations in the supply voltage V of the standard cell by applying a pessimism of plus or minus x percent (i.e., +/−x %) to a nominal voltage value VDD.sub.nom of the supply voltage V, resulting in a determination of corner voltage values VDD.sub.c,PVT of the supply voltage V, wherein each VDD.sub.c,PVT equals VDD.sub.nom+/−x %, and further obtaining thereof a set of PVT corner values, which define a set of PVT corners, wherein the PVT corner values comprise a minimum and a maximum process delay time dependency value of P, a minimum and a maximum operating temperature value of T and a minimum and a maximum value of VDD.sub.c,PVT and the PVT corners are each defined by a PVT corner value of P, V and T; determining a reference hardware performance value F0 of the set of performance values F of the standard cell, wherein the reference performance value F0 is a function of P, V and T values that are within the PVT corner values of the standard cell; determining a reference hardware performance monitor value C0 of the set of performance monitor values C, wherein C0 is the value associated with the performance monitoring circuit monitoring the performance value F0 of the standard cell; performing a virtual regulation and adapting of body bias voltages VNW and VPW to determine a VNW.sub.c0 of the VNW and a VPW.sub.c0 of the VPW for each PVT corner of the set of PVT corners of the standard cell such that, when VNW.sub.c0 and VPW.sub.c0 are applied to each associated PVT corner of the set of PVT corners, said reference performance value F0 of the standard cell or said reference hardware performance monitor value C0 will be reached at each PVT corner of said set of PVT corners and the static deviation in the supply voltage will be compensated for by the application of the VNW.sub.c0 and VPW.sub.c0 at each associated PVT corner; defining a set of PVTBB corner values, which define a set of PVTBB corners for the set of PVT corners, wherein each PVTBB corner value is a function of P, T, VDD.sub.cPVT, VNW.sub.c0 and VPW.sub.c0, and the PVTBB corners are each defined by a PVTBB corner value of P, V and T, and wherein in a three dimensional graph of P, V and T, the set of PVTBB corners define a first area in the graph that is smaller than, and positioned within, a second area in the graph defined by the set of PVT corners; and providing the results of characterizing the cell with adaptive body biasing in a library file.

2. The method for characterization of a standard cell with adaptive body biasing according to claim 1, wherein the reference hardware performance monitor value C0 is determined by considering a worst case P, V, T condition wherein P, V and T correspond to a PVT corner having a maximum process delay time dependency value of P, the minimum or the maximum operating temperature value of T, and the minimum supply voltage value of VDD.sub.cPVT (i.e., VDD.sub.nom−x %), and choosing bias conditions for maximum performance in the worst case P, V, T condition, or the reference hardware performance monitor value C0 is determined by considering a typical P, V, T condition wherein P has a value that is between the minimum and the maximum process delay time dependency value of P, V has a value that is substantially equal to VDD.sub.nom and T has a value that is between the minimum and the maximum operating temperature value of T, and choosing a centered value of the bias voltages, or the reference hardware performance monitor value C0 is determined by considering a best case P, V, T condition wherein P, V and T correspond to a PVT corner having a minimum process delay time dependency value of P, the minimum or the maximum operating temperature value of T, and the maximum supply voltage value of VDD.sub.cPVT (i.e., VDD.sub.nom−x %), and choosing bias conditions for minimum leakage current performance in the best case P, V, T condition.

3. The method for characterization of a standard cell with adaptive body biasing according to claim 2, wherein the method further comprises considering dynamic derivations in the bias voltages VNW and VPW by adding a VPW dynamic derivation pessimism of plus or minus (i.e., +/−) ΔVPW to the VPW or by adding a VNW dynamic derivation pessimism of +/−ΔVNW to the VNW related to said reference performance F0 of the standard cell, wherein VNW+/−ΔVNW equals VNW.sub.c and wherein VPW+/−ΔVPW equals VPW.sub.c, for each PVT corner and is used for representing a charge pump ripple.

4. The method for characterization of a standard cell with adaptive body biasing according to claim 3, wherein a pessimism of plus or minus ΔVPW.sub.m (i.e., +/−ΔVNW.sub.m) is added to the adaptive body bias voltage VPW or a pessimism of plus or minus ΔVNW.sub.m (i.e., +/−ΔVNW.sub.m) is added to the adapted body bias voltage VNW, wherein ΔVPW.sub.m and ΔVPW.sub.m are used for representing a mismatch effect in the hardware performance monitor circuit.

5. The method for characterization of a standard cell with adaptive body biasing according to claim 4, wherein the method further comprises considering dynamic deviations in the supply voltage V of the standard cell by applying a pessimism of plus or minus y percent (i.e., +/−y %) to the nominal voltage value VDD.sub.nom of the supply voltage V, resulting in a determination of PVTBB corner voltage values VDD.sub.c,PVTBB of the supply voltage, wherein each VDD.sub.c,PVTBB equals VDD.sub.nom+/−(x+y) %.

6. The method for characterization of a standard cell with adaptive body biasing according to claim 5, wherein a performance value of F of the set of performance values F in the PVTBB corners is determined by interpolation based on the generated data-set for the operating range of the performance value F and different VNW and VPW values, whereas the results are provided in the library file.

7. The method for characterization of a standard cell with adaptive body biasing according to claim 1, wherein the adaptive body biasing of a PVT corner is performed before the characterization of the cell.

8. The method for characterization of a standard cell with adaptive body biasing according to claim 1, wherein a circuit characteristic of the standard cell is a delay time.

9. The method for characterization of a standard cell with adaptive body biasing according to claim 1, wherein a circuit characteristic of the standard cell is a leakage current consumption.

10. The method for characterization of a standard cell with adaptive body biasing according to claim 1, wherein the method is used for the characterization of analogue or mixed-signaled circuit blocks.

11. The method for characterization of a standard cell with adaptive body biasing according to claim 10, wherein the circuit block is an oscillator circuit or a driver circuit.

12. The method for characterization of a standard cell with adaptive body biasing according to claim 1, wherein the method further comprises considering dynamic derivations in the bias voltages VNW and VPW by adding a VPW dynamic derivation pessimism of plus or minus (i.e., +/−) ΔVPW to the VPW or by adding a VNW dynamic derivation pessimism of +/−ΔVNW to the VNW related to said reference performance F0 of the standard cell, wherein VNW+/−ΔVNW equals VNW.sub.c and wherein VPW+/−ΔVPW equals VPW.sub.c, for each PVT corner and is used for representing a charge pump ripple.

13. The method for characterization of a standard cell with adaptive body biasing according to claim 1, wherein a pessimism of plus or minus ΔVPW.sub.m (i.e., +/−ΔVPW.sub.m) is added to the adaptive body bias voltage VPW or a pessimism of plus or minus ΔVNW.sub.m (i.e., +/−ΔVNW.sub.m) is added to the adapted body bias voltage VNW, wherein ΔVPW.sub.m and ΔVPW.sub.m are used for representing a mismatch effect in the hardware performance monitor circuit.

14. The method for characterization of a standard cell with adaptive body biasing according to claim 1, wherein the method further comprises considering dynamic deviations in the supply voltage V of the standard cell by applying a pessimism of plus or minus y percent (i.e., +/−y %) to the nominal voltage value VDD.sub.nom of the supply voltage V, resulting in a determination of PVTBB corner voltage values VDD.sub.c,PVTBB of the supply voltage, wherein each VDD.sub.c,PVTBB equals VDD.sub.nom+/−(x+y) %.

15. The method for characterization of a standard cell with adaptive body biasing according to claim 1, wherein a performance value of F in the set of performance values of F in the PVTBB corners is determined by interpolation based on the generated data-set for the operating range of the performance value F and different VNW and VPW values, whereas the results are provided in the library file.

Description

(1) The invention will be explained in more detail using an exemplary embodiment.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

(2) The appended drawings show

(3) FIG. 1 Visualization of the PVTBB corners according to the invention;

(4) FIG. 2 Illustration of the body biasing, the adaption of the n-well-bias and p-well bias voltages for regulation of the performance of a cell;

(5) FIG. 3 Overview of the overall procedure of the inventive method for characterization of a standard cell with adaptive body biasing.

DETAILED DESCRIPTION

(6) FIG. 1 shows a visualization of the PVTBB corners. These PVTBB corners can be represented as the corners of a cube, whereas the size of the cube is characterized by the three dimensions temperature (T), supply voltage VDD and process (P). The process (P) dimension extends from slow-slow, meaning slow-nmos/slow-pmos referring to timing to fast-fast, meaning fast-nmos/fast-pmos referring to timing, the temperature (T) from Tmin to Tmax, and the supply voltage from VDDmin to VDDmax. A slow/cold corner is characterized by a low temperature, a low supply voltage and a slow process. A fast/hot corner is characterized by a high temperature, a high supply voltage and a fast process.

(7) So far, the characterization of standard cells was carried out without consideration of body biasing, e.g. through the connection of VSS nodes, or the characterization was carried out with fixed body bias voltages at each library corner, whereas an adaption of the body bias voltages during operation could not be considered. Therefore, it was necessary to assume a high pessimism for the determination of the library corners which are used in the simulation/characterization process of standard cells by the customers.

(8) With the inventive method the consideration of the specific body bias values VNWc and VPWc for a corner is possible before the final characterization of the cell is carried out. This will be achieved by performing a “virtual regulation” (numerical method) and assuming that these cells operate in an adaptive body bias control system. The virtual regulation of the body bias voltages takes into account static variations of the supply voltage. Additionally, a separate consideration of dynamic variations of the supply voltage that cannot be compensated by the control loop can be performed during the characterization process of the cells. Adding pessimism for VNW and VPW voltages has the effect that dynamic variation of the VNW and VPW voltages during system operation (e.g. caused by ripple of charge pumps) can be considered as pessimism ΔVNWa and ΔVNWa during characterization of the library. Additionally the variability of the performance monitor within the adaptive body biasing regulation hardware can be considered as effective mismatch of the resulting VNW and VPW voltages, described by ΔVNWm and ΔVPWm. This can be considered in the safety margins ΔVNW and ΔVPW by
ΔVNW=ΔVNWa+ΔVNWm and ΔVPW=ΔVPWa+ΔVPWm.

(9) In the fixed corners predefined in this way, the adaptation of the circuit properties by the dynamic adaptive control of the body bias voltages during operation is correctly modeled under all conceivable application scenarios. Using the existing worst case sign-off methodology and best-case assumptions, the correct functionality can be ensured during the design process, because the behavior of the adaptive control is fully contained in the corner definitions.

(10) Only absolutely necessary pessimisms in the static corner are considered, all other adaptively controllable properties are compensated by the body bias voltages. This enables the best possible implementation of the circuit.

(11) In case a characterization of the standard cell library is already available, the method of the invention can be applied to generate the target VNW and VPW values (including pessimisms) for the adaptive body bias operation. By means of library interpolation (supported by state-of the art design implementation tools), the library performance at the target corners by the invention can be generated by interpolation.

(12) FIG. 2 illustrates the body biasing and the adaption of the n-well bias and p-well bias for regulation of the performance of a cell. It shows the VNW (x-axis) and VPW (y-axis) plane. For a given performance (e.g. rising edge delay or falling edge delay of a clock inverter cell) its value depends on both VNW and VPW, and the PVT condition. As additional constraint, the match between two performances, e.g. rising edge delay of a clock inverter cell equals falling edge delay of a clock inverter cell can be defined. This results in a relation between VNW and VPW (drawn line) which must be fulfilled. An adaptive body bias regulation scheme (circuit) can meet this constraint adaptively during system operation.

(13) Fulfilling the nominal performance criterion at a typical PVT condition, as example, results in the nominal VNW VPW values.

(14) In case the PVT condition is slow for timing, the VNW/VPW voltages have: absolute higher values in case of forward body biasing (FBB), absolute lower values in case of reverse body biasing (RBB).

(15) In case the PVT condition is fast for timing, the VNW/VPW voltages have: absolute lower values in case of forward body biasing (FBB), absolute higher values in case of reverse body biasing (RBB).

(16) FIG. 3 shows an overview of the overall procedure of the inventive method for characterization of a standard cell with adaptive body biasing.

(17) The method for characterization of a standard cell with adaptive body biasing is carries out in several steps.

(18) In a first step a simulation of a selected cell set is performed, in order to generate a data-set for a performance F. This results in F(VDD, T, VNW, VPW, Process(ss,tt,ff,sf,fs)).

(19) Furthermore, a simulation of a hardware performance monitor output value C is performed, in order to generate a data-set C(VDD, T, VNW, VPW, Process(ss,tt,ff,sf,fs)).

(20) At the beginning of the method it is also possible to define PVT corners and to consider static and slow supply voltage variations by VDDc,PVT=VDD.sub.nom+/−x %, which results in PVT corners/Process, VDDc,PVT, Tc).

(21) In a second step of the method, the target performance at typical condition is determined by using the simulation results of the first step, and hence the nominal values of VNW and VPW are determined. This results in a target performance F0, a target reference value C0 for the regulation of the nominal values VNW and VPW for F0 at typical PVT conditions.

(22) In a further step, these results and the defined PVT corners are used for the virtual body biasing. With the virtual body biasing the target performance (VNWC0, VPWC0) for each PVT corner is determined to a) meet the reference performance F0 by using a numerical method on dataset from the first step of the method, and b) alternatively meet the reference hardware performance monitor value C0 by using the simulation results of the hardware performance monitor. The result of this step is (VNWC0, VPWC0) for each PVT corner.

(23) In a next step, pessimism for VNW and VPW is added, e.g. a charge pump ripple ΔVNWa, ΔVPWa is added or a hardware performance monitor mismatch/calculate VNW/VPW sensitivities ΔVNWm, ΔVPWm is added, whereas this results in (VNWC, VPWC) values for each PVT corner.

(24) Furthermore, a set of PVTBB corners for each said PVT corner with (Process, VDDc0,PVTBB, (VPWc0, VNWc0)Tc0)) and including an additional safety margin for VDD by VDDc,PVTBB=VDD.sub.nom+/−(x+y) %, whereas this results in PVTBB corner (Process, VDDc,PVTBB, (VPWc, VNWc)Tc)).

(25) The overall results of characterizing the cell with adaptive body biasing are provided in a library file.

(26) In a very preferred embodiment of the inventive method, the pessimism or safety margins of the bias voltages will be illustrated by two examples.

Example 1

(27) Two bias voltages for adaptive body biasing are considered: ΔV1=ΔVPWm (p-well voltage pessimism for hardware performance monitor) ΔV2=ΔVNWm (n-well voltage for hardware performance monitor), with ΔV1>0 and ΔV2>0 based on the inventive method for characterization of a standard cell, the safety margin is added to the nominal values of VNWc0 and VPWc0, additionally to the ΔVNWa and ΔVPWa actuator pessimism, which considers static and dynamic mismatch of the bias voltage actuators (e.g. charge pumps):

(28) Forward Body Biasing (FBB):
(VPW.sub.c,VNW.sub.c)=(VNW.sub.c0−ΔVNW.sub.a−ΔVNW.sub.s,VPW.sub.c0+ΔVPW.sub.a+ΔVPW.sub.m)  Slow timing:
(VPW.sub.c,VNW.sub.c)=(VNW.sub.c0,VPW.sub.c0)  Typical timing:
(VPW.sub.c,VNW.sub.c)=(VNW.sub.c0+ΔVNW.sub.a+ΔVNW.sub.m,VPW.sub.c0−ΔVPW.sub.a−ΔVPW.sub.m)  Fast timing:
Reverse Body Biasing (RBB):
(VPW.sub.c,VNW.sub.c)=(VNW.sub.c0+ΔVNW.sub.a+ΔVNW.sub.m,VPW.sub.c0−ΔVPW.sub.a−γVPW.sub.m)  Slow timing:
(VPW.sub.c,VNW.sub.c)=(VNW.sub.c0,VPW.sub.c0)  Typical timing:
(VPW.sub.c,VNW.sub.c)=(VNW.sub.c0−ΔVNW.sub.a−ΔVNW.sub.m,VPW.sub.c0+ΔVPW.sub.a+ΔVPW.sub.m)  Fast timing:

Example 2

(29) One regulated supply voltage VDD for adaptive voltage scaling is considered: ΔV.sub.1=ΔVDD (supply voltage), with ΔV.sub.1=ΔVDD>0, the safety margin is added to the nominal values of VDD.sub.0 as described:
(VDD)=(VDD.sub.0−ΔVDD)  Slow timing:
(VDD)=(VDD.sub.0)  Typical timing:
(VDD)=(VDD0+ΔVDD)  Fast timing:

(30) The invention allows to consider the adaptive bias voltages, e.g. VNW and VPW which are present in the operation of the circuit, e.g. when operated in a closed loop biasing scheme with hardware performance monitor, during cell characterization and implementation. Thereby, pessimisms are reduced and better power performance and area results can be obtained.