Capacitance reductions

11362603 · 2022-06-14

Assignee

Inventors

Cpc classification

International classification

Abstract

The disclosure relates to a method for reducing the torque ripple and noise evolution in an EC motor with single-phase feed by buffer-storing electrical energy in the EC motor, which is embodied with a power factor correction circuit (PFC) having a capacitor (Cz) at the power supply system input for a specific power supply system AC voltage UN, wherein the capacitance of the capacitor is dimensioned such that when the power supply system AC voltage UN is applied, a pulsating DC voltage is generated in a link circuit (Z), wherein the pulsating electrical energy generated as a result is stored by means of a primary regulation of the id current component as magnetic energy in the EC motor at least for a predefined time period.

Claims

1. A method for reducing torque ripple and noise evolution in an electronically commutated (EC) motor with single-phase feed and a power factor correction circuit (PFC) having a capacitor at a power supply system input for a specific power supply system AC voltage U.sub.N, the method comprising: dimensioning the capacitance of the capacitor (C.sub.Z) such that when the power supply system AC voltage U.sub.N is applied, a pulsating DC voltage is generated in a link circuit (Z); and buffer-storing electrical energy in the EC motor, wherein the pulsating electrical energy generated in the link circuit (Z) is stored by means of a primary regulation of an id current component as magnetic energy in the EC motor at least for a predefined time period.

2. The method according to claim 1, wherein the regulation for storing the energy comprises adjusting the field-generating id current component.

3. The method according to claim 1, wherein a trajectory-tracking, flatness-based, non-linear regulation in the state space is used for controlling the id current component.

4. The method according to claim 3, wherein a frequency of an id current trajectory is equivalent to double the power supply system frequency of the power supply system AC voltage U.sub.N, and wherein the frequency of the id current trajectory is synchronized with the power supply system frequency.

5. The method according to claim 1, wherein the amplitude and phase position of the id current component compared to those of the power supply system AC voltage U.sub.N are adjusted by a second id target value specification, which is superimposed on the primary regulation, such that the pulsation of the DC voltage generated in the link circuit (Z) is reduced or minimized.

6. The method according to claim 5, wherein, during the regulation, the amplitude of the id current component is selected to be a lowest amplitude within the available amplitude-phase position regulation field.

7. The method according to claim 1, wherein the amplitude of the id current component is set to a negative value to achieve a reduction of iron losses in the EC motor due to a resulting field weakening.

8. A circuit arrangement for an electronically commutated (EC) motor having a link circuit (Z) and which can be supplied with a single-phase feed, comprising: a. a power supply system input for connecting to at least one specific power supply system voltage U.sub.N, b. a power factor correction circuit (PFC) having a capacitor (C.sub.Z) on the side of the power supply system input, wherein the capacitance of the capacitor (C.sub.Z) is dimensioned such that when a power supply system voltage U.sub.N is applied, a pulsating DC voltage U.sub.ZK is generated in the link circuit (Z), c. a primary regulating device comprising a trajectory plan (TP) and a flatness-based state regulator (FZ) which is configured to regulate an id current component in such a manner that the pulsating electrical energy can be stored as magnetic energy in the EC motor at least for a predefined period of time.

9. The circuit arrangement according to claim 8, further comprising: d. a second regulation device that adjusts the amplitude (I.sub.A) and phase position of the id current component compared to those of the power supply system voltage U.sub.N.

10. The circuit arrangement according to claim 9, wherein the second regulation device provides a second regulation for adjusting the phase position and amplitude of the id current component and is configured such that the pulsation of a DC voltage generated in the link circuit (Z) is reduced or minimized.

11. An electronically commutated (EC) motor having the circuit arrangement according to claim 8.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other advantageous developments of the disclosure are characterized in the dependent claims and/or are explained in more detail in the following in conjunction with the description of the preferred embodiment of the disclosure based on the drawings. These show:

(2) FIG. 1 A schematic view of an EC motor according to the disclosure;

(3) FIG. 2 A representation of the progression of the id current over time; and

(4) In the following, the disclosure is described in more detail in reference to FIGS. 1 and 2 based on an exemplary embodiment of the disclosure.

DETAILED DESCRIPTION

(5) In this context, FIG. 1 shows a schematic view of an EC motor 1 for a ventilation fan. The EC motor 1 is connected to a circuit arrangement 1a comprising a link circuit Z (that is, the link circuitry Z) for generating the link circuit DC voltage U.sub.ZK, wherein the link circuit is embodied having a link circuit capacitor C.sub.Z. Furthermore, the circuit arrangement 1a has a power supply system input 2 and a rectifier 8. The link circuit Z is connected to the EC motor 1 via a commutation circuit 7. The link circuit Z carries the nominal voltage U.sub.ZK in its nominal operation, which voltage is generated by the power supply system input circuit 2a and the rectifier 8. A power factor correction circuit (PFC) is provided upstream of the link circuit Z.

(6) Herein, the capacitance of the capacitor C.sub.Z is dimensioned such that when a power supply system AC voltage U.sub.N is applied, a pulsating DC voltage is generated in the link circuit Z.

(7) To reduce the AC voltage components in the pulsating DC voltage, a primary regulation device 4 and a secondary, or additional, regulation device 5 are embodied to regulate the motor current. Therein, the regulation 4 considers an id target value specification id-S, a target motor speed w and a trajectory plan TP, in which the motor speed target, the id current progression and the rotation angle DW are used as parameters. Out of these, the trajectory parameters TP.sub.P are generated, which then are transferred to a flatness-based state regulator FZ with monitor. Following a Clark/Park transformation C/P, the flatness-based state regulator FZ with monitor receives the values id-Mess and iq-Mess. The voltage values U.sub.d and U.sub.q, are transferred from the flatness-based state regulator FZ to the Clark-Park control element P/C, which additionally processes values such as angle position, as well as plus and minus of the link circuit voltage U.sub.ZK, to obtain the voltage values U.sub.a, U.sub.b and U.sub.c from the same. These are transferred to the motor via a three-phase current measurement SM. The three-phase current measurement SM therein transfers the current value I.sub.abc back to the C/P control element.

(8) Thus, the regulation of the id current component is performed in such a manner that the pulsating electrical energy can be stored as magnetic energy in the EC motor 1 at least for a predefined period of time.

(9) Furthermore, the regulation 5 serves to adjust the amplitude I.sub.A (as shown in FIG. 2) and phase position of the id current compared to those of the power supply system voltage U.sub.N, wherein the generated pulsating electrical energy is stored as magnetic energy in the EC motor 1 via the regulation of the id current component by means of the primary regulation 4. The undesirable pulsation of the motor torque caused by the pulsation of the DC current, due to an intentionally undersized capacitance value of the capacitor, can be compensated for by the control 4, 5 of the id current. The id current progression required for this is shown in FIG. 2, wherein only negative current impulses are generated.