Backup power supply system

Abstract

A balancing system for balancing respective voltages of N consecutively connected capacitors during charging or discharging includes balancing units, each having a pair of associated switches and an electromagnetic coil. An inter-switch junction is connected to an inter-capacitor junction of a corresponding group of capacitors through the electromagnetic coil. A control and generation circuit generates PWM control signals and transmits a generated PWM control signal to each of the switches. The PWM control signals have fixed duty cycles that do not vary temporarily during charging or discharging of the N capacitors. The duty cycles of two PWM control signals transmitted to two associated switches are complementary for each balancing unit.

Claims

1. A backup power supply system, comprising: a stack of N consecutively connected capacitors grouped in y groups each including at least two consecutive capacitors, wherein y<N−1; and a balancing system for balancing respective voltages of the N consecutively connected capacitors during charging or discharging of said N consecutively connected capacitors, said balancing system comprising: a plurality of balancing units for the y groups of capacitors, respectively, each balancing unit comprising a pair of associated switches connected through an inter-switch junction and an electromagnetic coil, said inter-switch junction being connected to an inter-capacitor junction of the corresponding group of capacitors through said electromagnetic coil; and a control and generation circuit for generating PWM control signals and transmitting a generated PWM control signal to each of the switches; wherein: the control and generation circuit is configured to generate PWM control signals having fixed duty cycles that do not vary temporarily during charging or discharging of the N consecutively connected capacitors, the duty cycles of two PWM control signals to be transmitted to two associated switches are complementary for each balancing unit, the control and generation circuit includes a plurality of n flip-flops, and n is an integer determined from the number N of capacitors according to the relation 2.sup.n-1<N≤2.sup.n.

2. The backup power supply system according to claim 1, wherein the stack of N consecutively connected capacitors has two terminals and each pair of associated switches is connected to said terminals of the stack of N consecutively connected capacitors.

3. The backup power supply system according to claim 2, wherein the N consecutively connected capacitors have respective indices i, i is from 1 to N, and for each balancing unit having an inter-capacitor junction between two capacitors of respective indices i and i+1 connected to the inter-switch junction, the control and generation circuit is configured to generate a first PWM control signal having a duty cycle equal to (N−i)/N and a second PWM control signal having a duty cycle equal to i/N.

4. The backup power supply system according to claim 1, wherein, for each balancing unit, the pair of associated switches is connected to two terminals of the corresponding group of capacitors.

5. The backup power supply system according to claim 4, wherein the control and generation circuit is configured to generate PWM control signals that all have a duty cycle of 50%.

6. The backup power supply system according to claim 1, wherein each group of capacitors includes only two capacitors.

7. The backup power supply system according to claim 1, wherein the control and generation circuit includes a flip-flop based frequency divider.

8. The backup power supply system according to claim 7, wherein the control and generation circuit is configured to be connected to a power source and be provided with a clock signal from said power source.

9. The backup power supply system according to claim 1, wherein the control and generation circuit includes logical gates.

10. The backup power supply system according to claim 1, comprising a power source that is configured to: produce a fixed charge current, during a first charging phase; and during a second charging phase, after the voltage of the stack of N consecutively connected capacitors has reached a predetermined target value, produce a charge current modulated to maintain the voltage of the stack of N consecutively connected capacitors at the predetermined target value.

11. The backup power supply system according to claim 1, wherein the stack of N consecutively connected capacitors are configured to supply power to an electrical circuit of a vehicle when an electrical battery of the vehicle is temporarily disconnected from the electrical circuit.

12. A vehicle comprising the backup power supply system according to claim 1, wherein the backup power supply system is configured to be charged from a power source comprising an electrical battery of the vehicle and to supply power to an electrical circuit of the vehicle.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other features, purposes and advantages of the disclosure will become more explicit by means of reading the detailed statement of the non-restrictive embodiments made with reference to the accompanying drawings.

(2) FIG. 1 shows a schematic and simplified representation of a first exemplary embodiment of the backup power supply system having two capacitors and a pair of associated switches.

(3) FIG. 2 shows schematically a second exemplary embodiment of the backup power supply system, having four capacitors and three pairs of associated switches.

(4) FIG. 3A shows simulation results of the capacitor voltages converging when charging and balancing the backup power supply system of FIG. 2.

(5) FIG. 3B shows PWM control signals transmitted to switches of the backup power supply system in the simulation of FIG. 3A and the capacitor voltages, after convergence (between 29.950 ms and 30 ms after start of the balancing operation).

(6) FIG. 4 shows a third exemplary embodiment of the backup power supply system, having three capacitors and two pairs of associated switches.

(7) FIG. 5 shows a fourth exemplary embodiment of the backup power supply system, having three capacitors and two pairs of associated switches, that is an alternative embodiment to embodiment of FIG. 4.

(8) FIG. 6 shows a fifth exemplary embodiment of the backup power supply system, having N capacitors and N−1 pairs of associated switches, N being an odd number;

(9) FIG. 7 shows a sixth embodiment of the backup power supply system, having N capacitors and N−1 pairs of associated switches, N being an even number.

(10) FIG. 8 shows a seventh exemplary embodiment of the backup power supply system, having N capacitors and N−1 pairs of associated switches (only a part the N capacitors and N−1 pairs of switches being represented for the sake of clarity), during charging of the capacitors from a power source.

(11) FIG. 9 shows the seventh exemplary embodiment of the backup power supply system of FIG. 8, during discharging of the capacitors to supply a load (or device).

(12) FIG. 10 shows an exemplary embodiment of a circuit for generating PWM control signals controlling the switches of the backup power supply system of FIG. 2.

(13) FIG. 11 shows an exemplary embodiment of a power supply system of the prior art, having a power source connected in parallel to a plurality of serially connected capacitors for buffering energy, supplying a load P.

(14) FIG. 12 shows a first exemplary embodiment of a balancing circuit for capacitors of a power supply system, of the prior art.

(15) FIG. 13 shows a second exemplary embodiment of a balancing circuit for capacitors of a power supply system, of the prior art, that is an improved variant of the first exemplary embodiment of FIG. 12.

(16) FIG. 14 shows a third exemplary embodiment of an improved balancing circuit for capacitors of a power supply system, of the prior art.

DETAILED DESCRIPTION

(17) Beforehand, it is stated that the same, analogous or corresponding elements represented on different figures have the same reference, unless otherwise stated.

(18) The present disclosure concerns a backup power supply system 100 that can be used, for example in a vehicle, as an energy reserve available to be used when it is needed, for example when a battery power supply is interrupted due to a disconnection of the battery. The backup power supply system 100 is charged from a power source 200, for example an electrical battery (typically a 12V battery) in a vehicle. When the battery power supply is interrupted, the backup power supply is discharged in order to supply current to one or more loads, that are electrical devices of the vehicle.

(19) The backup power supply system 100 has a set or stack 10 of N capacitors C1, C2, . . . , Ci, . . . , CN that are serially connected and a balancing circuit 20 for balancing the respective voltages of the N capacitors during charging or discharging of the N capacitors.

(20) In an example embodiment, the capacitors C1, C2, . . . , Ci, . . . , CN are supercapacitors.

(21) A number of n groups of at least two consecutive capacitors, with n≤N−1, are defined from the N capacitors 10. Conventionally, an index j designates the index of a group of at least two capacitors with 1≤j≤n in the present description.

(22) For each group of capacitors of index j, the balancing circuit 20 has a pair of associated and serially connected switches. The pairs of associated switches are referenced as SWj1 and SWj2 with 1≤j≤n (namely SW11, SW12, . . . , SWj1, SWj2, . . . , SWn1, SWn2) in the figures. An inter-switch junction, or node, related to each pair of associated switches (that is the junction or node between the two switches) is connected to an inter-capacitor junction, or node, related to said group of capacitors (that is a junction or node between two capacitors of the same group) through an electromagnetic coil L1, . . . , Lj, . . . , Ln. The group including:

(23) one group of index j having at least two capacitors,

(24) the corresponding pair of associated switches SWj1 and SWj2 and

(25) the corresponding electromagnetic coil Lj

(26) form a balancing unit named BUj in the description.

(27) The backup power supply system 100 also includes a control and generation circuit 30 for generating PWM (Pulse Width Modulation) control signals PWMj1, PWMj2 and transmitting a generated PWM control signal PWMj1, PWMj2 to each of the switches SWj1, SWj2, with 1≤j≤n, in order to control the switches. In the present disclosure, the control and generation circuit generates PWM control signals PWMj1, PWMj2 having fixed duty cycles.

(28) The expression “fixed duty cycles” means that the respective duty cycles do not vary temporarily during charging or discharging of the N capacitors. In other words, the duty cycles of the control signals used to turn on/off the switches are constant over time during charging or discharging.

(29) For each balancing unit BUj, the two generated PWM control signal PWMj1, PWMj2 are complementary (PWMj1=PWMj2), which means that the first signal PWMj1 is ON (or high level) when the second signal PWMj2 is OFF (or low level). So, the sum of the fixed duty cycles DC of the two PWM control signals PWMj1 and PWMj2 (respectively transmitted to two associated switches SWj1 and SWj2 with 1≤j≤n) is equal to 100%.

(30) The backup power supply system 100 operates the switches according to a switching frequency f.sub.sw. For example, the backup power supply system 100 uses a clock signal from the power source 200 (for example a power DCDC converter) as a basis frequency f.sub.b to control the switches. For a stack of N capacitors, the switching frequency f.sub.sw is equal to the basis frequency f.sub.b divided by N: f.sub.sw=f.sub.b/N. This configuration provides the advantage that there is no need to generate a frequency. As a result, the amount of resources or components can be reduced. Alternatively, an external basis frequency generator can be used. In that case, the frequency is advantageously determined according to a desired switching frequency for balancing the capacitors: f.sub.b=f.sub.sw.Math.N.

(31) When the capacitors are being charged, they are connected to a power source 200. More precisely, the two terminals of the stack of N serially connected capacitors are connected to the two terminals of the power source 200. Conventionally, the capacitor of index 1 is connected to the positive terminal of the power source 200 and the capacitor of index N is connected to the negative terminal of the power source 200 (for example connected to the ground). The references u_total and i_charge designate the voltage and the electrical current provided by the power source 200. When the capacitors are used to supply one or more loads, the connection with the power source 200 is interrupted and the stack of N serially connected capacitors is connected to the load(s).

(32) During charging (or discharging) of the N stacked capacitors, for each balancing unit BUj balancing a group of capacitors, an imbalance between the respective capacitor voltages of the different capacitors within the group causes an electrical current i_bal through the coil Lj. This electrical current i_bal allows to balance the capacitor voltages. The basic principle is that the capacitor having the highest voltage discharges into the capacitor having the smallest voltage (in case the group has two capacitors).

(33) We first assume that the N serially connected capacitors are grouped by two and two adjacent groups of two capacitors have one middle capacitor in common. It means that N−1 groups of two consecutive connectors are defined.

(34) FIG. 1 shows a schematic representation of the backup power supply system 100 according to a first exemplary embodiment that is very simplified. In this simplified embodiment, the backup power supply system 100 has only one balancing unit BU. More precisely, the backup power supply system 100 has only two capacitors C1, C2 and a pair of two associated switches SW1, SW2, connected to one another through a interswitch junction. The two switches SW1 and SW2 are connected “in parallel” to the two capacitors C1, C2 (i.e., the two terminals of the pair of switches SW1, SW2 are respectively connected to the two terminals of the stack of capacitors C1, C2), but the inter-capacitor junction between the two capacitors C1 and C2 and the inter-switch junction between the two switches SW1, SW2 are connected through a coil L. The backup power supply system 100 has also a control and generation circuit 30 that generates two PWM control signals PWM1 and PWM2 and transmits them to the two switches SW1 and SW2, respectively, in order to control them. The respective duty cycles DC of these two PWM control signals PWM1 and PWM2 are fixed and both equal to 50%. In order to charge the two capacitors C1 and C2, the balancing unit BU is connected to a power source 200, as represented in FIG. 1 (the BU is connected to the terminals of the power source 200). The control and generation circuit 30 can also be connected to the power source 200 and supplied by it.

(35) During the operation of charging the capacitors C1, C2 through the balancing circuit 20, the capacitor voltages converge to the same value of u_total/2, u_total being the voltage of the power source 200, within a short period of time, inferior to one second, as will be explained in more detail later in the description. In FIG. 1, the reference i_bal12 represents the current through the coil when the top capacitor C1 discharges into the bottom capacitor C2, and the reference i_bal21 represents the current through the coil when the top capacitor C2 discharges into the bottom capacitor C1.

(36) FIG. 2 shows a schematic representation of the backup power supply system 100 according to a second exemplary embodiment.

(37) In the second exemplary embodiment, the backup power supply system 100 has a stack of four capacitors C1, C2, C3 and C4 (N=4), serially (i.e., consecutively) connected, and three pairs of associated switches SW11-SW12, SW21-SW22, SW31-SW32. Each pair of switches SW11-SW12 (SW21-SW22 and SW31-SW32) is connected ‘in parallel’ to the stack of capacitors C1-C4 (i.e., the two terminals of each pair of switches SW11-SW12, SW21-SW22, SW31-SW32 are respectively connected to the two terminals of the stack of capacitors C1-C4). The three inter-capacitor junctions are connected to the three inter-switch junctions of the three pairs of switches SW11-SW12, SW21-SW22, SW31-SW32 through three coils L1, L2 and L3, respectively.

(38) A control and generation circuit (not represented in FIG. 2) generates PWM control signals with fixed duty cycles to control the switches SW11-SW12, SW21-SW22, SW31-SW32. The values of the duty cycles for controlling SW11-SW12, SW21-SW22, SW31-SW32 are as follows:

(39) DC11=75%, DC12=25%

(40) DC21=50%, DC22=50%

(41) DC31=25%, DC32=75%

(42) so as to set the voltages of the junction nodes between C1 and C2, between C2 and C3 and between C3 and C4 to 75%. u_total, 50%. u_total and 25%. u_total, respectively, after balancing.

(43) FIG. 3A shows a simulation result of the evolution over time of the capacitor voltages u_C1, u_C2, u_C3, u_C4 of the four capacitors C1, C2, C3 and C4 when these capacitors are charged from the power source 200, through the balancing circuit 20. For the simulation, the voltage u_total of the power source 200 is for example set to 7.2V. Consequently, a target value of the capacitor voltage for each of the capacitors C1, C2, C3 and C4 is equal to 1.8V (7.2V divided by 4).

(44) Initially, the capacitor voltages u_C1, u_C2, u_C3, u_C4 are for example equal or close to zero. The time evolutions of the different capacitor voltages u_C1, u_C2, u_C3, u_C4 are analogous, but not identical as the capacitors have different capacitance values.

(45) The charging operation has two main phases: a first quick phase I and a second slow phase II. The first quick charging phase I has a first (or initial) part T1 during which there is no balancing. The capacitor voltages u_C1, u_C2, u_C3, u_C4 start increasing but diverge, which means that they become more and more different from one another, due to the lack of balancing. This phenomenon is due to the fact that the balancing circuit 20 needs that a certain amount of voltage be reached, for example a voltage threshold of around 3 or 4 V at the terminals of the stack of the N serial capacitors, in order for the switches to start working. However, depending on the technology used for the switches, the latter may work before reaching this N-capacitor voltage threshold.

(46) As soon as the balancing starts, the capacitor voltages u_C1, u_C2, u_C3, u_C4 converge, which means that they come closer to each other. This corresponds to a second and subsequent part T2 of the quick charging phase I. Then, as soon as the maximum total voltage u_total across the capacitor stack is reached (7.2V in the present example), the slow phase II starts. During the slow phase II, the capacitor voltages u_C1, u_C2, u_C3, u_C4 across the different capacitors increase more slowly or decrease a little and converge to a common voltage. As can also be seen in FIG. 3A, the capacitor voltages u_C1, u_C2, u_C3, u_C4 of all capacitors C1 to C4 reach and keep a value equal or very close to the target value of 1.8V after a short time period of around 15 ms.

(47) In the exemplary embodiment of FIG. 3A, during the first phase I of charging, the power source 200 produces a fixed charge current. During the second phase II of charging, after the voltage of the N stacked capacitors has reached the predetermined target value (u_total), the power source 200 produces a charge current that is modulated or regulated in order to maintain the voltage of the N stacked capacitors at the predetermined target value (u_total).

(48) FIG. 3B shows the PWM control signals PWM11, PWM21 and PWM31, transmitted to switches SW11, SW21 and SW31 respectively, and the time evolutions of the capacitor voltages u_C1, u_C2, u_C3, u_C4, during a time period between 29,950 ms and 30 ms (from the beginning of the charging operation). FIG. 3B shows that, after a period of time of around 30 ms from the start of the charging operation, all capacitor voltages u_C1, u_C2, u_C3, u_C4 have reached and maintain voltage value equal to the capacitor voltage target value (1.8V) with an accuracy of around 2 or 3%.

(49) The balancing circuit 20 allows that each of the N stacked capacitors reaches the target voltage value in a fast, accurate and efficient manner.

(50) FIG. 4 shows a third exemplary embodiment that only differs from the second exemplary embodiment in that the stack of capacitors has only three serially connected capacitors C1, C2, C3 and two pairs of associated switches SW11-SW12 and SW21-SW22. The inter-switch junctions are connected to the two inter-capacitor junctions through two coils L1, L2, respectively.

(51) In some exemplary embodiments (such as the second and third exemplary embodiments), each pair of associated switches is connected ‘in parallel’ to a stack of N serially connected capacitors (i.e., the two terminals of each pair of switches are connected to the two terminals of the N stacked capacitors, respectively). For each balancing unit BUj, the inter-switch junction between SWj1 and SWj2 is connected to an inter-capacitor junction between two capacitors of respective indices i and i+1 of the same group j through the coil Lj, and the control and generation circuit 20 generates a first PWMj1 control signal having a duty cycle equal to (N−i)/N and a second PWMj2 control signal having a duty cycle equal to i/N.

(52) In other exemplary embodiments (that are a variant of the above embodiments), for each balancing unit BUj associated with the group j of at least two capacitors, the pair of associated switches SWj1-SWj2 is connected in parallel to the group j of stacked capacitors. When n groups of at least two consecutive capacitors are defined from the N capacitors, n pairs of associated switches are connected ‘in parallel’ the n groups of capacitors, respectively. In addition, for each balancing unit BUj associated with the group j of at least two capacitors, the inter-switch junction between SWj1 and SWj2 is connected to an inter-capacitor junction between two capacitors of respective indices i and i+1 of the group j through a coil Lj. In these variant embodiments, the control and generation circuit generates PWM control signals that all have a fixed duty cycle of 50% for all the switches SWj1-SWj2 with 1≤j≤n.

(53) FIG. 5 is a fourth exemplary embodiment, according to the above disclosed variant. More precisely, the embodiment of FIG. 5 is a variant of the embodiment of FIG. 4 according to the above paragraph. In this FIG. 5, the stack of capacitors has three serially connected capacitors C1, C2, C3 and two pairs of associated switches SW11-SW12 and SW21-SW22 balances the capacitor voltages. More precisely, the pair of switches SW11-SW12 is connected ‘in parallel’ to the two capacitors C1, C2 (i.e., the two terminals of the pair of switches SW11-SW12 are connected to the two terminals of the capacitors C1-C2) and the pair of switches SW21-SW22 is connected ‘in parallel’ to the two capacitors C2, C3 (i.e., the two terminals of the pair of switches SW21-SW22 are connected to the two terminals of the capacitors C2-C3). The inter-switch junctions are connected to the inter-capacitor junctions through the coils L1 and L2. The duty cycles of all PWM control signals transmitted to switches SW11-SW12 and SW21-SW22 are fixed and equal to 50%.

(54) FIG. 6 shows a fifth exemplary embodiment that is a generalization of the fourth embodiment of FIG. 5, with a number N of serially connected (stacked) capacitors, N being an odd number. For each balancing unit BUj, the pair of associated switches SWj1-SWj2 is connected ‘in parallel’ to the corresponding group of two capacitors (i.e., the two terminals of switches SWj1-SWj2 are connected to the two terminals of the corresponding group of two capacitors) and the inter-switch junction is connected to the inter-capacitor junction through a coil Lj. There are N−1 coils that connect each of the N−1 inter-capacitor junctions to N−1 inter-switch junctions belonging to the N−1 pairs of associated switches SWj1-SWj2 with 1≤j≤N−1, respectively.

(55) FIG. 7 shows a sixth embodiment that only differs from the sixth embodiment in that the number N of serially connected (stacked) capacitors is an even number.

(56) FIG. 8 shows a seventh exemplary embodiment that is a generalization of the embodiments of FIGS. 2 and 4, with a number N of serially connected (stacked) capacitors. The N serially connected capacitors have respective indices i from 1 to N. The capacitor C1 is connected to the positive terminal of the power source 200 and the capacitor CN is connected to the negative terminal of the power source 200 (here to the ground). For each balancing unit BUj, the pair of associated switches SWj1-SWj2 is connected ‘in parallel’ to the N serially connected (stacked) capacitors (i.e., the two terminals of the pair of associated switches SWj1-SWj2 are connected to the two terminals of the N stacked capacitors) and the inter-switch junction between SWj1 and SWj2 is connected to an inter-capacitor junction through a coil Lj. When the inter-capacitor junction between capacitors Ci and Ci+1 are connected to the inter-switch junction between SWj1 and SWj2, a first PWM control signal having a duty cycle equal to (N−i)/N is generated and transmitted to a first of the two associated switches SWj1 and a second PWM control signal having a duty cycle equal to i/N is transmitted to the second of the two associated switches SWj2. The first switch SWj1 is connected to the positive terminal of the power source 200 and the second switch SWj2 is connected to the negative terminal of the power source 200 (here connected to the ground).

(57) FIG. 9 shows the backup power supply system according to the seventh embodiment of FIG. 8, during discharging of the N capacitors in order to supply a load P. The connection of the stack of N capacitors to the power source is interrupted and the capacitors discharge into the load. The balancing circuit allows to balance the respective voltages of the N capacitors during discharging of the N capacitors.

(58) In an eighth exemplary embodiment of the backup power supply system, n groups of two or more capacitors are defined from the N capacitors and at least part of the n groups have more than two capacitors. Such embodiment is appropriate when the number N of capacitors is important.

(59) According to the present disclosure, the control and generation circuit generates PWM control signals having fixed duty cycles, which allows to balance quickly the capacitor voltages of the N serially connected capacitors without feedback loop.

(60) In some exemplary embodiments, each pair of associated switches are connected ‘in parallel’ to the N serially connected capacitors. In other exemplary embodiments, j pairs of associated switches are connected ‘in parallel’ to j groups of at least two capacitors.

(61) The generation of these PWM control signals having fixed duty cycles can be achieved using flip-flops and logical gates. The control and generation circuit uses a clock signal that is transmitted from the power source. The flip-flops operate as frequency dividers. A number of x flip-flops allows to generate the duty-cycles of a maximum of 2.sup.x capacitors connected in series. More generally, the control and generation circuit 30 has a number of n flip-flops, wherein n is determined from the number N of capacitors according to the relation 2.sup.n-1<N≤2.sup.n.

(62) FIG. 11 shows an exemplary embodiment of a circuit for generating three PWM control signals having respective duty cycles of 25%, 50% and 75%. Such a circuit is well-known by the skilled person and will not be described in more detail.

(63) The generation of PWM control signals having one common duty cycle of 50% allows to use a control and generation circuit that is simple, has smaller components and produces less current ripple.

(64) The reduction of the current ripple is noticeable in particular when the basis frequency, used to control the switches and balance the capacitors, is provided by the power source 200. For example, for a stack of four capacitors C1 to C4, a plurality of PWM control signals having respective duty-cycles of 25%, 50% and 75% are generated, which implies to divide the basis frequency by four in order to obtain the switching (or balancing) frequency. The generation of PWM control signals produces a higher current ripple for a lower frequency. The generation of PWM control signals having only a 50% duty-cycle only needs to divide the basis frequency by two. Therefore, through the higher switching frequency (basis frequency divided by two) of the balancing circuit, less current ripple is produced. When an external basis frequency generator is used and its frequency is determined according to the desired switching frequency for balancing the capacitors, there is no noticeable difference of current ripple.

(65) As previously indicated, the backup power supply system 100 is for example integrated in a vehicle and supplies power to an electrical circuit of the vehicle. In such a case, the power source 200 is an electrical battery of the vehicle, such as a 12V battery. The N serially connected capacitors supply power to the electrical circuit of the vehicle when the electrical battery of the vehicle is temporary disconnected from the electrical circuit.

(66) The present disclosure also concerns the balancing circuit 20 for balancing respective voltages of N serially connected capacitors of a backup power supply system, during charging or discharging of said N capacitors, n groups of at least two consecutive capacitors, with n≤N−1, being defined from the N capacitors, as previously described.

(67) In particular, the balancing circuit 20 has, for each group of capacitors, a pair of associated and connected switches with an inter-switch junction that is connected to an inter-capacitor junction of said group of capacitors through an electromagnetic coil, said group of capacitors, said pair of associated switches and said electromagnetic coil forming a balancing unit; and a control and generation circuit for generating PWM control signals and transmitting a generated PWM control signal to each of the switches, that generates PWM control signals having fixed duty cycles.

(68) The duty cycles of two PWM control signals transmitted to two associated switches are complementary for each balancing unit.

(69) The present disclosure also concerns a vehicle integrating the backup power supply system and/or the balancing circuit previously described.

(70) The preceding description is illustrative rather than limiting in nature. Variations and modifications to the disclosed example embodiments may become apparent to those skilled in the art that do not necessarily depart from the essence of the invention. The scope of legal protection given to the invention can only be determined based on the following claims.