Method for Contacting and Packetising a Semiconductor Chip

Abstract

A method for contacting and packaging a semiconductor chip of a power electronic component. The power electronic component has a first contact face produced in a first step via a multi-material printing process and a semiconductor chip, which is placed in a second step onto the first contact face. A ceramic insulation layer, which surrounds the semiconductor chip along its circumference and extends over the first contact face not covered by the semiconductor chip, is printed in a third step onto the first contact face. A second contact face is printed in a fourth step onto the ceramic insulation layer and the semiconductor chip. In a fifth step, the power electronic component is sintered by means of heat treatment.

Claims

1. Method for contacting and packaging a semiconductor chip (2) of a power electronic component, wherein the power electronic component has a first, lower contact face (1) and a semiconductor chip (2) positioned thereon, characterized in that a ceramic insulation layer (3), which surrounds the semiconductor chip (2) along its circumference and extends over the first contact face (1) not covered by the semiconductor chip (2), is printed onto the lower contact face (1), and in that a second, upper contact face (4) is printed onto the ceramic insulation layer (3) and the semiconductor chip (2), wherein the first and second contact face (1, 4) and the ceramic insulation layer (3) are created in a printing process by means of a 3D multi-material printer such that in a first method step the first contact face (1) is produced by means of the multi-material printing process, in a second method step the semiconductor chip (2) is placed onto the first, lower contact face (1), in a third method step a ceramic insulation layer (3), which surrounds the circumference of the semiconductor chip (2), is printed onto the first contact face 1), in a fourth method step the second contact face (4) is printed onto the ceramic insulation layer (3) and the semiconductor chip (2), in a fifth method step the power electronic component is sintered by means of heat treatment.

2. Method according to one of claim 1, characterized in that the height of the ceramic insulation layer (3) substantially corresponds to the height of the semiconductor chip (2).

3. Method according to claim 1, characterized in that a cutout (5) for an additional connection (6) is made in the second contact face (4).

4. Method according to claim 3, characterized in that the connection (6) is surrounded at the edges by the ceramic insulation layer (3) and is insulated from the second contact face (4).

5. Method according to claim 1, characterized in that the first contact face (1) and or second contact face (4) is produced from a conductive material.

6. Method according to claim 1, characterized in that, in a further method step, a housing for the semiconductor chip (2) is created by means of the printing process, with cooling functionalities being introduced into the housing.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In the drawings:

[0034] FIG. 1 shows a schematic illustration of the layer structure of the power electronic component.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0035] The power electronic component H in accordance with the method according to the invention is shown in FIG. 1. The power electronic component has a first, lower contact face 1 and a semiconductor chip 2 arranged thereon, preferably by means of a “pick and place” method. The lower contact face 1 is produced from copper, in particular by means of 3D multi-material printing.

[0036] Extending over the first, lower contact face 1 is a ceramic insulation layer 3 which is applied by means of the printing process, said layer surrounding the semiconductor chip 2 along its circumference and embedding it in the insulation layer 3. The insulation layer 3 extends over the area of the contact face 1 that is not covered by the semiconductor chip 2.

[0037] The ceramic insulation layer 3 substantially has a height corresponding to the height of the semiconductor chip 2, thereby creating a flat surface. A second, upper contact face 4 is arranged on the ceramic insulation layer 3 by means of the 3D multi-material printing process.

[0038] As shown in FIG. 1, the second contact face 4 has a cutout 5, which is designed in the form of an additional connection 6 or contact. The cutout 5 is insulated from the upper, second contact face 4 by means of the ceramic insulation layer 3, which surrounds the circumference of said cutout. The ceramic insulation layer 3 extends around the connection 5 in some regions, encapsulating it up to the height of the upper side of the upper contact face 4. Either one or multiple cutouts 5 may be provided in the upper contact face 4.

[0039] The cutout 5 and the ceramic insulation layer 3 may be applied together with the second contact face 4 in one method step. An additional connection 6 thus created is important for power electronic components. In this way, one or multiple connections 6 in the form of gate contacts can be created when producing a field-effect transistor.

LIST OF REFERENCE NUMERALS

[0040] 1 first, lower contact face [0041] 2 semiconductor chip [0042] 3 ceramic insulation layer [0043] 4 second, upper contact face [0044] 5 cutout [0045] 6 additional connection [0046] H power electronic component