SELECTOR DEVICE, RESISTIVE TYPE MEMORY DEVICE AND ASSOCIATED MANUFACTURING METHOD

Abstract

A selector device intended to select a resistive memory cell includes a first selector device including a first active material and a second selector device including a second active material, the first selector device and the second selector device being connected in parallel.

Claims

1. A selector device configured to select a resistive memory cell, comprising a first selector device comprising a first active material and a second selector device comprising a second active material, the first selector device and the second selector device being connected in parallel, the first selector device being configured to supply an electric current adapted to a reading of a state of the resistive memory cell and the second selector device being configured to supply an electric current adapted to a writing of a state of a resistive memory cell

2. The selector device according to claim 1, wherein the first active material has a first threshold voltage for the passage of an electric current and the second active material has a second threshold voltage for the passage of an electric current, the first threshold voltage being lower than the second threshold voltage.

3. The selector device according to claim 1, wherein the first selector device is a diode.

4. The selector device according to claim 1, wherein the second selector device is an ovonic threshold switch or a field assisted superlinear threshold selector or a mixed ionic electronic conduction selector.

5. The selector device according to claim 1, wherein the second selector device arranged to surround the first selector device.

6. The selector device according to claim 1, wherein the second selector device further comprises a first electrode of the second selector device and wherein the first electrode of the second selector device and the second active material surround the first selector device.

7. The selector device according to claim 6, wherein the first electrode of the second selector device comprises a first and a second part of first electrode, the second active material comprises a first and a second part of active material, the first parts forming a first angle with a plane of the layers of the first selector device and the second parts forming a second angle with a plane of the layers of the first selector device.

8. The selector device according to claim 7, wherein the first parts are substantially normal to the plane of the layers of the first selector device and the second parts are substantially parallel to the plane of the layers of the first selector device.

9. A memory device comprising the selector device according to claim 1 and a resistive memory cell, the selector device and the resistive memory cell being connected in series.

10. The memory device according to claim 9, comprising a single memory cell.

11. The memory device according to claim 9, comprising two memory cells each resistive memory cell being connected in series with the selector device.

12. The memory device according to claim 9, wherein the first selector device is a front end device and the second selector device is a back end device.

13. A method for manufacturing a selector device configured to select a resistive memory cell, the method comprising: depositing a first set of layers comprising a first and a second electrode layer of a first selector device and a layer of a first active material of the first selector device; depositing a second set of layers comprising a first and a second electrode layer of a second selector device and a layer of a second active material of a second selector device; electrically connecting the first electrode layer of the first set of layers and the first electrode layer of the second set of layers, and electrically connecting the second electrode layer of the first set of layers and the second electrode layer of the second set of layers.

14. The method for manufacturing a selector device according to claim 13, further comprising: depositing an electrically conductive layer configured to connect electrically the first electrode layer of the first set of layers and the first electrode layer of the second set of layers, and depositing the second electrode layer of the second selector device, the second electrode layer of the second selector device being electrically connected to the second electrode layer of the first set of layers.

15. The method for manufacturing a selector device according to claim 13, further comprising etching the first set of layers.

16. The method for manufacturing a selector device according to the claim 15, wherein the deposition of the second set of layers further comprises etching the layers of the second set, the layers of the second set surrounding after etching the layers of the first set.

17. The method for manufacturing a selector device according to claim 15, further comprising depositing and etching a dielectric layer, the dielectric layer surrounding after etching the first set of layers.

18. The method for manufacturing a selector device according to claim 15, further comprising depositing a third set of layers comprising a resistive memory cell active material and a resistive memory cell electrode.

19. The method for manufacturing a selector device according to the claim 18, wherein the deposition of the third set of layers is carried out so as to arrange the third set of layers in contact with the electrically conductive layer intended to connect the first electrode layer of the first set of layers and the first electrode layer of the second set of layers.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0064] The figures are presented for indicative purposes and in no way limit the invention.

[0065] FIG. 1 represents an electric current applied voltage characteristic for a backend type selector;

[0066] FIG. 2 represents a memory device known to those skilled in the art comprising a resistive memory cell connected in series to a diode type selector:

[0067] FIG. 3 represents an electric current applied voltage characteristic for a 1S1R type memory device comprising a resistive memory cell and a selector device;

[0068] FIG. 4 schematically represents an embodiment of the memory device according to the invention comprising the selector device according to the invention;

[0069] FIG. 5 represents an embodiment of the selector device according to the invention;

[0070] FIG. 6 represents an electric current applied voltage characteristic for a polycrystalline silicon diode;

[0071] FIG. 7 represents an electric current applied voltage characteristic for an ovonic threshold switch or OTS;

[0072] FIG. 8 represents an electric current applied voltage characteristic for the memory device according to the invention;

[0073] FIGS. 9 and 9b schematically represent a sectional view of the memory device according to the invention;

[0074] FIG. 10 schematically represents the method for manufacturing a selector device according to the invention;

[0075] FIGS. 11a to 11f represent sectional views of the results obtained after each step of the manufacturing method according to the invention;

[0076] FIG. 12 illustrates another embodiment of a memory device according to the invention;

[0077] FIGS. 13 to 15 illustrate alternative embodiments of the memory device of FIG. 12:

[0078] FIGS. 16 to 18 illustrate other embodiments of memory devices according to the invention.

[0079] The invention and the different applications thereof will be better understood on reading the description that follows and by examining the figures that accompany it.

DETAILED DESCRIPTION

[0080] Unless stated otherwise, a same element appearing in the different figures has a single reference.

[0081] FIG. 1 has already been described with reference to the prior art.

[0082] FIG. 2 has already been described with reference to the prior art.

[0083] FIG. 3 has already been described with reference to the prior art.

[0084] FIG. 4 schematically illustrates the memory device M according to an aspect of the invention, comprising a memory cell CR and a selector device S according to the invention, the memory cell and the selector device being connected in series. The selector device S according to the invention comprises a first selector device S1 and a second selector device S2. The first selector device S1 and the second selector device S2 are connected in parallel. Each of the two selector devices has two states, a first low resistance state and a second high resistance state. The electric current applied voltage characteristic of each selector device shows a threshold electric voltage above which the selector device switches into its low resistance state and supplies an electric current.

[0085] Beneficially, the first selector device and the second selector device are configured to have different threshold electric voltages. This is possible for example thanks to the choice of different active materials for the two devices.

[0086] The first selector device S1 comprises a first active material having a first threshold electric voltage. The second selector device S2 comprises a second active material having a second threshold electric voltage. The first selector device S1 supplies in its low resistance state an electric current lower than the second selector device S2.

[0087] Beneficially, thanks to the connection of the two selector devices S1 and S2 in parallel, it is possible to associate the operation of reading the state of the resistive memory cell CR with the first selector device and the operation of programming the state of the memory cell CR with the second selector device S2.

[0088] Indeed, the operation of reading the state of the resistive memory cell CR requires a low electric current, generally of the order of 1 μA. Thanks to the device according to the invention, it is thus possible to apply the first threshold voltage to the selector device S and to use the electric current supplied by the first selector device S1. This makes it possible to use uniquely the first selector device for the reading operation while avoiding activating the second selector device. The reading operation does not lead to any activation of the second selector device S2, while limiting its deterioration and while increasing the lifetime and the reliability of the device. In addition, by using a low electric current for the reading operation, the device according to the invention limits energy consumption.

[0089] Thus, to carry out an operation of writing of the resistive memory cell CR, it is possible to apply the second threshold electric voltage, which makes it possible to activate the second selector device S2, while placing it in its low resistance state. The second threshold electric voltage being higher than the first threshold electric voltage, the second selector device S2 supplies a very strong electric current, for example greater than or equal to 100 μA. This strong electric current may be opportunely used to modify the state of the resistive memory cell.

[0090] Beneficially, the activation of the second selector device S2 is carried out uniquely during a writing or programming operation. Writing operations being generally less frequent than simple reading operations, this makes it possible to reduce considerably degradation of the second selector device S2.

[0091] In other words, the resistive memory device according to the invention makes it possible to deal with the different constraints encountered during reading and writing operations, while increasing the reliability and the lifetime of the device and while limiting energy consumption.

[0092] FIG. 5 shows a particular embodiment of the selector device S according to the invention. According to this embodiment, the first selector device S1 is a diode and the second selector device S2 is a backend selector device of ovonic threshold switch or OTS type.

[0093] FIG. 6 illustrates the electrical characteristic of a backend diode with temperature. A threshold voltage around 1 V and currents around 10 μA for an applied voltage of 2V may be observed.

[0094] FIG. 7 illustrates the electrical characteristic of an OTS type backend selector. It may be seen that, for applied voltages greater than the threshold voltage V.sub.TH, the OTS selector passes abruptly from the OFF state to the conductive ON state.

[0095] The choice of a diode for the first selector device comprises several benefits.

[0096] Firstly, the diode has very considerable non-linearity and it may be activated at relatively low voltages, with a first threshold voltage of the order of 1V.

[0097] Due to the low manufacturing temperature of the backend, normally less than 500° C., the resistance of the ON state or low resistance state of the diode may be highly variable. However, this is no longer a problem for the device according to the invention, where the active state of the diode is reserved solely for the reading operation and thus for a simple distinction between the ON state and the OFF state of the memory cell. Beneficially, the device according to the invention eliminates the necessity of mastering the current supplied by a diode during the writing operation.

[0098] Furthermore, the relatively high resistance of the diode in its ON state poses a strict limit to the miniaturisation of the diode, which is not relevant if the diode is used uniquely for reading operations.

[0099] In addition, the sub-threshold current of a diode is very low and compatible with very low leakage currents.

[0100] Beneficially, the device according to the invention uses the diode uniquely for a reading operation, the characteristics of the diode being perfectly suited for this operation, the diode may be of the p-n or p-i-n type, obtained by consecutive doping by ion implantation.

[0101] A p-n junction diode may comprise B doped polycrystalline silicon in the “p” zone of the diode and P doped polycrystalline silicon in the “n” zone of the diode.

[0102] A p-i-n junction diode may comprise B doped polycrystalline silicon in the “p” zone of the diode, intrinsic polycrystalline silicon in the “i” zone and P doped polycrystalline silicon in the “n” zone of the diode.

[0103] The choice of a backend type OTS selector for the second selector device S2 also comprises several benefits.

[0104] Firstly, the threshold voltage for this type of backend selector is high, for example greater than or equal to 1V. A correlation exists between leakage current I.sub.LEAK and threshold voltage V.sub.TH. Indeed, the higher the threshold voltage V.sub.TH, the lower I.sub.LEAK. Ideally, the sub-threshold leakage currents must be very low to reduce losses in memory cells outside of the selected memory device, at the intersection of the word line and the bit line. Beneficially, a high threshold voltage for the second selector device makes it possible to have greater selectivity of the memory point to address and thus a lower I.sub.LEAK.

[0105] In addition, an OTS type selector in its active state can deliver a high current density, thus enabling programming of the resistive memory cell CR. This aspect is very favourable to scaling of the device.

[0106] The choice of an OTS type selector device is thus ideal for carrying out operations of programming or writing the resistive memory cell.

[0107] FIG. 8 illustrates the electrical characteristic of the device according to the invention illustrated in FIG. 5. The reading voltage V.sub.Read must be higher than the threshold voltage of the diode V.sub.threshold,DIODE, so as to place the diode in its active, or low resistance, state. At the voltage V.sub.Read the selector device S2 remains in its high resistance state, the only electric current being that supplied by the diode. This configuration precisely makes it possible to read the state of the memory cell. If the memory is in a SET state or low resistance state with a resistance of the order of 10 kOhms, the electric current will be dominated by the resistance of the diode in series with that of the memory. One speaks of SET state of the 1S1R device. If on the other hand the memory is in a RESET state, with a resistance of the order of 1 MOhm, the electric current will be dominated by the resistance of the memory and thus be very low. In this case one speaks of SET state of the 1S1R device.

[0108] According to an embodiment, the device further comprises a comparator making it possible to distinguish between the two resistive states.

[0109] The programming operation will be carried out by applying the voltage V.sub.Prog to the selector device. The voltage V.sub.Prog is higher than the voltage V.sub.th,OTS of the OTS type backend selector. The voltage V.sub.Prog is higher than V.sub.read and V.sub.threshold,Diode. The voltage V.sub.Prog is sufficiently high to change the state of the backend selector and to place it in its active state, which allows the selector to supply high currents. These currents are sufficiently high to enable programming of the resistive memory cell.

[0110] In a manner identical to a standard “crossbar” structure, voltage generators with a current control will have to be put in place to manage correctly the word line and the bit line of the addressed device, at the intersection of the two lines.

[0111] The technique of biasing a matrix formed by several memory devices according to the invention must take into account the presence of two different threshold voltages (thus a voltage for reading, a voltage for programming). The operation the most impacted by the presence of leakage currents is reading, which thus limits the maximum dimension of the matrix. Indeed, the reading operation is based on the distinction between a maximum current, associated with the SET state and a minimum current, associated with the RESET state. The current associated with the RESET state is impacted by the presence of all the devices on the same bit line and the same word line of the selected device V/2 biased fora “V/2” type matrix bias. This same current may also be impacted by all the V/3 biased devices of the matrix for a “V/3” type matrix bias.

[0112] FIG. 9 illustrates an embodiment of the memory device M according to the invention, said device comprising: [0113] A resistive memory cell CR comprising a first memory cell electrode 101, a second memory cell electrode 103 and a memory cell active material 102; [0114] A first selector device S1 comprising a first electrode of the first selector device 104, a second electrode of the first selector device 106 and a first active material 105; [0115] A second selector device S2 comprising a first electrode of the second selector device 107 and a second active material 108; the second electrode of the second selector device S2 is not represented in this figure and may be realised as illustrated by the conductive layer WL in FIG. 11f; [0116] A dielectric layer 109 configured to electrically insulate the first selector device S1 and the second active material 108; [0117] A second dielectric layer 110 configured to electrically insulate the first electrode of the second selector device 107 and a dielectric filling layer 111.

[0118] According to an embodiment, the first memory cell electrode 101 is arranged so as to connect electrically the first electrode of the first selector device 104 and the first electrode of the second selector device 107. This arrangement makes it possible to obtain a connection in series between the resistive memory cell CR and the selector device S comprising the first selector device S1 and the second selector device S2 which are in parallel (S1 and S2).

[0119] According to an embodiment, the device 100 further comprises an electrode or an electrically conductive element, which is not represented in FIG. 9, connecting the second electrode of the first selector device S2 and the second active material. According to an embodiment, this second electrode is a metal line of words or bits, as is illustrated in FIG. 11f. Beneficially, the electrically conductive element connecting the second electrode 106 of the first selector device S1 and the second active material 108 makes it possible to realise the connection in parallel of the first selector device S1 and the second selector device S2.

[0120] According to the embodiment illustrated in FIG. 9, the layers 109, 108, 107 and 110 are deposited and next intercalary layer or spacer etched. In other words, each layer is deposited and next etched along the direction normal to the plane of deposition of the layer itself. The etching may comprise the entire thickness of the layer, as in the case of the electrically insulating layer 109, which is configured as a vertical layer normal to the plane of deposition of the layers of the first selector device S1. Beneficially, the electrically insulating layer 109 makes it possible to electrically insulate the first selector device S1 and the second active material 108. Following the etching process, the insulating layer 109 surrounds the first selector device S1.

[0121] The etching of the layers 108 and 107 may be partial, only comprising a part of the thickness of the deposited layers. It follows that the layers 107 and 108 have a variable thickness along the direction normal to the plane of deposition of the layers of the first selector device S1. For example, the sectional view of FIG. 9 shows that the second active material 108 has an L-shaped section, with a foot of thickness e. Beneficially, the foot of thickness e of the layer forming the second active material 108 enables the connection in parallel between the first selector device S1 and the second selector device S2. This is possible thanks to the first electrode of the second selector device 107 and the metal element connecting the second electrode of the first selector 106 and the second active material 108, said metal element not being represented in FIG. 9. According to an embodiment illustrated in FIG. 11f, the metal element is a word line WL.

[0122] In other words, as is illustrated in FIG. 9b, the first electrode 107 of the second selector device comprises a first 107a and a second part 107b of first electrode, the second active material 108 comprises a first 108a and a second part 108b of active material 108, the first parts 107a, 108a forming a first angle with the plane of the layers 104, 105, 106 of the first selector device S1 and the second parts 107b, 108b forming a second angle with the plane of the layers 104, 105, 106 of the first selector device S1.

[0123] The embodiment illustrated in FIGS. 9 and 9b comprises first parts 107a and 108a normal to the plane of the layers of the first selector device S1 and second parts 107b and 108b parallel to the plane of the layers of the first selector device.

[0124] According to the embodiment represented in FIG. 9, the layers 107,108, 110 and 111 surround the first selector device S1. In other words, the layers 107 and 108 of the second selector device S2 surround the first selector device S1. This is possible thanks to the fact that the layers comprised in the second selector device S2 are at least partially spacer etched.

[0125] FIG. 10 schematically illustrates the steps of the method P for manufacturing a selector device according to the invention. The method according to the invention comprises a step P101 of depositing a first set of layers comprising a first selector device. According to an embodiment, the first selector device is a diode and the first set of layers comprises a first electrode of the first set of layers, a second electrode of the first set of layers and an active medium of the first set of layers, inserted among the two electrodes. According to an embodiment, the active medium comprises polycrystalline silicon.

[0126] The method according to the invention further comprises a step P102 of etching of the first set of layers. Following this etching step, the first set of layers may have a square, rectangular or circular section.

[0127] During step P103, a first dielectric layer or electrically insulating layer is deposited. According to an embodiment, step P103 further comprises the spacer or intercalary layer etching of the dielectric layer to electrically insulate the active medium of the first selector device and the active medium of the second selector device. Following the spacer etching step, the insulating layer surrounds the first selector device. In other words, the normal to the plane of the electrically insulating layer is oriented along a direction different from the normal to the plane of the layers of the first set of layers.

[0128] During step P104, a second set of layers is deposited. The second set of layers comprises a second active material of a second selector device and a first electrode of a second selector device. Step 104 may also comprise the spacer etching of the layers of the second set. According to an embodiment, before depositing the electrode layer, the layer comprising the second active material is partially etched, with a variable thickness as a function of the etching depth.

[0129] According to an embodiment, the variable thickness of the second active material forms a perimeter intended to host the first electrode of the second set of layers, as is illustrated in FIGS. 9 and 9b. In the same way, the first electrode of the second selector device is spacer etched, with a variable thickness as a function of the etching depth. According to an embodiment, the first electrode of the second selector device forms a perimeter intended to host a second insulating layer, as is illustrated in FIGS. 9 and 9b.

[0130] At the end of step P104, the first set of layers comprising the first selector device is surrounded by the second set of layers comprising an electrode layer and a layer of active material of the second selector device.

[0131] The method according to the invention further comprises a step P105 of depositing an electrically conductive layer intended to connect electrically the first electrode layer of the first set of layers and the first electrode layer of the second set of layers.

[0132] Beneficially, the electrically conductive layer deposited during step P105 makes it possible to realise the connection of the two selector devices in parallel. According to an embodiment, the electrically conductive layer deposited during step P105 is an electrode layer of a resistive memory cell, such as the layer 101 illustrated in FIG. 9.

[0133] The method according to the invention further comprises a step P106 of depositing a dielectric filling layer. According to an embodiment, step P106 further comprises the planarization of the dielectric filling layer. According to an embodiment, the dielectric filling surrounds the second selector device.

[0134] Step P107 comprises the deposition of a third set of layers comprising a memory cell electrode and a resistive memory cell active material. According to an embodiment, the third set of layers covers the electrically conductive layer deposited during step P105, so as to form a resistive memory cell. According to an embodiment, the resistive memory cell thus formed comprises the layers 101, 102 and 103 illustrated in FIG. 9.

[0135] In other words, the step of deposition of the third set of layers P107 is carried out so as to arrange the third set of layers in contact with the electrically conductive layer intended to connect an electrode layer of the first set of layers and the first electrode layer of the second set of layers.

[0136] According to this embodiment, the electrically conductive layer deposited during step 105 also has the function of electrode layer for the resistive memory cell, of which the structure is completed by the layers of the third set of layers.

[0137] Beneficially, step P107 makes it possible to realise the connection in series between the resistive memory cell and the parallel formed by the two selector devices.

[0138] According to an embodiment, step P107 comprises the etching of the third set of layers comprising the resistive memory cell.

[0139] The method according to the invention further comprises a step P108 of depositing a second electrode layer P108 of the second selector device, the second electrode layer of the second selector device being electrically connected to an electrode layer of the first selector device.

[0140] Beneficially, step P108 makes it possible to complete the connection in parallel of the two selector devices.

[0141] According to an embodiment, the second electrode layer of the second selector device is a word line or a bit line.

[0142] FIG. 11a schematically illustrates the result of step P101 when the first selector device S1 is a polysilicon diode. In this case, the first selector device S1 comprises a first electrode of the diode 101, a second electrode of the diode 103 and an active material comprising polycrystalline silicon 102. FIG. 11b shows the result of step P102, comprising the etching of the device S1 of FIG. 11a, resulting in a diode with square, rectangular or circular section.

[0143] FIG. 11c illustrates the second set of layers surrounding the first set of layers. The layers 107,108,109 and 110 have been described in relation with FIGS. 9 and 9b. Thanks to the steps of “spacer” etching, both the layer of second active material 108 and the electrode layer of the second set of layers 107 comprise a perimeter enabling the connection of the first and the second set of layers in parallel. In other words, the sectional view of FIG. 11c shows that the second active material 108 has an L-shaped section comprising a foot of thickness e. Beneficially, the L shape of the second active material 108 makes it possible to connect the first selector device S1 and the second selector device S2 in parallel.

[0144] FIG. 11d represents the result of step P103, with the deposition of a dielectric layer 111 surrounding the second set of layers.

[0145] FIG. 11e represents the result of step P107, with the deposition of the third set of layers comprising the resistive memory cell. The third set of layers comprises a memory cell electrode 101 also having the function of electrical connection between the first electrode 107 of the second selector device and the first electrode 104 of the first selector device. This arrangement makes it possible to realise the connection in parallel of the first and the second set of layers, corresponding to the first S1 and second S2 selector devices.

[0146] FIG. 11f represents the device according to the invention connected to a bit line BL and a word line WL, illustrating an embodiment of step P108. In particular, the word line WL makes it possible to complete the parallel connection between the first and the second selector device while having the function of second electrode of the second selector device.

[0147] Exemplary active materials used for the second selector device S2 according to the invention are: chalcogenide materials based on Ge, Se, As, Si, Te, Sb, N, C, etc. or sets of layers of several chalcogenide materials: Ge—Se, Ge—Se—Sb, As—Se—Ge—Si—N etc.

[0148] The electrodes may for example be made of TiN, TaN, W, TiWN, TiCN, TiSiN, C, etc. or sets of layers based on the same materials or other conductive materials.

[0149] The PCM materials used as active materials for the resistive memory cell CR are also materials based on chalcogenide alloys, or mixtures or sets of layers thereof: Ge—Sb—Te, Ga—Sb—Te, Ge—Te, Sb—Te, Ti—Sb—Te, Ti—Te.

[0150] FIG. 12 illustrates another embodiment of a memory device 200 according to the invention comprising a selector device 201 according to the invention and a resistive memory cell 202 of PCM or PCRAM (phase change random access memory) type.

[0151] The selector device 201 according to the invention comprises a p-n junction diode 203 (here a P+-N++ junction diode) and an OTS type selector 204.

[0152] The particularity of this embodiment consists of a diode 203, front end embedded, for example in an SOI (silicon on insulator) substrate or in a silicon layer 205 doped in a suitable manner for the formation of the diode 203.

[0153] The silicon layer 205 comprises an N+ doped (i.e. strongly N doped) part 206 with a first N++ doped (i.e. very strongly N doped, that is to say doped more than the N+ doped part 206) inner well 207

[0154] A second P+ doped (i.e. strongly P doped) well 208 is formed inside the first N++ doped well 207. The two wells 207 and 208 thus enable the formation of the diode 203 comprising a P+/N++ junction. More specifically, the second P+ well 208 is substantially centred inside the first N++ well 207 and one of the parts 207a (here on the left in the drawing) of the first well 207 enables the formation of the P+/N++ junction at its interface with the second P++ well 208.

[0155] The upper part of the two wells 207 and 208 arrive on the surface of the silicon layer 206 in such a way as to be able to ensure back end contacts above the silicon layer 206.

[0156] The OTS selector 204 is thus back end formed on the part 207b (here on the right in the drawing) of the first well 207, the parts 207a and 207b being on either side of the second P+ well 208.

[0157] The OTS selector 204 comprises:

[0158] a first electrode 209 formed in contact with the upper surface of the part 207b of the first N++ well 207

[0159] an active layer 210 formed for example of a chalcogenide material deposited on the first electrode 209 and

[0160] a second electrode 211 formed on the active layer 201.

[0161] A word line (or WL) 212 is formed in contact with the upper surface of the part 207a of the first P+ well 208. This word line 212 may be considered as a first electrode of the diode 203 and is connected to the first electrode 209 of the OTS selector 204 via the N++ zone 207 (a conductive path 213 is represented in a purely schematic manner in order to illustrate this conductive link). The conductive path 213 is obviously slightly resistive (due to the N++ nature of the zone 207) but sufficient to ensure good conduction between the line 212 and the first electrode 209.

[0162] Two conductive electrodes 214 and 215, for example metal electrodes, are respectively arranged on the P+ well 208 of the diode 203 and on the second electrode 211 of the OTS selector 204. The electrode 214 may be considered as the second electrode of the diode 203.

[0163] A U-shaped electrode 216 comprising a U base 216a in the plane of the layers and two U-shaped arms (respectively 216b and 216c) are arranged such that the base of the U 201a is in contact respectively with the conductive electrodes 214 and 215. This U-shaped electrode, 216, is for example realised in the form of a liner deposited in a trench etched in an insulator zone, and extends along the direction x perpendicular to the sectional plane of FIG. 12.

[0164] The PCM memory 202 comprises an active layer 217 arranged above and in contact with the arm 216b of the U-shaped electrode 216. This active layer 217 is formed of a phase change material, typically a chalcogenide material.

[0165] A bit line BL1 218 is arranged above and in contact with the active layer 217.

[0166] According to this embodiment, the bit line 218 acts as upper electrode for the PCM memory 202 and the arm 216b of the U-shaped electrode 216 (and more generally the U-shaped electrode 216) acts as lower electrode for the PCM memory 202.

[0167] According to this embodiment, it is observed that the second electrode 214 of the diode 203 and the upper electrode 211 of the OTS selector 201 are electrically connected by the U-shaped electrode 216.

[0168] Thus, the first selector device formed by the diode 203 and the second selector device 204 formed by the OTS selector are connected in parallel. Further, the PCM memory cell 202 is in series with the two selectors 203 and 204 mounted in parallel.

[0169] The interest of such an embodiment notably lies at the technological level, in terms of manufacture, since it makes it possible to separate the manufacture of the first selector (the diode 203), front end produced, from the remainder of the device, back end produced with higher metallisation levels

[0170] It will furthermore be noted that, according to the invention, the diode is used only for reading such that its dimensions may be reduced because it does not need to allow an important current to pass (i.e. reading current of the PCM memory); the N++ zone 206 must be dimensioned to allow the writing current coming from the OTS selector 204 to pass.

[0171] FIG. 13 illustrates another embodiment of a memory device according to the invention. This device is in all points comparable with that of FIG. 12 with the difference that the P and N dopings of the back end zone are inversed. Thus, the P+ well 208 becomes an N+ well and the N++ well 207 becomes a P++ well. More generally, it is possible to inverse the P and N dopings in the invention.

[0172] The N+ doped part 206 in which the wells are embedded becomes indifferently a P or P+ zone.

[0173] At the operating level of the memory device, the only change consists in the direction of the reading current which is reversed with respect to that of FIG. 12, the diode of FIG. 13 being conductive in an opposite direction with respect to its arrangement of FIG. 12.

[0174] FIG. 14 illustrates an alternative of the device 200 of FIG. 12. The only difference concerns the electrode 216. It is observed in fact that the arm 216c of the U-shaped electrode 216 has no usefulness in the device 200, if it is not that the formation of a U shape is easily achievable in the form of a liner. In the embodiment of FIG. 14, the U-shaped electrode 216 is replaced by an inversed T-shaped electrode 216′ comprising a base 216a′ in the plane of the layers and a perpendicular arm 216b′. As in FIG. 12, the base 216a′ is arranged such that it is in contact respectively with the conductive electrodes 214 and 215 whereas the arm 216b′ acts as lower electrode for the PCM memory 202. The active layer of the PCM memory is located above and in contact with the arm 216b′.

[0175] FIG. 15 illustrates an alternative 300 of the memory device of FIG. 12. The device 300 is identical to the device 200 of FIG. 12 (the common characteristics bear the same reference numbers) with the difference that it comprises in addition a second PCM memory cell 220 in addition to the first PCM memory cell 202.

[0176] The PCM memory cell 220 comprises an active layer 221 arranged above and in contact with the arm 216c of the U-shaped electrode 216. This active layer 221 is formed of a phase change material, typically a chalcogenide material.

[0177] A bit line BL1 222 is arranged above and in contact with the active layer 221.

[0178] According to this embodiment, the bit line 222 acts as upper electrode for the second PCM memory 220 and the arm 216c of the U-shaped electrode 216 (and more generally the U-shaped electrode 216) acts as lower electrode for the second PCM memory 220.

[0179] The benefit of the embodiment of FIG. 15 is to benefit from the existence of the other arm of the U-shaped electrode to add another PCM memory.

[0180] According to this embodiment, each of the two PCM memory cells 202 and 220 is mounted in series with the two selectors 203 and 204 in such a way as to form two 1T1R assemblies mounted in parallel.

[0181] In the presence of the two PCM memories, one of the principles of the invention may be to program one in the SET state and the other in the RESET state.

[0182] To do so, two different pulses 11 and 12 are applied to the respective upper electrodes 218 and 222 (i.e. the bit lines BL1 and BL2) of the memory cells 202 and 220.

[0183] As a reminder, a PCM memory cell uses a phase change material capable of switching very rapidly and reversibly between an amorphous phase and a crystalline phase. Yet these two phases have very great differences in properties. The amorphous phase is notably characterised by a high electrical resistivity, whereas the crystalline phase has a much lower electrical resistivity. Thus, the information bit is encoded by the difference in resistivity between the amorphous state and the crystalline state of the phase change material. Typically, the amorphous phase represents the logic level ‘0’ and the crystalline state represents the logic level ‘1’. The transition from the crystalline state to the amorphous state is obtained by applying a short pulse of high amplitude current, to locally melt the crystalline material and make it amorphous. The transition from the amorphous state to the crystalline state is also based on a heating up of the material, to a crystallisation temperature however less high. It is obtained by applying a current pulse that is longer but of smaller amplitude

[0184] In this instance, the pulse 11 applied to the cell 202 is going to make the active material of the cell 202 amorphous through heating. The same phenomenon is going to take place with the pulse 12 applied to the cell 220, the difference consisting in that the pulse 12 is longer than the pulse 11 and continues with a current ramp of less high intensity; thus, the end of the pulse 12 is going to make it possible to crystallise the active material of the cell 220. Thus, the first pulse 11 is going to place the cell 202 in a RESET (high resistance) state whereas the pulse 12 is going to place the cell 220 in a SET (low resistance) state. It will be noted that the writing of the cells 202 and 220 takes place through the passage of current in the OTS selector 201.

[0185] Reading for its part will take place via the selector formed by the diode 203. When the cell 202 is going to be “read”, a high resistance will be measured at its terminals and when the cell 220 is going to be “read”, a lower resistance will be measured at its terminals.

[0186] The device 300 of FIG. 15 is thus a double cell per bit or DLC (double level cell) type device which uses the knowledge of two states to reinforce the probability of knowing a single state.

[0187] According to this embodiment, the other arm of the electrode is thus used in a pragmatic manner. The two items of information are compared to have more certain information. It is even possible to have another resistive information between the bit lines 201 and 222 (BL1 and BL2).

[0188] Such a configuration is particularly useful for applications that depend in a critical manner on the retention of the information stored in the memory.

[0189] FIGS. 16 to 18 illustrate other embodiments of the invention in which the two selectors (diode and OTS) are directly formed at the same metal level above a word line.

[0190] The invention is particularly beneficial in the case where the first selector is a diode and the second selector is an OTS type selector.

[0191] Certain embodiments have been described in the case of a PCM type memory cell but the invention could also apply to other resistive memory cells such as OxRam or CBRAM.