POLY-INSULATOR-POLY CAPACITOR AND FABRICATION METHOD THEREOF

Abstract

A poly-insulator-poly (PIP) capacitor including a substrate having a capacitor forming region; a first capacitor dielectric layer on the capacitor forming region; a first poly electrode on the first capacitor dielectric layer; a second capacitor dielectric layer on the first poly electrode; and a second poly electrode on the second capacitor dielectric layer. A third poly electrode is disposed adjacent to a first sidewall of the second poly electrode. A third capacitor dielectric layer is disposed between the third poly electrode and the second poly electrode. A fourth poly electrode is disposed adjacent to a second sidewall of the second poly electrode opposite to the first sidewall. A fourth capacitor dielectric layer is disposed between the fourth poly electrode and the second poly electrode.

Claims

1. A poly-insulator-poly (PIP) capacitor, comprising: a semiconductor substrate comprising a capacitor forming region; a first capacitor dielectric layer disposed on the capacitor forming region; a first poly electrode disposed on the first capacitor dielectric layer; a second capacitor dielectric layer disposed on the first poly electrode; a second poly electrode disposed on the second capacitor dielectric layer, wherein the first poly electrode comprises a contact portion that protrudes beyond an end surface of the second poly electrode; a third poly electrode disposed adjacent to a first sidewall of the second poly electrode; a third capacitor dielectric layer disposed between the third poly electrode and the second poly electrode; a fourth poly electrode disposed adjacent to a second sidewall of the second poly electrode that is opposite to the first sidewall; and a fourth capacitor dielectric layer disposed between the fourth poly electrode and the second poly electrode.

2. The PIP capacitor according to claim 1, wherein the first poly electrode, the third poly electrode, and the fourth poly electrode are electrically connected to an anode.

3. The PIP capacitor according to claim 2, wherein the second poly electrode is electrically connected to a cathode, and wherein the third poly electrode, the third capacitor dielectric layer, and the second poly electrode constitute a first capacitor, the first poly electrode, the second capacitor dielectric layer, and the second poly electrode constitute a second capacitor, and the second poly electrode, the fourth capacitor dielectric layer, and the fourth poly electrode constitute a third capacitor.

4. The PIP capacitor according to claim 3, wherein an ion well is disposed within the capacitor forming region and is electrically connected to the cathode, and wherein the third poly electrode, the first capacitor dielectric layer and the ion well constitute a fourth capacitor, and the first poly electrode, the first capacitor dielectric layer and the ion well constitute a fifth capacitor.

5. The PIP capacitor according to claim 4, wherein a fifth capacitor dielectric layer is disposed between the fourth poly electrode and the semiconductor substrate, wherein the fifth capacitor dielectric layer is thicker than the first capacitor dielectric layer, and wherein the fourth poly electrode, the fifth capacitor dielectric layer, and the ion well constitute a sixth capacitor.

6. The PIP capacitor according to claim 1, wherein a width of the first poly electrode is greater than a width of the second poly electrode.

7. The PIP capacitor according to claim 1, wherein the second capacitor dielectric layer, the third capacitor dielectric layer, and the fourth capacitor dielectric layer comprise an oxide-nitride-oxide (ONO) dielectric layer.

8. The PIP capacitor according to claim 1 further comprising a hard mask layer capping the second poly electrode, and wherein a top surface of the hard mask layer is flush with a top surface of the fourth poly electrode.

9. The PIP capacitor according to claim 1, wherein the third capacitor dielectric layer and the fourth capacitor dielectric layer are in direct contact with a top surface of the first poly electrode.

10. The PIP capacitor according to claim 1, wherein the capacitor forming region is a trench isolation region.

11. A method for forming a poly-insulator-poly (PIP) capacitor, comprising: providing a semiconductor substrate comprising a capacitor forming region; forming a first capacitor dielectric layer on the capacitor forming region; forming a first poly electrode on the first capacitor dielectric layer; forming a second capacitor dielectric layer on the first poly electrode; forming a second poly electrode on the second capacitor dielectric layer; forming a third poly electrode adjacent to a first sidewall of the second poly electrode; forming a third capacitor dielectric layer between the third poly electrode and the second poly electrode; forming a fourth poly electrode adjacent to a second sidewall of the second poly electrode that is opposite to the first sidewall; and forming a fourth capacitor dielectric layer between the fourth poly electrode and the second poly electrode.

12. The method according to claim 11, wherein the first poly electrode, the third poly electrode, and the fourth poly electrode are electrically connected to an anode.

13. The method according to claim 12, wherein the second poly electrode is electrically connected to a cathode, and wherein the third poly electrode, the third capacitor dielectric layer, and the second poly electrode constitute a first capacitor, the first poly electrode, the second capacitor dielectric layer, and the second poly electrode constitute a second capacitor, and the second poly electrode, the fourth capacitor dielectric layer, and the fourth poly electrode constitute a third capacitor.

14. The method according to claim 13, further comprising: forming an ion well within the capacitor forming region, wherein the ion well is electrically connected to the cathode, and wherein the third poly electrode, the first capacitor dielectric layer and the ion well constitute a fourth capacitor, and the first poly electrode, the first capacitor dielectric layer and the ion well constitute a fifth capacitor.

15. The method according to claim 14, further comprising: forming a fifth capacitor dielectric layer between the fourth poly electrode and the semiconductor substrate, wherein the fifth capacitor dielectric layer is thicker than the first capacitor dielectric layer, and wherein the fourth poly electrode, the fifth capacitor dielectric layer, and the ion well constitute a sixth capacitor.

16. The method according to claim 11, wherein a width of the first poly electrode is greater than a width of the second poly electrode.

17. The method according to claim 11, wherein the second capacitor dielectric layer, the third capacitor dielectric layer, and the fourth capacitor dielectric layer comprise an oxide-nitride-oxide (ONO) dielectric layer.

18. The method according to claim 11 further comprising: forming a hard mask layer capping the second poly electrode, wherein a top surface of the hard mask layer is flush with a top surface of the fourth poly electrode.

19. The method according to claim 11, wherein the third capacitor dielectric layer and the fourth capacitor dielectric layer are in direct contact with a top surface of the first poly electrode.

20. The method according to claim 11, wherein the capacitor forming region is a trench isolation region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG. 1 is a schematic cross-sectional diagram of a PIP capacitor according to an embodiment of the present invention.

[0027] FIG. 2 is a side perspective view of the PIP capacitor in FIG. 1.

[0028] FIG. 3 is an equivalent circuit diagram of the PIP capacitor in FIG. 1.

[0029] FIG. 4 to FIG. 8 are schematic cross-sectional diagrams showing a method of forming a PIP capacitor according to an embodiment of the present invention.

DETAILED DESCRIPTION

[0030] In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention.

[0031] Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be considered as limiting, but the embodiments included herein are defined by the scope of the accompanying claims.

[0032] Please refer to FIG. 1 to FIG. 3. FIG. 1 is a schematic cross-sectional diagram of a PIP capacitor according to an embodiment of the present invention. FIG. 2 is a side perspective view of the PIP capacitor in FIG. 1. FIG. 3 is an equivalent circuit diagram of the PIP capacitor in FIG. 1. As shown in FIG. 1, the integrated capacitor 1 of the present invention includes two PIP capacitors 1a and 1b that are mirror-symmetrical with respect to the central line CL, which are formed in the capacitance forming region CA of the semiconductor substrate 100. According to an embodiment of the present invention, the capacitor forming region CA may include an ion well 101, such as an N-type well (or N well). In some embodiments, the capacitor forming region CA may include a trench isolation area, for example, shallow trench insulation (STI) structure. In the following, the PIP capacitor 1a is taken as an example for description. In FIG. 2, only the PIP capacitor 1a is shown as an example.

[0033] As shown in FIG. 1 and FIG. 2, a first capacitor dielectric layer DL.sub.1 is formed on the capacitor forming region CA. On the first capacitor dielectric layer DL.sub.1, a first polysilicon electrode (or first poly electrode) P.sub.1 is provided. On the first polysilicon electrode P.sub.1, a second capacitor dielectric layer DL.sub.2 is provided. On the second capacitor dielectric layer DL.sub.2, a second polysilicon electrode (or second poly electrode) P.sub.2 is provided. As shown in FIG. 2, the first polysilicon electrode P.sub.1 includes a contact portion CP, and the contact portion CP protrudes beyond one end surface ES of the second polysilicon electrode P.sub.2. On a first sidewall SW.sub.1 adjacent to the second polysilicon electrode P.sub.2, a third polysilicon electrode (or third poly electrode) P.sub.3 is provided. Between the third polysilicon electrode P.sub.3 and the second polysilicon electrode P.sub.2, a third capacitor dielectric layer DL.sub.3 is provided. A fourth polysilicon electrode (or fourth poly electrode) P.sub.4 is provided on a second sidewall SW.sub.2 adjacent to the second polysilicon electrode P.sub.2. The second side wall SW.sub.2 and the first side wall SW.sub.1 are two opposite side walls. Between the fourth polysilicon electrode P.sub.4 and the second polysilicon electrode P.sub.2, a fourth capacitor dielectric layer DL.sub.4 is provided.

[0034] According to an embodiment of the present invention, as shown in FIG. 2, the first polysilicon electrode P.sub.1, the third polysilicon electrode P.sub.3, and the fourth polysilicon electrode P.sub.4 are electrically connected to anode through contact plugs CT.sub.1, CT.sub.3, and CT.sub.4, respectively. According to an embodiment of the present invention, as shown in FIG. 2, the second polysilicon electrode P.sub.2 is electrically connected to cathode through the contact plug CT.sub.2. As shown in FIG. 1, the third polysilicon electrode P.sub.3, the third capacitor dielectric layer DL.sub.3 and the second polysilicon electrode P.sub.2 constitute a first capacitor C.sub.1. The first polysilicon electrode P.sub.1, the second capacitor dielectric layer DL.sub.2 and the second polysilicon electrode P.sub.2 constitute a second capacitor C.sub.2. The second polysilicon electrode P.sub.2, the fourth capacitor dielectric layer DL.sub.4 and the fourth polysilicon electrode P.sub.4 constitute a third capacitor C.sub.3. According to an embodiment of the present invention, the ion well 101 is electrically connected to the cathode through the contact plug CT. The third polysilicon electrode P.sub.3, the first capacitor dielectric layer DL.sub.1 and the ion well 101 constitute a fourth capacitor C.sub.4. The first polysilicon electrode P.sub.1, the first capacitor dielectric layer DL.sub.1 and the ion well 101 constitute a fifth capacitor C.sub.5.

[0035] According to an embodiment of the present invention, a fifth capacitor dielectric layer DL.sub.5 is disposed between the fourth polysilicon electrode P.sub.4 and the ion well 101 of the semiconductor substrate 100. The fifth capacitor dielectric layer DL.sub.5 is thicker than the first capacitor dielectric layer DL.sub.1. The fourth polysilicon electrode P.sub.4, the fifth capacitor dielectric layer DL.sub.5 and the ion well 101 constitute a sixth capacitor C.sub.6. As shown in FIG. 3, the above-mentioned first capacitor C.sub.1 to sixth capacitor C.sub.6 form a parallel capacitor configuration.

[0036] According to an embodiment of the present invention, as shown in FIG. 1, a width of the first polysilicon electrode P.sub.1 is slightly larger than a width of the second polysilicon electrode P.sub.2. According to an embodiment of the present invention, the second capacitor dielectric layer DL.sub.2, the third capacitor dielectric layer DL.sub.3, and the fourth capacitor dielectric layer DL.sub.4 may comprise an oxide-nitride-oxide (ONO) dielectric layer. According to an embodiment of the present invention, the PIP capacitor 1a further includes a hard mask layer HM capping the second polysilicon electrode P.sub.2. A top surface S.sub.2 of the hard mask layer HM is flush with a top surface S.sub.4 of the fourth polysilicon electrode P.sub.4. According to an embodiment of the present invention, the third capacitor dielectric layer DL.sub.3 and the fourth capacitor dielectric layer DL.sub.4 are in direct contact a top surface S.sub.1 of the first polysilicon electrode P.sub.1.

[0037] FIG. 4 to FIG. 8 are schematic cross-sectional diagrams showing a method for forming a PIP capacitor according to an embodiment of the present invention, wherein like regions, layers, and elements are designated by like reference numerals or labels. As shown in FIG. 4, first, a semiconductor substrate 100 is provided, which includes a capacitor forming region CA. An ion well 101, such as an N well, may be included in the capacitor forming region CA of the semiconductor substrate 100. In some embodiments, the capacitor forming region CA may include a trench isolation area, for example, STI structure. A first capacitor dielectric layer DL.sub.1, a first polysilicon layer PL.sub.1, a second capacitor dielectric layer DL.sub.2, a second polysilicon layer PL.sub.2, and a hard mask layer HM are sequentially formed on the capacitor forming region CA. According to an embodiment of the present invention, for example, the first capacitor dielectric layer DL.sub.1 may be a silicon oxide layer, the second capacitor dielectric layer DL.sub.2 may be an ONO dielectric layer, and the hard mask layer HM may be a silicon nitride layer, but not limited thereto. According to an embodiment of the present invention, for example, the thickness of the second polysilicon layer PL.sub.2 may be greater than that of the first polysilicon layer PL.sub.1, but is not limited thereto.

[0038] As shown in FIG. 5, lithography and etching processes are then performed to pattern the hard mask layer HM, the second polysilicon layer PL.sub.2 and the second capacitor dielectric layer DL.sub.2, and define a first stack structure ST.sub.1 on the first polysilicon layer PL.sub.1. The first stack structure ST.sub.1 includes the second capacitor dielectric layer DL.sub.2, the second polysilicon electrode P.sub.2 and the hard mask layer HM. Then, first spacers SP.sub.1, for example, oxide-nitride (ON) spacers, are formed on two opposite sidewalls of the first stack structure ST.sub.1.

[0039] As shown in FIG. 6, the lithography and etching processes are performed to pattern the first polysilicon layer PL.sub.1, and define a second stacked structure ST.sub.2 on the first capacitor dielectric layer DL.sub.1, including the first polysilicon electrode P.sub.1, the second capacitor dielectric layer DL.sub.2, the second polysilicon electrode P.sub.2, the hard mask layer HM and the first spacers SP.sub.1. According to an embodiment of the present invention, the sidewalls of the first polysilicon electrode P.sub.1 may be approximately flush with the outer surface of the first spacers SP.sub.1. According to an embodiment of the present invention, the width of the first polysilicon electrode P.sub.1 is greater than the width of the second polysilicon electrode P.sub.2. According to an embodiment of the present invention, as shown in FIG. 2, the first polysilicon electrode P.sub.1 includes a contact portion CP, and the contact portion CP protrudes beyond one end surface ES of the second polysilicon electrode P.sub.2.

[0040] As shown in FIG. 7, second spacers SP.sub.2, for example, silicon oxide spacers, are then formed on two sidewalls of the second stack structure ST.sub.2. Then, a third polysilicon electrode P.sub.3 and a fourth polysilicon electrode P.sub.4 are formed on opposite sides of the second stack structure ST.sub.2, respectively. To form the third polysilicon electrode P.sub.3 and the fourth polysilicon electrode P.sub.4, for example, a polysilicon layer is deposited in a blanket manner, and then a chemical mechanical polishing (CMP) process may be performed to planarize the polysilicon layer until the hard mask layer HM is exposed. According to an embodiment of the present invention, a top surface S.sub.2 of the hard mask layer HM may be flush with a top surface S.sub.4 of the fourth polysilicon electrode P4.

[0041] As shown in FIG. 8, a deposition process, for example, a chemical vapor deposition (CVD) process is performed to deposit an inter-layer dielectric layer IL on the semiconductor substrate 100. Then, lithography and etching processes may be performed to form contact plugs CT, CT.sub.1 to CT.sub.4 in the inter-layer dielectric layer IL, such that the first polysilicon electrode P.sub.1, the third polysilicon electrode P.sub.3, and the fourth polysilicon electrode P.sub.4 are electrically connected to the anode through the contact plugs CT.sub.1, CT.sub.3 and CT.sub.4 respectively, and that the ion well 101 and the second polysilicon electrode P.sub.2 are electrically connected to the cathode through the contact plugs CT and CT.sub.2, respectively.

[0042] It is advantageous to use the present invention because high-density PIP capacitors can be formed in the early stage of the semiconductor manufacturing process, which have high capacitance values and can withstand high voltages (for example, >10V). In addition, the manufacturing method of the PIP capacitor of the present invention is compatible with embedded flash memory process, for example, ESF3 (third-generation embedded SuperFlash or ESF3) platform.

[0043] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.