METHOD OF COPPER HILLOCK DETECTING

Abstract

A method of copper hillock detecting includes the following steps. A testkey structure is disposed on a substrate, wherein the testkey structure includes a lower metallization layer, an upper metallization layer, and a dielectric layer between the lower metallization layer and the upper metallization layer. A force voltage difference is applied to the lower metallization layer and the upper metallization layer under a test temperature and stress time. A changed sensing voltage difference to the lower metallization layer and the upper metallization layer is detected for detecting copper hillock.

Claims

1. A method of copper hillock detecting, comprising: disposing a testkey structure on a substrate, wherein the testkey structure comprises: a lower metallization layer, an upper metallization layer, and a dielectric layer between the lower metallization layer and the upper metallization layer; applying a force voltage difference to the lower metallization layer and the upper metallization layer under a test temperature and stress time; and detecting a changed sensing voltage difference to the lower metallization layer and the upper metallization layer for detecting copper hillock.

2. The method of copper hillock detecting according to claim 1, wherein the testkey structure is disposed in a scribe line of the substrate.

3. The method of copper hillock detecting according to claim 1, further comprising: performing a regular integrated circuit fabricating process on the substrate.

4. The method of copper hillock detecting according to claim 3, further comprising: processing a mass production after the changed sensing voltage difference is detected within a pre-determined voltage range.

5. The method of copper hillock detecting according to claim 3, further comprising: optimizing the regular integrated circuit fabricating process after the changed sensing voltage difference is detected out of a pre-determined voltage range.

6. The method of copper hillock detecting according to claim 1, wherein the force voltage difference is at a range of 0-400V.

7. The method of copper hillock detecting according to claim 1, wherein the test temperature is at a range of 25-300° C.

8. The method of copper hillock detecting according to claim 1, wherein the stress time is at a range of 0.001-60 s.

9. The method of copper hillock detecting according to claim 1, wherein the force voltage difference comprises a three-step voltage of a first step voltage, a second step voltage and a third step voltage.

10. The method of copper hillock detecting according to claim 9, wherein the second step voltage is higher than the first step voltage and the third step voltage.

11. The method of copper hillock detecting according to claim 10, wherein the first step voltage and the third step voltage is 40V, and the second step voltage is 400V.

12. The method of copper hillock detecting according to claim 1, wherein the lower metallization layer comprises a plurality of first metal lines parallel to each other, and the upper metallization layer comprises a plurality of second metal lines parallel to each other.

13. The method of copper hillock detecting according to claim 12, wherein the first metal lines and the second metal lines are crossly arranged.

14. The method of copper hillock detecting according to claim 12, wherein the first metal lines and the second metal lines extend along a same direction.

15. The method of copper hillock detecting according to claim 14, wherein the second metal lines vertically overlap the first metal lines.

16. The method of copper hillock detecting according to claim 12, wherein the second metal lines are connected to a common voltage while the first metal lines are connected to ground.

17. The method of copper hillock detecting according to claim 12, wherein a part of the second metal lines are connected to a first voltage, the other part of the second metal lines are connected to a second voltage, and the first metal lines are connected to ground.

18. The method of copper hillock detecting according to claim 17, wherein the part of the second metal lines and the other part of the second metal lines are alternatively arranged.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG. 1 schematically depicts a top view and a cross-sectional view of a testkey structure according to an embodiment of the present invention.

[0008] FIG. 2 schematically depicts a top view and a cross-sectional view of a testkey structure according to an embodiment of the present invention.

[0009] FIG. 3 schematically depicts a top view and a cross-sectional view of a testkey structure according to an embodiment of the present invention.

[0010] FIG. 4 schematically depicts a top view and a cross-sectional view of a testkey structure according to an embodiment of the present invention.

[0011] FIG. 5 schematically depicts a top view of a method of copper hillock detecting according to an embodiment of the present invention.

[0012] FIG. 6 schematically depicts a voltage versus time chart of a method of copper hillock detecting according to an embodiment of the present invention.

[0013] FIG. 7 schematically depicts a top view of a method of copper hillock detecting according to an embodiment of the present invention.

[0014] FIG. 8 schematically depicts a flow chart of a method of copper hillock detecting according to an embodiment of the present invention.

DETAILED DESCRIPTION

[0015] FIG. 8 schematically depicts a flow chart of a method of copper hillock detecting according to an embodiment of the present invention. According to step S1 of FIG. 8—disposing a testkey structure on a substrate, testkey structures are applied in the present invention for copper hillock detecting. Four testkey structures are depicted in FIGS. 1-4 as examples, but the present invention is not restricted thereto.

[0016] FIG. 1 schematically depicts a top view and a cross-sectional view of a testkey structure according to an embodiment of the present invention, wherein FIG. 1 (a) depicts a top view of a testkey structure, and FIG. 1 (b) depicts a cross-sectional view of the testkey structure along line AA′. A testkey structure 120 is disposed on a substrate 110, wherein the testkey structure 120 is disposed in a scribe line of the substrate 110. The substrate 110 may have formed thereon any type or number of integrated circuit structure such as transistors, resistors, and the like. The testkey structure 120 is not limited by particular integrated circuit structures over which it is formed, or to which metallization layers are logically connected. As such, the integrated circuit structures are not shown in the figures.

[0017] In this embodiment, the testkey structure 120 includes a lower metallization layer 122, an upper metallization layer 124, and a dielectric layer 126. The dielectric layer 126 is located between the lower metallization layer 122 and the upper metallization layer 124 for electrically isolating the lower metallization layer 122 from the upper metallization layer 124. In this case, the lower metallization layer 122 includes a plurality of first metal lines 122a/122b/122c/122d parallel to each other, and the upper metallization layer 124 includes a plurality of second metal lines 124a/124b/124c/124d parallel to each other. The first metal lines 122a/122b/122c/122d and the second metal lines 124a/124b/124c/124d are crossly arranged, wherein the first metal lines 122a/122b/122c/122d are disposed along a first direction x while the second metal lines 124a/124b/124c/124d are disposed along a second direction y.

[0018] FIG. 2 schematically depicts a top view and a cross-sectional view of a testkey structure according to an embodiment of the present invention, wherein FIG. 2 (a) depicts a top view of a testkey structure, and FIG. 2(b) depicts a cross-sectional view of the testkey structure along line BB′. A testkey structure 220 is disposed on a substrate 210. The substrate 210 may have formed thereon any type or number of integrated circuit structure such as transistors, resistors, and the like. In this embodiment, the testkey structure 220 includes a lower metallization layer 222, an upper metallization layer 224, and a dielectric layer 226. The dielectric layer 226 is located between the lower metallization layer 222 and the upper metallization layer 224 for electrically isolating the lower metallization layer 222 from the upper metallization layer 224. In this case, the lower metallization layer 222 includes a plurality of first metal lines 222a/222b/222c/222d parallel to each other, and the upper metallization layer 224 includes a plurality of second metal lines 224a/224b/224c/224d parallel to each other. The first metal lines 222a/222b/222c/222d and the second metal lines 224a/224b/224c/224d are crossly arranged. In this case, the first metal lines 222a/222b/222c/222d are disposed along the second direction y while the second metal lines 224a/224b/224c/224d are disposed along the first direction x.

[0019] FIG. 3 schematically depicts a top view and a cross-sectional view of a testkey structure according to an embodiment of the present invention, wherein FIG. 3 (a) depicts a top view of a testkey structure, and FIG. 3(b) depicts a cross-sectional view of the testkey structure along line CC′. A testkey structure 320 is disposed on a substrate 310. In this embodiment, the testkey structure 320 includes a lower metallization layer 322, an upper metallization layer 324, and a dielectric layer 326. The dielectric layer 326 is located between the lower metallization layer 322 and the upper metallization layer 324 for electrically isolating the lower metallization layer 322 from the upper metallization layer 324. In this case, the lower metallization layer 322 includes a plurality of first metal lines 322a/322b/322c/322d parallel to each other, and the upper metallization layer 324 includes a plurality of second metal lines 324a/324b/324c/324d parallel to each other. The first metal lines 322a/322b/322c/322d and the second metal lines 324a/324b/324c/324d extend along a same direction. In this case, the first metal lines 322a/322b/322c/322d and the second metal lines 324a/324b/324c/324d are disposed along the first direction x. Besides, the first metal lines 322a/322b/322c/322d overlap the second metal lines 324a/324b/324c/324d completely, but it is not limited thereto.

[0020] FIG. 4 schematically depicts a top view and a cross-sectional view of a testkey structure according to an embodiment of the present invention, wherein FIG. 4 (a) depicts a top view of a testkey structure, and FIG. 4(b) depicts a cross-sectional view of the testkey structure along line DD′. A testkey structure 420 is disposed on a substrate 410. In this embodiment, the testkey structure 420 includes a lower metallization layer 422, an upper metallization layer 424, and a dielectric layer 426. The dielectric layer 426 is located between the lower metallization layer 422 and the upper metallization layer 424 for electrically isolating the lower metallization layer 422 from the upper metallization layer 424. In this case, the lower metallization layer 422 includes a plurality of first metal lines 422a/422b/422c/422d parallel to each other, and the upper metallization layer 424 includes a plurality of second metal lines 424a/424b/424c/424d parallel to each other. The first metal lines 422a/422b/422c/422d and the second metal lines 424a/424b/424c/424d extend along a same direction. In this case, the first metal lines 422a/422b/422c/422d and the second metal lines 424a/424b/424c/424d are disposed along the second direction y. Besides, the first metal lines 422a/422b/422c/422d vertically overlap the second metal lines 424a/424b/424c/424d completely. In this case, the first metal lines 422a/422b/422c/422d overlap the second metal lines 424a/424b/424c/424d completely.

[0021] A structure test for current leakage between metal interconnect layers that may be caused by a hillock-induced electrical short is provided in the present invention.

[0022] According to step S2 of FIG. 8—applying a force voltage difference to the lower metallization layer and the upper metallization layer under a test temperature and stress time, a method of copper hillock detecting is presented as follows. FIG. 5 schematically depicts a top view of a method of copper hillock detecting according to an embodiment of the present invention. FIG. 6 schematically depicts a voltage versus time chart of a method of copper hillock detecting according to an embodiment of the present invention. Please refer to FIG. 5 and FIG. 6, the testkey structure 220 of FIG. 2 is applied in this embodiment, but it is not limited thereto.

[0023] A force voltage difference V1−G to the lower metallization layer 222 and the upper metallization layer 224 is applied under a test temperature T and stress time t. Preferably, the second metal lines 224a/224b/224c/224d are connected to a common voltage V1 while the first metal lines 222a/222b/222c/222d are connected to ground G. In a preferred embodiment, the force voltage difference V1−G is at a range of 0-400V, the test temperature is at a range of 25-300 t, and the stress time is at a range of 0.001-60 s. Ina still preferred embodiment, the force voltage difference includes a three-step voltage of a first step voltage V11, a second step voltage V12 and a third step voltage V13, wherein the second step voltage V12 is higher than the first step voltage V11 and the third step voltage V13, but the present invention is not restricted thereto. In one case, the first step voltage V11 and the third step voltage V13 is 40V, and the second step voltage V12 is 400V.

[0024] Moreover, another method of copper hillock detecting is provided. FIG. 7 schematically depicts a top view of a method of copper hillock detecting according to an embodiment of the present invention. The voltage versus time chart of FIG. 6 still can be applied in this embodiment. Please refer to FIG. 7 and FIG. 6, the testkey structure 220 of FIG. 2 is also applied in this embodiment, but it is not limited thereto.

[0025] In this embodiment, a part of the second metal lines 224a/224c are connected to a first voltage V2, the other part of the second metal lines 224b/224d are connected to a second voltage V3, and the first metal lines 222a/222b/222c/222d are connected to ground G. Thus, a force voltage difference V2-G to the lower metallization layer 222 and the second metal lines 224a/224c can be applied under the test temperature T and the stress time t as shown in FIG. 6. Or, a force voltage difference V3-G to the lower metallization layer 222 and the second metal lines 224b/224d can be applied under the test temperature T and the stress time t as shown in FIG. 6. Or, a force voltage difference V3−V2 to the second metal lines 224a/224c and the second metal lines 224b/224d can be applied under the test temperature T and the stress time t as shown in FIG. 6. In this case, the second metal lines 224a/224c and the second metal lines 224b/224d are alternatively arranged, but it is not limited thereto.

[0026] Then, according to step S3 of FIG. 8—detecting a changed sensing voltage difference to the lower metallization layer and the upper metallization layer for detecting copper hillock, a changed sensing voltage difference of the force voltage difference V1−G of FIG. 5, the force voltage difference V2−G of FIG. 7, the force voltage difference V3−G of FIG. 7, or the force voltage difference V3−V2 of FIG. 7, can be detected for detecting copper hillock.

[0027] In the present invention, according to step S4 of FIG. 8 —performing a regular integrated circuit fabricating process on the substrate, a regular integrated circuit fabricating process is performed on the substrate 110 after the changed sensing voltage difference of the force voltage difference V1−G/V2−G/V3−G/V3−V2 is detected. According to step S5 of FIG. 8—processing a mass production after the changed sensing voltage difference is detected within a pre-determined voltage range, a mass production is processed after the changed sensing voltage difference V1−G/V2−G/V3−G/V3−V2 is detected within a pre-determined voltage range. Or, according to step S6 of FIG. 8—optimizing the regular integrated circuit fabricating process after the changed sensing voltage difference is detected out of a pre-determined voltage range, the regular integrated circuit fabricating process is optimized after the changed sensing voltage difference V1−G/V2−G/V3−G/V3−V2 is detected out of a pre-determined voltage range.

[0028] To summarize, the present invention provides a method of copper hillock detecting, which disposes a testkey structure including a lower metallization layer, an upper metallization layer, and a dielectric layer between the lower metallization layer and the upper metallization layer on a substrate, applies a force voltage difference to the lower metallization layer and the upper metallization layer under a test temperature and stress time, and detects a changed sensing voltage difference to the lower metallization layer and the upper metallization layer for detecting copper hillock. Therefore, copper hillock between the lower metallization layer and the upper metallization layer, or between metal lines of the lower metallization layer or between metal lines of the upper metallization layer can be detected before mass production is processed.

[0029] Preferably, the force voltage difference is at a range of 0-400V, the test temperature is at a range of 25-300° C., and the stress time is at a range of 0.001-60 s. Still preferably, the force voltage difference includes a three-step voltage of a first step voltage, a second step voltage and a third step voltage, wherein the second step voltage is higher than the first step voltage and the third step voltage.

[0030] The lower metallization layer includes a plurality of first metal lines parallel to each other, and the upper metallization layer includes a plurality of second metal lines parallel to each other, wherein the first metal lines and the second metal lines may be crossly arranged or extend along a same direction.

[0031] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.